Searched refs:dbus_mask (Results 1 – 6 of 6) sorted by relevance
| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | cache_ll.h | 121 uint32_t dbus_mask = 0; in cache_ll_l1_enable_bus() local
122 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; in cache_ll_l1_enable_bus()
123 dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0; in cache_ll_l1_enable_bus()
124 dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0; in cache_ll_l1_enable_bus()
125 REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_enable_bus()
145 uint32_t dbus_mask = 0; in cache_ll_l1_disable_bus() local
146 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; in cache_ll_l1_disable_bus()
147 dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0; in cache_ll_l1_disable_bus()
148 dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0; in cache_ll_l1_disable_bus()
149 REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | cache_ll.h | 118 uint32_t dbus_mask = 0; in cache_ll_l1_enable_bus() local
120 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_enable_bus()
122 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_enable_bus()
124 REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_enable_bus()
148 uint32_t dbus_mask = REG_READ(EXTMEM_DCACHE_CTRL1_REG); in cache_ll_l1_get_enabled_bus() local
150 mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()
152 mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()
179 uint32_t dbus_mask = 0; in cache_ll_l1_disable_bus() local
181 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_disable_bus()
183 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | cache_ll.h | 76 uint32_t dbus_mask = 0; in cache_ll_l1_enable_bus() local
77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; in cache_ll_l1_enable_bus()
78 REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); in cache_ll_l1_enable_bus()
98 uint32_t dbus_mask = 0; in cache_ll_l1_disable_bus() local
99 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; in cache_ll_l1_disable_bus()
100 REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | cache_ll.h | 76 uint32_t dbus_mask = 0; in cache_ll_l1_enable_bus() local
77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
78 REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); in cache_ll_l1_enable_bus()
98 uint32_t dbus_mask = 0; in cache_ll_l1_disable_bus() local
99 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
100 REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | cache_ll.h | 102 uint32_t dbus_mask = 0; in cache_ll_l1_enable_bus() local
103 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
104 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_enable_bus()
124 uint32_t dbus_mask = 0; in cache_ll_l1_disable_bus() local
125 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
126 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | cache_ll.h | 103 uint32_t dbus_mask = 0; in cache_ll_l1_enable_bus() local
104 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
105 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_enable_bus()
125 uint32_t dbus_mask = 0; in cache_ll_l1_disable_bus() local
126 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
127 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_disable_bus()
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