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Searched refs:ctrl (Results 1 – 25 of 73) sorted by relevance

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/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dspimem_flash_ll.h49 dev->ctrl.val = 0; in spimem_flash_ll_reset()
81 dev->ctrl.val = 0; in spimem_flash_ll_erase_sector()
370 typeof (dev->ctrl) ctrl = dev->ctrl; in spimem_flash_ll_set_read_mode()
371 …ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUA… in spimem_flash_ll_set_read_mode()
373 ctrl.val |= SPI_MEM_FASTRD_MODE_M; in spimem_flash_ll_set_read_mode()
379 ctrl.fread_qio = 1; in spimem_flash_ll_set_read_mode()
382 ctrl.fread_quad = 1; in spimem_flash_ll_set_read_mode()
385 ctrl.fread_dio = 1; in spimem_flash_ll_set_read_mode()
388 ctrl.fread_dual = 1; in spimem_flash_ll_set_read_mode()
391 ctrl.fastrd_mode = 0; in spimem_flash_ll_set_read_mode()
[all …]
Dgpspi_flash_ll.h54 dev->ctrl.val = 0; in gpspi_flash_ll_reset()
155 dev->ctrl.hold_pol = pol_val; in gpspi_flash_ll_set_hold_pol()
208 typeof (dev->ctrl) ctrl = dev->ctrl; in gpspi_flash_ll_set_read_mode()
211 …ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_… in gpspi_flash_ll_set_read_mode()
220 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
221 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
225 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
229 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
230 ctrl.faddr_dual = 1; in gpspi_flash_ll_set_read_mode()
234 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
[all …]
Dadc_ll.h182 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
215 APB_SARADC.ctrl.work_mode = 0; in adc_ll_digi_set_convert_mode()
216 APB_SARADC.ctrl.sar_sel = 0; in adc_ll_digi_set_convert_mode()
218 APB_SARADC.ctrl.work_mode = 0; in adc_ll_digi_set_convert_mode()
219 APB_SARADC.ctrl.sar_sel = 1; in adc_ll_digi_set_convert_mode()
221 APB_SARADC.ctrl.work_mode = 1; in adc_ll_digi_set_convert_mode()
223 APB_SARADC.ctrl.work_mode = 2; in adc_ll_digi_set_convert_mode()
225 APB_SARADC.ctrl.data_sar_sel = 1; in adc_ll_digi_set_convert_mode()
240 APB_SARADC.ctrl.sar1_patt_len = patt_len - 1; in adc_ll_digi_set_pattern_table_len()
242 APB_SARADC.ctrl.sar2_patt_len = patt_len - 1; in adc_ll_digi_set_pattern_table_len()
[all …]
Dspi_ll.h155 hw->ctrl.val = 0; in spi_ll_slave_init()
182 hw->ctrl.val = 0; in spi_ll_slave_hd_init()
198 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
488 hw->ctrl.wr_bit_order = lsbfirst; in spi_ll_set_tx_lsbfirst()
499 hw->ctrl.rd_bit_order = lsbfirst; in spi_ll_set_rx_lsbfirst()
590 hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; in spi_ll_master_set_line_mode()
592 hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); in spi_ll_master_set_line_mode()
593 hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); in spi_ll_master_set_line_mode()
594 hw->ctrl.fcmd_oct = (line_mode.cmd_lines == 8); in spi_ll_master_set_line_mode()
595 hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); in spi_ll_master_set_line_mode()
[all …]
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dgpspi_flash_ll.h49 dev->ctrl.val = 0; in gpspi_flash_ll_reset()
150 dev->ctrl.hold_pol = pol_val; in gpspi_flash_ll_set_hold_pol()
203 typeof (dev->ctrl) ctrl = dev->ctrl; in gpspi_flash_ll_set_read_mode()
206 …ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_… in gpspi_flash_ll_set_read_mode()
215 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
220 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
224 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
225 ctrl.faddr_dual = 1; in gpspi_flash_ll_set_read_mode()
229 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
[all …]
Dspimem_flash_ll.h51 dev->ctrl.val = 0; in spimem_flash_ll_reset()
83 dev->ctrl.val = 0; in spimem_flash_ll_erase_sector()
376 typeof (dev->ctrl) ctrl = dev->ctrl; in spimem_flash_ll_set_read_mode()
377 …ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUA… in spimem_flash_ll_set_read_mode()
378 ctrl.val |= SPI_MEM_FASTRD_MODE_M; in spimem_flash_ll_set_read_mode()
384 ctrl.fread_qio = 1; in spimem_flash_ll_set_read_mode()
387 ctrl.fread_quad = 1; in spimem_flash_ll_set_read_mode()
390 ctrl.fread_dio = 1; in spimem_flash_ll_set_read_mode()
393 ctrl.fread_dual = 1; in spimem_flash_ll_set_read_mode()
396 ctrl.fastrd_mode = 0; in spimem_flash_ll_set_read_mode()
[all …]
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dgpspi_flash_ll.h48 dev->ctrl.val = 0; in gpspi_flash_ll_reset()
67 dev->ctrl.hold_pol = pol_val; in gpspi_flash_ll_set_hold_pol()
147 dev->ctrl.hold_pol = 1; in gpspi_flash_ll_user_start()
203 typeof (dev->ctrl) ctrl = dev->ctrl; in gpspi_flash_ll_set_read_mode()
206 …ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_… in gpspi_flash_ll_set_read_mode()
215 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
220 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
224 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
225 ctrl.faddr_dual = 1; in gpspi_flash_ll_set_read_mode()
[all …]
Dspimem_flash_ll.h49 dev->ctrl.val = 0; in spimem_flash_ll_reset()
81 dev->ctrl.val = 0; in spimem_flash_ll_erase_sector()
374 typeof (dev->ctrl) ctrl = dev->ctrl; in spimem_flash_ll_set_read_mode()
375 …ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUA… in spimem_flash_ll_set_read_mode()
376 ctrl.val |= SPI_MEM_FASTRD_MODE_M; in spimem_flash_ll_set_read_mode()
382 ctrl.fread_qio = 1; in spimem_flash_ll_set_read_mode()
385 ctrl.fread_quad = 1; in spimem_flash_ll_set_read_mode()
388 ctrl.fread_dio = 1; in spimem_flash_ll_set_read_mode()
391 ctrl.fread_dual = 1; in spimem_flash_ll_set_read_mode()
394 ctrl.fastrd_mode = 0; in spimem_flash_ll_set_read_mode()
[all …]
Dspi_ll.h153 hw->ctrl.val = 0; in spi_ll_slave_init()
180 hw->ctrl.val = 0; in spi_ll_slave_hd_init()
196 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
486 hw->ctrl.wr_bit_order = lsbfirst; in spi_ll_set_tx_lsbfirst()
497 hw->ctrl.rd_bit_order = lsbfirst; in spi_ll_set_rx_lsbfirst()
588 hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; in spi_ll_master_set_line_mode()
590 hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); in spi_ll_master_set_line_mode()
591 hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); in spi_ll_master_set_line_mode()
592 hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); in spi_ll_master_set_line_mode()
593 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
[all …]
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dgpspi_flash_ll.h49 dev->ctrl.val = 0; in gpspi_flash_ll_reset()
150 dev->ctrl.hold_pol = pol_val; in gpspi_flash_ll_set_hold_pol()
203 typeof (dev->ctrl) ctrl = dev->ctrl; in gpspi_flash_ll_set_read_mode()
206 …ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_… in gpspi_flash_ll_set_read_mode()
215 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
220 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
224 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
225 ctrl.faddr_dual = 1; in gpspi_flash_ll_set_read_mode()
229 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
[all …]
Dspimem_flash_ll.h49 dev->ctrl.val = 0; in spimem_flash_ll_reset()
81 dev->ctrl.val = 0; in spimem_flash_ll_erase_sector()
374 typeof (dev->ctrl) ctrl = dev->ctrl; in spimem_flash_ll_set_read_mode()
375 …ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUA… in spimem_flash_ll_set_read_mode()
376 ctrl.val |= SPI_MEM_FASTRD_MODE_M; in spimem_flash_ll_set_read_mode()
382 ctrl.fread_qio = 1; in spimem_flash_ll_set_read_mode()
385 ctrl.fread_quad = 1; in spimem_flash_ll_set_read_mode()
388 ctrl.fread_dio = 1; in spimem_flash_ll_set_read_mode()
391 ctrl.fread_dual = 1; in spimem_flash_ll_set_read_mode()
394 ctrl.fastrd_mode = 0; in spimem_flash_ll_set_read_mode()
[all …]
Dadc_ll.h149 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
197 APB_SARADC.ctrl.sar_patt_len = patt_len - 1; in adc_ll_digi_set_pattern_table_len()
231 APB_SARADC.ctrl.sar_patt_p_clear = 1; in adc_ll_digi_clear_pattern_table()
232 APB_SARADC.ctrl.sar_patt_p_clear = 0; in adc_ll_digi_clear_pattern_table()
243 APB_SARADC.ctrl.wait_arb_cycle = cycle; in adc_ll_digi_set_arbiter_stable_cycle()
313 APB_SARADC.ctrl.sar_clk_gated = 1; in adc_ll_digi_clk_sel()
321 APB_SARADC.ctrl.sar_clk_gated = 0; in adc_ll_digi_controller_clk_disable()
525 APB_SARADC.ctrl.sar_clk_gated = 1; in adc_ll_digi_set_power_manage()
526 APB_SARADC.ctrl.xpd_sar_force = 3; in adc_ll_digi_set_power_manage()
528 APB_SARADC.ctrl.sar_clk_gated = 1; in adc_ll_digi_set_power_manage()
[all …]
Dspi_ll.h153 hw->ctrl.val = 0; in spi_ll_slave_init()
180 hw->ctrl.val = 0; in spi_ll_slave_hd_init()
196 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
486 hw->ctrl.wr_bit_order = lsbfirst; in spi_ll_set_tx_lsbfirst()
497 hw->ctrl.rd_bit_order = lsbfirst; in spi_ll_set_rx_lsbfirst()
588 hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; in spi_ll_master_set_line_mode()
590 hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); in spi_ll_master_set_line_mode()
591 hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); in spi_ll_master_set_line_mode()
592 hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); in spi_ll_master_set_line_mode()
593 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
[all …]
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dgpspi_flash_ll.h54 dev->ctrl.val = 0; in gpspi_flash_ll_reset()
201 typeof (dev->ctrl) ctrl = dev->ctrl; in gpspi_flash_ll_set_read_mode()
204 …ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_… in gpspi_flash_ll_set_read_mode()
213 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
214 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
218 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
222 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
223 ctrl.faddr_dual = 1; in gpspi_flash_ll_set_read_mode()
227 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
234 dev->ctrl = ctrl; in gpspi_flash_ll_set_read_mode()
[all …]
Dspimem_flash_ll.h49 dev->ctrl.val = 0; in spimem_flash_ll_reset()
81 dev->ctrl.val = 0; in spimem_flash_ll_erase_sector()
370 typeof (dev->ctrl) ctrl = dev->ctrl; in spimem_flash_ll_set_read_mode()
371 …ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUA… in spimem_flash_ll_set_read_mode()
372 ctrl.val |= SPI_MEM_FASTRD_MODE_M; in spimem_flash_ll_set_read_mode()
378 ctrl.fread_qio = 1; in spimem_flash_ll_set_read_mode()
381 ctrl.fread_quad = 1; in spimem_flash_ll_set_read_mode()
384 ctrl.fread_dio = 1; in spimem_flash_ll_set_read_mode()
387 ctrl.fread_dual = 1; in spimem_flash_ll_set_read_mode()
390 ctrl.fastrd_mode = 0; in spimem_flash_ll_set_read_mode()
[all …]
Dadc_ll.h172 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
206 APB_SARADC.ctrl.work_mode = 0; in adc_ll_digi_set_convert_mode()
207 APB_SARADC.ctrl.sar_sel = 0; in adc_ll_digi_set_convert_mode()
208 APB_SARADC.ctrl.data_sar_sel = 0; in adc_ll_digi_set_convert_mode()
210 APB_SARADC.ctrl.work_mode = 0; in adc_ll_digi_set_convert_mode()
211 APB_SARADC.ctrl.sar_sel = 1; in adc_ll_digi_set_convert_mode()
212 APB_SARADC.ctrl.data_sar_sel = 0; in adc_ll_digi_set_convert_mode()
214 APB_SARADC.ctrl.work_mode = 1; in adc_ll_digi_set_convert_mode()
215 APB_SARADC.ctrl.data_sar_sel = 1; in adc_ll_digi_set_convert_mode()
217 APB_SARADC.ctrl.work_mode = 2; in adc_ll_digi_set_convert_mode()
[all …]
Dspi_ll.h148 hw->ctrl.val = 0; in spi_ll_slave_init()
169 hw->ctrl.val = 0; in spi_ll_slave_hd_init()
186 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
450 hw->ctrl.wr_bit_order = lsbfirst; in spi_ll_set_tx_lsbfirst()
461 hw->ctrl.rd_bit_order = lsbfirst; in spi_ll_set_rx_lsbfirst()
552 hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; in spi_ll_master_set_line_mode()
554 hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); in spi_ll_master_set_line_mode()
555 hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); in spi_ll_master_set_line_mode()
556 hw->ctrl.fcmd_oct = (line_mode.cmd_lines == 8); in spi_ll_master_set_line_mode()
557 hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); in spi_ll_master_set_line_mode()
[all …]
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dgpspi_flash_ll.h49 dev->ctrl.val = 0; in gpspi_flash_ll_reset()
150 dev->ctrl.hold_pol = pol_val; in gpspi_flash_ll_set_hold_pol()
203 typeof (dev->ctrl) ctrl = dev->ctrl; in gpspi_flash_ll_set_read_mode()
206 …ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_… in gpspi_flash_ll_set_read_mode()
215 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
216 ctrl.faddr_quad = 1; in gpspi_flash_ll_set_read_mode()
220 ctrl.fread_quad = 1; in gpspi_flash_ll_set_read_mode()
224 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
225 ctrl.faddr_dual = 1; in gpspi_flash_ll_set_read_mode()
229 ctrl.fread_dual = 1; in gpspi_flash_ll_set_read_mode()
[all …]
Dspimem_flash_ll.h50 dev->ctrl.val = 0; in spimem_flash_ll_reset()
82 dev->ctrl.val = 0; in spimem_flash_ll_erase_sector()
375 typeof (dev->ctrl) ctrl = dev->ctrl; in spimem_flash_ll_set_read_mode()
376 …ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUA… in spimem_flash_ll_set_read_mode()
377 ctrl.val |= SPI_MEM_FASTRD_MODE_M; in spimem_flash_ll_set_read_mode()
383 ctrl.fread_qio = 1; in spimem_flash_ll_set_read_mode()
386 ctrl.fread_quad = 1; in spimem_flash_ll_set_read_mode()
389 ctrl.fread_dio = 1; in spimem_flash_ll_set_read_mode()
392 ctrl.fread_dual = 1; in spimem_flash_ll_set_read_mode()
395 ctrl.fastrd_mode = 0; in spimem_flash_ll_set_read_mode()
[all …]
Dspi_ll.h157 hw->ctrl.val = 0; in spi_ll_slave_init()
184 hw->ctrl.val = 0; in spi_ll_slave_hd_init()
200 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
490 hw->ctrl.wr_bit_order = lsbfirst; in spi_ll_set_tx_lsbfirst()
501 hw->ctrl.rd_bit_order = lsbfirst; in spi_ll_set_rx_lsbfirst()
592 hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; in spi_ll_master_set_line_mode()
594 hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); in spi_ll_master_set_line_mode()
595 hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); in spi_ll_master_set_line_mode()
596 hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); in spi_ll_master_set_line_mode()
597 hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); in spi_ll_master_set_line_mode()
[all …]
/hal_espressif-latest/components/hal/esp32/include/hal/
Dspi_flash_ll.h65 dev->ctrl.val = 0; in spi_flash_ll_reset()
97 dev->ctrl.val = 0; in spi_flash_ll_erase_sector()
245 typeof (dev->ctrl) ctrl = dev->ctrl; in spi_flash_ll_set_read_mode()
246 ctrl.val &= ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M); in spi_flash_ll_set_read_mode()
247 ctrl.val |= SPI_FASTRD_MODE_M; in spi_flash_ll_set_read_mode()
253 ctrl.fread_qio = 1; in spi_flash_ll_set_read_mode()
256 ctrl.fread_quad = 1; in spi_flash_ll_set_read_mode()
259 ctrl.fread_dio = 1; in spi_flash_ll_set_read_mode()
262 ctrl.fread_dual = 1; in spi_flash_ll_set_read_mode()
265 ctrl.fastrd_mode = 0; in spi_flash_ll_set_read_mode()
[all …]
Dspi_ll.h99 hw->ctrl.val = 0; in spi_ll_slave_init()
328 hw->ctrl.wr_bit_order = lsbfirst; in spi_ll_set_tx_lsbfirst()
339 hw->ctrl.rd_bit_order = lsbfirst; in spi_ll_set_rx_lsbfirst()
461 hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; in spi_ll_master_set_line_mode()
470 hw->ctrl.fread_dual = 1; in spi_ll_master_set_line_mode()
474 hw->ctrl.fread_dio = 1; in spi_ll_master_set_line_mode()
479 hw->ctrl.fastrd_mode = 1; in spi_ll_master_set_line_mode()
484 hw->ctrl.fread_quad = 1; in spi_ll_master_set_line_mode()
488 hw->ctrl.fread_qio = 1; in spi_ll_master_set_line_mode()
493 hw->ctrl.fastrd_mode = 1; in spi_ll_master_set_line_mode()
/hal_espressif-latest/components/bt/host/bluedroid/btc/profile/std/a2dp/
Dbtc_a2dp_control.c93 void btc_a2dp_control_media_ctrl(esp_a2d_media_ctrl_t ctrl) in btc_a2dp_control_media_ctrl() argument
95 APPL_TRACE_DEBUG("BTC MEDIA (A2DP-DATA) EVENT %u", ctrl); in btc_a2dp_control_media_ctrl()
99 a2dp_cmd_acknowledge(ctrl, ESP_A2D_MEDIA_CTRL_ACK_BUSY); in btc_a2dp_control_media_ctrl()
103 btc_aa_ctrl_cb.a2dp_cmd_pending = ctrl; in btc_a2dp_control_media_ctrl()
105 switch (ctrl) { in btc_a2dp_control_media_ctrl()
179 APPL_TRACE_ERROR("### A2DP-MEDIA EVENT %u NOT HANDLED ###", ctrl); in btc_a2dp_control_media_ctrl()
/hal_espressif-latest/components/esp_rom/include/esp32s3/rom/usb/
Dcdc_acm.h169 int cdc_acm_line_ctrl_set(cdc_acm_device *dev, uint32_t ctrl, uint32_t val);
180 int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val);
/hal_espressif-latest/components/esp_rom/include/esp32s2/rom/usb/
Dcdc_acm.h168 int cdc_acm_line_ctrl_set(cdc_acm_device *dev, uint32_t ctrl, uint32_t val);
179 int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val);

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