Searched refs:conf_ch (Results 1 – 4 of 4) sorted by relevance
51 dev->conf_ch[0].conf0.clk_en = enable; // register clock gating in rmt_ll_enable_periph_clock()71 dev->conf_ch[0].conf0.mem_pd = 1; in rmt_ll_mem_force_power_off()81 dev->conf_ch[0].conf0.mem_pd = 0; in rmt_ll_mem_power_by_pmu()113 dev->conf_ch[channel].conf1.ref_always_on = 1; in rmt_ll_set_group_clock_src()116 dev->conf_ch[channel].conf1.ref_always_on = 0; in rmt_ll_set_group_clock_src()150 dev->conf_ch[i].conf1.ref_cnt_rst = 1; in rmt_ll_tx_reset_channels_clock_div()169 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); in rmt_ll_tx_set_channel_clock_div()181 dev->conf_ch[channel].conf1.mem_rd_rst = 1; in rmt_ll_tx_reset_pointer()182 dev->conf_ch[channel].conf1.mem_rd_rst = 0; in rmt_ll_tx_reset_pointer()183 dev->conf_ch[channel].conf1.apb_mem_rst = 1; in rmt_ll_tx_reset_pointer()[all …]
119 dev->conf_ch[channel].conf1.ref_always_on_chn = 1; in rmt_ll_set_group_clock_src()122 dev->conf_ch[channel].conf1.ref_always_on_chn = 0; in rmt_ll_set_group_clock_src()172 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn, div); in rmt_ll_tx_set_channel_clock_div()184 dev->conf_ch[channel].conf1.mem_rd_rst_chn = 1; in rmt_ll_tx_reset_pointer()185 dev->conf_ch[channel].conf1.mem_rd_rst_chn = 0; in rmt_ll_tx_reset_pointer()186 dev->conf_ch[channel].conf1.apb_mem_rst_chn = 1; in rmt_ll_tx_reset_pointer()187 dev->conf_ch[channel].conf1.apb_mem_rst_chn = 0; in rmt_ll_tx_reset_pointer()199 dev->conf_ch[channel].conf1.tx_start_chn = 1; in rmt_ll_tx_start()211 dev->conf_ch[channel].conf1.tx_stop_chn = 1; in rmt_ll_tx_stop()223 dev->conf_ch[channel].conf0.mem_size_chn = block_num; in rmt_ll_tx_set_mem_blocks()[all …]
50 } conf_ch[8]; member
780 } conf_ch[4]; member
