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Searched refs:conf1 (Results 1 – 25 of 71) sorted by relevance

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/hal_espressif-latest/components/hal/esp32/include/hal/
Drmt_ll.h113 dev->conf_ch[channel].conf1.ref_always_on = 1; in rmt_ll_set_group_clock_src()
116 dev->conf_ch[channel].conf1.ref_always_on = 0; in rmt_ll_set_group_clock_src()
150 dev->conf_ch[i].conf1.ref_cnt_rst = 1; in rmt_ll_tx_reset_channels_clock_div()
181 dev->conf_ch[channel].conf1.mem_rd_rst = 1; in rmt_ll_tx_reset_pointer()
182 dev->conf_ch[channel].conf1.mem_rd_rst = 0; in rmt_ll_tx_reset_pointer()
183 dev->conf_ch[channel].conf1.apb_mem_rst = 1; in rmt_ll_tx_reset_pointer()
184 dev->conf_ch[channel].conf1.apb_mem_rst = 0; in rmt_ll_tx_reset_pointer()
196 dev->conf_ch[channel].conf1.tx_start = 1; in rmt_ll_tx_start()
233 dev->conf_ch[channel].conf1.tx_conti_mode = enable; in rmt_ll_tx_enable_loop()
247 dev->conf_ch[channel].conf1.idle_out_en = enable; in rmt_ll_tx_fix_idle_level()
[all …]
Duart_ll.h398 hw->conf1.rxfifo_full_thrhd = full_thrhd; in uart_ll_set_rxfifo_full_thr()
412 hw->conf1.txfifo_empty_thrhd = empty_thrhd; in uart_ll_set_txfifo_empty_thr()
473 hw->conf1.rx_flow_thrhd = rx_thrs; in uart_ll_set_hw_flow_ctrl()
474 hw->conf1.rx_flow_en = 1; in uart_ll_set_hw_flow_ctrl()
476 hw->conf1.rx_flow_en = 0; in uart_ll_set_hw_flow_ctrl()
496 if(hw->conf1.rx_flow_en) { in uart_ll_get_hw_flow_ctrl()
795 return hw->conf1.rx_flow_en; in uart_ll_is_hw_rts_en()
866 hw->conf1.rx_tout_thrhd = tout_thr; in uart_ll_set_rx_tout()
867 hw->conf1.rx_tout_en = 1; in uart_ll_set_rx_tout()
869 hw->conf1.rx_tout_en = 0; in uart_ll_set_rx_tout()
[all …]
Dledc_ll.h330 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc = duty_direction; in ledc_ll_set_duty_direction()
345 *duty_direction = hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc; in ledc_ll_get_duty_direction()
360 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num; in ledc_ll_set_duty_num()
375 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle; in ledc_ll_set_duty_cycle()
390 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_scale = duty_scale; in ledc_ll_set_duty_scale()
420 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; in ledc_ll_set_duty_start()
Dpcnt_ll.h281 typeof(hw->conf_unit[unit].conf1) conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_set_thres_value()
287 hw->conf_unit[unit].conf1 = conf1_reg; in pcnt_ll_set_thres_value()
329 typeof(hw->conf_unit[unit].conf1) conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_get_thres_value()
Dsdio_slave_ll.h88 slc->conf1.slc0_rx_stitch_en = 0; in sdio_slave_ll_init()
89 slc->conf1.slc0_tx_stitch_en = 0; in sdio_slave_ll_init()
90 slc->conf1.slc0_len_auto_clr = 0; in sdio_slave_ll_init()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Drmt_ll.h119 dev->conf_ch[channel].conf1.ref_always_on_chn = 1; in rmt_ll_set_group_clock_src()
122 dev->conf_ch[channel].conf1.ref_always_on_chn = 0; in rmt_ll_set_group_clock_src()
184 dev->conf_ch[channel].conf1.mem_rd_rst_chn = 1; in rmt_ll_tx_reset_pointer()
185 dev->conf_ch[channel].conf1.mem_rd_rst_chn = 0; in rmt_ll_tx_reset_pointer()
186 dev->conf_ch[channel].conf1.apb_mem_rst_chn = 1; in rmt_ll_tx_reset_pointer()
187 dev->conf_ch[channel].conf1.apb_mem_rst_chn = 0; in rmt_ll_tx_reset_pointer()
199 dev->conf_ch[channel].conf1.tx_start_chn = 1; in rmt_ll_tx_start()
211 dev->conf_ch[channel].conf1.tx_stop_chn = 1; in rmt_ll_tx_stop()
248 dev->conf_ch[channel].conf1.tx_conti_mode_chn = enable; in rmt_ll_tx_enable_loop()
345 dev->conf_ch[channel].conf1.idle_out_en_chn = enable; in rmt_ll_tx_fix_idle_level()
[all …]
Duart_ll.h368 hw->conf1.rxfifo_full_thrhd = full_thrhd; in uart_ll_set_rxfifo_full_thr()
382 hw->conf1.txfifo_empty_thrhd = empty_thrhd; in uart_ll_set_txfifo_empty_thr()
444 hw->conf1.rx_flow_en = 1; in uart_ll_set_hw_flow_ctrl()
446 hw->conf1.rx_flow_en = 0; in uart_ll_set_hw_flow_ctrl()
466 if(hw->conf1.rx_flow_en) { in uart_ll_get_hw_flow_ctrl()
762 return hw->conf1.rx_flow_en; in uart_ll_is_hw_rts_en()
827 hw->conf1.rx_tout_en = 1; in uart_ll_set_rx_tout()
829 hw->conf1.rx_tout_en = 0; in uart_ll_set_rx_tout()
843 if(hw->conf1.rx_tout_en > 0) { in uart_ll_get_rx_tout_thr()
Dledc_ll.h347 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc = duty_direction; in ledc_ll_set_duty_direction()
362 *duty_direction = hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc; in ledc_ll_get_duty_direction()
377 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num; in ledc_ll_set_duty_num()
392 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle; in ledc_ll_set_duty_cycle()
407 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_scale = duty_scale; in ledc_ll_set_duty_scale()
437 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; in ledc_ll_set_duty_start()
Dpcnt_ll.h280 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_set_thres_value()
286 hw->conf_unit[unit].conf1 = conf1_reg; in pcnt_ll_set_thres_value()
328 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_get_thres_value()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Drmt_ll.h490 dev->chmconf[channel].conf1.mem_wr_rst_chm = 1; in rmt_ll_rx_reset_pointer()
491 dev->chmconf[channel].conf1.mem_wr_rst_chm = 0; in rmt_ll_rx_reset_pointer()
492 dev->chmconf[channel].conf1.apb_mem_rst_chm = 1; in rmt_ll_rx_reset_pointer()
493 dev->chmconf[channel].conf1.apb_mem_rst_chm = 0; in rmt_ll_rx_reset_pointer()
519 dev->chmconf[channel].conf1.rx_en_chm = enable; in rmt_ll_rx_enable()
521 dev->chmconf[channel].conf1.conf_update_chm = 1; in rmt_ll_rx_enable()
559 dev->chmconf[channel].conf1.mem_owner_chm = owner; in rmt_ll_rx_set_mem_owner()
572 dev->chmconf[channel].conf1.rx_filter_en_chm = enable; in rmt_ll_rx_enable_filter()
585 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_chm, thres); in rmt_ll_rx_set_filter_thres()
661 dev->chmconf[channel].conf1.mem_rx_wrap_en_chm = enable; in rmt_ll_rx_enable_wrap()
[all …]
Dledc_ll.h333 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc = duty_direction; in ledc_ll_set_duty_direction()
348 *duty_direction = hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc; in ledc_ll_get_duty_direction()
363 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num; in ledc_ll_set_duty_num()
378 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle; in ledc_ll_set_duty_cycle()
393 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_scale = duty_scale; in ledc_ll_set_duty_scale()
423 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; in ledc_ll_set_duty_start()
Duart_ll.h412 hw->conf1.rxfifo_full_thrhd = full_thrhd; in uart_ll_set_rxfifo_full_thr()
426 hw->conf1.txfifo_empty_thrhd = empty_thrhd; in uart_ll_set_txfifo_empty_thr()
487 hw->conf1.rx_flow_en = 1; in uart_ll_set_hw_flow_ctrl()
489 hw->conf1.rx_flow_en = 0; in uart_ll_set_hw_flow_ctrl()
509 if (hw->conf1.rx_flow_en) { in uart_ll_get_hw_flow_ctrl()
806 return hw->conf1.rx_flow_en; in uart_ll_is_hw_rts_en()
871 hw->conf1.rx_tout_en = 1; in uart_ll_set_rx_tout()
873 hw->conf1.rx_tout_en = 0; in uart_ll_set_rx_tout()
887 if(hw->conf1.rx_tout_en > 0) { in uart_ll_get_rx_tout_thr()
Dgdma_ll.h110 dev->channel[channel].in.conf1.in_check_owner = enable; in gdma_ll_rx_enable_owner_check()
145 dev->channel[channel].in.conf1.in_ext_mem_bk_size = size_index; in gdma_ll_rx_set_block_size_psram()
153 dev->channel[channel].in.conf1.dma_infifo_full_thrs = water_mark; in gdma_ll_rx_set_water_mark()
358 dev->channel[channel].out.conf1.out_check_owner = enable; in gdma_ll_tx_enable_owner_check()
409 dev->channel[channel].out.conf1.out_ext_mem_bk_size = size_index; in gdma_ll_tx_set_block_size_psram()
Dpcnt_ll.h280 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_set_thres_value()
286 hw->conf_unit[unit].conf1 = conf1_reg; in pcnt_ll_set_thres_value()
328 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_get_thres_value()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Drmt_ll.h480 dev->chmconf[channel].conf1.mem_wr_rst_chm = 1; in rmt_ll_rx_reset_pointer()
481 dev->chmconf[channel].conf1.mem_wr_rst_chm = 0; in rmt_ll_rx_reset_pointer()
482 dev->chmconf[channel].conf1.apb_mem_rst_chm = 1; in rmt_ll_rx_reset_pointer()
483 dev->chmconf[channel].conf1.apb_mem_rst_chm = 0; in rmt_ll_rx_reset_pointer()
496 dev->chmconf[channel].conf1.rx_en_chm = enable; in rmt_ll_rx_enable()
498 dev->chmconf[channel].conf1.conf_update_chm = 1; in rmt_ll_rx_enable()
536 dev->chmconf[channel].conf1.mem_owner_chm = owner; in rmt_ll_rx_set_mem_owner()
549 dev->chmconf[channel].conf1.rx_filter_en_chm = enable; in rmt_ll_rx_enable_filter()
562 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_chm, thres); in rmt_ll_rx_set_filter_thres()
638 dev->chmconf[channel].conf1.mem_rx_wrap_en_chm = enable; in rmt_ll_rx_enable_wrap()
[all …]
Dpcnt_ll.h280 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_set_thres_value()
286 hw->conf_unit[unit].conf1 = conf1_reg; in pcnt_ll_set_thres_value()
328 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_get_thres_value()
Duart_ll.h456 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd); in uart_ll_set_rxfifo_full_thr()
470 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd); in uart_ll_set_txfifo_empty_thr()
652 hw->conf1.sw_dtr = level & 0x1; in uart_ll_set_dtr_active_level()
928 typeof(hw->conf1) conf1_reg; in uart_ll_inverse_signal()
929 conf1_reg.val = hw->conf1.val; in uart_ll_inverse_signal()
934 hw->conf1.val = conf1_reg.val; in uart_ll_inverse_signal()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Drmt_ll.h465 dev->rx_conf[channel].conf1.mem_wr_rst = 1; in rmt_ll_rx_reset_pointer()
466 dev->rx_conf[channel].conf1.mem_wr_rst = 0; in rmt_ll_rx_reset_pointer()
467 dev->rx_conf[channel].conf1.mem_rst = 1; in rmt_ll_rx_reset_pointer()
468 dev->rx_conf[channel].conf1.mem_rst = 0; in rmt_ll_rx_reset_pointer()
481 dev->rx_conf[channel].conf1.rx_en = enable; in rmt_ll_rx_enable()
483 dev->rx_conf[channel].conf1.conf_update = 1; in rmt_ll_rx_enable()
521 dev->rx_conf[channel].conf1.mem_owner = owner; in rmt_ll_rx_set_mem_owner()
534 dev->rx_conf[channel].conf1.rx_filter_en = enable; in rmt_ll_rx_enable_filter()
547 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf1, rx_filter_thres, thres); in rmt_ll_rx_set_filter_thres()
623 dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; in rmt_ll_rx_enable_wrap()
[all …]
Dledc_ll.h332 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc = duty_direction; in ledc_ll_set_duty_direction()
347 *duty_direction = hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc; in ledc_ll_get_duty_direction()
362 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num; in ledc_ll_set_duty_num()
377 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle; in ledc_ll_set_duty_cycle()
392 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_scale = duty_scale; in ledc_ll_set_duty_scale()
422 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; in ledc_ll_set_duty_start()
Duart_ll.h437 hw->conf1.rxfifo_full_thrhd = full_thrhd; in uart_ll_set_rxfifo_full_thr()
451 hw->conf1.txfifo_empty_thrhd = empty_thrhd; in uart_ll_set_txfifo_empty_thr()
513 hw->conf1.rx_flow_en = 1; in uart_ll_set_hw_flow_ctrl()
515 hw->conf1.rx_flow_en = 0; in uart_ll_set_hw_flow_ctrl()
535 if (hw->conf1.rx_flow_en) { in uart_ll_get_hw_flow_ctrl()
838 return hw->conf1.rx_flow_en; in uart_ll_is_hw_rts_en()
911 hw->conf1.rx_tout_en = 1; in uart_ll_set_rx_tout()
913 hw->conf1.rx_tout_en = 0; in uart_ll_set_rx_tout()
927 if(hw->conf1.rx_tout_en > 0) { in uart_ll_get_rx_tout_thr()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Drmt_ll.h477 dev->chmconf[channel].conf1.mem_wr_rst_chm = 1; in rmt_ll_rx_reset_pointer()
478 dev->chmconf[channel].conf1.mem_wr_rst_chm = 0; in rmt_ll_rx_reset_pointer()
479 dev->chmconf[channel].conf1.apb_mem_rst_chm = 1; in rmt_ll_rx_reset_pointer()
480 dev->chmconf[channel].conf1.apb_mem_rst_chm = 0; in rmt_ll_rx_reset_pointer()
493 dev->chmconf[channel].conf1.rx_en_chm = enable; in rmt_ll_rx_enable()
495 dev->chmconf[channel].conf1.conf_update_chm = 1; in rmt_ll_rx_enable()
533 dev->chmconf[channel].conf1.mem_owner_chm = owner; in rmt_ll_rx_set_mem_owner()
546 dev->chmconf[channel].conf1.rx_filter_en_chm = enable; in rmt_ll_rx_enable_filter()
559 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_chm, thres); in rmt_ll_rx_set_filter_thres()
635 dev->chmconf[channel].conf1.mem_rx_wrap_en_chm = enable; in rmt_ll_rx_enable_wrap()
[all …]
Dpcnt_ll.h280 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_set_thres_value()
286 hw->conf_unit[unit].conf1 = conf1_reg; in pcnt_ll_set_thres_value()
328 pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; in pcnt_ll_get_thres_value()
Duart_ll.h477 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd); in uart_ll_set_rxfifo_full_thr()
491 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd); in uart_ll_set_txfifo_empty_thr()
673 hw->conf1.sw_dtr = level & 0x1; in uart_ll_set_dtr_active_level()
937 typeof(hw->conf1) conf1_reg; in uart_ll_inverse_signal()
938 conf1_reg.val = hw->conf1.val; in uart_ll_inverse_signal()
943 hw->conf1.val = conf1_reg.val; in uart_ll_inverse_signal()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dledc_ll.h332 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc = duty_direction; in ledc_ll_set_duty_direction()
347 *duty_direction = hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc; in ledc_ll_get_duty_direction()
362 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num; in ledc_ll_set_duty_num()
377 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle; in ledc_ll_set_duty_cycle()
392 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_scale = duty_scale; in ledc_ll_set_duty_scale()
422 hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; in ledc_ll_set_duty_start()
Duart_ll.h437 hw->conf1.rxfifo_full_thrhd = full_thrhd; in uart_ll_set_rxfifo_full_thr()
451 hw->conf1.txfifo_empty_thrhd = empty_thrhd; in uart_ll_set_txfifo_empty_thr()
513 hw->conf1.rx_flow_en = 1; in uart_ll_set_hw_flow_ctrl()
515 hw->conf1.rx_flow_en = 0; in uart_ll_set_hw_flow_ctrl()
535 if (hw->conf1.rx_flow_en) { in uart_ll_get_hw_flow_ctrl()
838 return hw->conf1.rx_flow_en; in uart_ll_is_hw_rts_en()
911 hw->conf1.rx_tout_en = 1; in uart_ll_set_rx_tout()
913 hw->conf1.rx_tout_en = 0; in uart_ll_set_rx_tout()
927 if(hw->conf1.rx_tout_en > 0) { in uart_ll_get_rx_tout_thr()

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