Searched refs:clk_sel0 (Results 1 – 4 of 4) sorted by relevance
66 uint32_t clk_sel0; in efuse_hal_set_timing() local70 clk_sel0 = 250; in efuse_hal_set_timing()74 clk_sel0 = 160; in efuse_hal_set_timing()78 clk_sel0 = 80; in efuse_hal_set_timing()83 efuse_ll_set_dac_clk_sel0(clk_sel0); in efuse_hal_set_timing()
220 EFUSE.clk.clk_sel0 = value; in efuse_ll_set_dac_clk_sel0()
191 clk_sel0, clk_sel1, dac_clk_div = self.REGS.EFUSE_CLK_SETTINGS[apb_freq]197 self.REGS.EFUSE_CLK_REG, self.REGS.EFUSE_CLK_SEL0_MASK, clk_sel0
1040 uint32_t clk_sel0:8; member
