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Searched refs:clk_sel (Results 1 – 25 of 25) sorted by relevance

/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dtemperature_sensor_ll.h64 uint8_t clk_sel = 0; in temperature_sensor_ll_clk_sel() local
67 clk_sel = 1; in temperature_sensor_ll_clk_sel()
70 clk_sel = 0; in temperature_sensor_ll_clk_sel()
76 APB_SARADC.saradc_apb_tsens_ctrl2.saradc_tsens_clk_sel = clk_sel; in temperature_sensor_ll_clk_sel()
Dclk_tree_ll.h313 uint32_t clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in clk_ll_cpu_get_src() local
314 switch (clk_sel) { in clk_ll_cpu_get_src()
417 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src() local
418 switch (clk_sel) { in clk_ll_rtc_slow_get_src()
458 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src() local
459 switch (clk_sel) { in clk_ll_rtc_fast_get_src()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dtemperature_sensor_ll.h64 uint8_t clk_sel = 0; in temperature_sensor_ll_clk_sel() local
67 clk_sel = 1; in temperature_sensor_ll_clk_sel()
70 clk_sel = 0; in temperature_sensor_ll_clk_sel()
76 APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = clk_sel; in temperature_sensor_ll_clk_sel()
Dclk_tree_ll.h421 uint32_t clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in clk_ll_cpu_get_src() local
422 switch (clk_sel) { in clk_ll_cpu_get_src()
525 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src() local
526 switch (clk_sel) { in clk_ll_rtc_slow_get_src()
566 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src() local
567 switch (clk_sel) { in clk_ll_rtc_fast_get_src()
Dadc_ll.h312 APB_SARADC.apb_adc_clkm_conf.clk_sel = 2; in adc_ll_digi_clk_sel()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dparlio_ll.h61 uint32_t clk_sel = 0; in parlio_ll_rx_set_clock_source() local
64 clk_sel = 0; in parlio_ll_rx_set_clock_source()
67 clk_sel = 1; in parlio_ll_rx_set_clock_source()
70 clk_sel = 3; in parlio_ll_rx_set_clock_source()
77 PCR.parl_clk_rx_conf.parl_clk_rx_sel = clk_sel; in parlio_ll_rx_set_clock_source()
343 uint32_t clk_sel = 0; in parlio_ll_tx_set_clock_source() local
346 clk_sel = 0; in parlio_ll_tx_set_clock_source()
349 clk_sel = 1; in parlio_ll_tx_set_clock_source()
352 clk_sel = 3; in parlio_ll_tx_set_clock_source()
359 PCR.parl_clk_tx_conf.parl_clk_tx_sel = clk_sel; in parlio_ll_tx_set_clock_source()
Dtemperature_sensor_ll.h73 uint8_t clk_sel = 0; in temperature_sensor_ll_clk_sel() local
76 clk_sel = 1; in temperature_sensor_ll_clk_sel()
79 clk_sel = 0; in temperature_sensor_ll_clk_sel()
85 PCR.tsens_clk_conf.tsens_clk_sel = clk_sel; in temperature_sensor_ll_clk_sel()
Dclk_tree_ll.h365 uint32_t clk_sel = PCR.sysclk_conf.soc_clk_sel; in clk_ll_cpu_get_src() local
366 switch (clk_sel) { in clk_ll_cpu_get_src()
612 uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; in clk_ll_32k_calibration_get_target() local
613 switch (clk_sel) { in clk_ll_32k_calibration_get_target()
658 uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel; in clk_ll_rtc_slow_get_src() local
659 switch (clk_sel) { in clk_ll_rtc_slow_get_src()
700 uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel; in clk_ll_rtc_fast_get_src() local
701 switch (clk_sel) { in clk_ll_rtc_fast_get_src()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dparlio_ll.h61 uint32_t clk_sel = 0; in parlio_ll_rx_set_clock_source() local
64 clk_sel = 0; in parlio_ll_rx_set_clock_source()
67 clk_sel = 1; in parlio_ll_rx_set_clock_source()
70 clk_sel = 3; in parlio_ll_rx_set_clock_source()
77 PCR.parl_clk_rx_conf.parl_clk_rx_sel = clk_sel; in parlio_ll_rx_set_clock_source()
347 uint32_t clk_sel = 0; in parlio_ll_tx_set_clock_source() local
350 clk_sel = 0; in parlio_ll_tx_set_clock_source()
353 clk_sel = 1; in parlio_ll_tx_set_clock_source()
356 clk_sel = 3; in parlio_ll_tx_set_clock_source()
363 PCR.parl_clk_tx_conf.parl_clk_tx_sel = clk_sel; in parlio_ll_tx_set_clock_source()
Dclk_tree_ll.h379 uint32_t clk_sel = PCR.sysclk_conf.soc_clk_sel; in clk_ll_cpu_get_src() local
380 switch (clk_sel) { in clk_ll_cpu_get_src()
490 uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; in clk_ll_32k_calibration_get_target() local
491 switch (clk_sel) { in clk_ll_32k_calibration_get_target()
536 uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel; in clk_ll_rtc_slow_get_src() local
537 switch (clk_sel) { in clk_ll_rtc_slow_get_src()
580 uint32_t clk_sel = REGI2C_READ_MASK(I2C_PMU, I2C_PMU_SEL_PLL8M_REF); in clk_ll_lp_pll_get_src() local
581 switch (clk_sel) { in clk_ll_lp_pll_get_src()
632 uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel; in clk_ll_rtc_fast_get_src() local
633 switch (clk_sel) { in clk_ll_rtc_fast_get_src()
Dtemperature_sensor_ll.h73 uint8_t clk_sel = 0; in temperature_sensor_ll_clk_sel() local
76 clk_sel = 1; in temperature_sensor_ll_clk_sel()
79 clk_sel = 0; in temperature_sensor_ll_clk_sel()
85 PCR.tsens_clk_conf.tsens_clk_sel = clk_sel; in temperature_sensor_ll_clk_sel()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dclk_tree_ll.h415 uint32_t clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in clk_ll_cpu_get_src() local
416 switch (clk_sel) { in clk_ll_cpu_get_src()
526 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src() local
527 switch (clk_sel) { in clk_ll_rtc_slow_get_src()
568 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src() local
569 switch (clk_sel) { in clk_ll_rtc_fast_get_src()
Dsdmmc_ll.h63 hw->clock.clk_sel = clk_val; in sdmmc_ll_select_clk_source()
Dadc_ll.h370 APB_SARADC.apb_adc_clkm_conf.clk_sel = (clk_src == ADC_DIGI_CLK_SRC_APB) ? 2 : 1; in adc_ll_digi_clk_sel()
380 APB_SARADC.apb_adc_clkm_conf.clk_sel = 0; in adc_ll_digi_controller_clk_disable()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dclk_tree_ll.h482 uint32_t clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); in clk_ll_cpu_get_src() local
483 switch (clk_sel) { in clk_ll_cpu_get_src()
640 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src() local
641 switch (clk_sel) { in clk_ll_rtc_slow_get_src()
681 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src() local
682 switch (clk_sel) { in clk_ll_rtc_fast_get_src()
Di2s_ll.h99 hw->clkm_conf.clk_sel = 2; in i2s_ll_enable_clock()
257 hw->clkm_conf.clk_sel = (src == I2S_CLK_SRC_APLL) ? 1 : 2; in i2s_ll_tx_clk_set_src()
268 hw->clkm_conf.clk_sel = (src == I2S_CLK_SRC_APLL) ? 1 : 2; in i2s_ll_rx_clk_set_src()
Dadc_ll.h365 APB_SARADC.apb_adc_clkm_conf.clk_sel = (clk_src == ADC_DIGI_CLK_SRC_APLL) ? 1 : 2; in adc_ll_digi_clk_sel()
375 APB_SARADC.apb_adc_clkm_conf.clk_sel = 0; in adc_ll_digi_controller_clk_disable()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dclk_tree_ll.h560 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in clk_ll_cpu_get_src() local
561 switch (clk_sel) { in clk_ll_cpu_get_src()
724 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src() local
725 switch (clk_sel) { in clk_ll_rtc_slow_get_src()
765 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src() local
766 switch (clk_sel) { in clk_ll_rtc_fast_get_src()
Demac_ll.h585 ext_regs->ex_oscclk_conf.clk_sel = 1; in emac_ll_clock_enable_rmii_input()
596 ext_regs->ex_oscclk_conf.clk_sel = 0; in emac_ll_clock_enable_rmii_output()
/hal_espressif-latest/components/soc/esp32/include/soc/
Demac_ext_struct.h38 uint32_t clk_sel : 1; member
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dsdmmc_struct.h383 uint32_t clk_sel : 1; ///< clock source select (0: XTAL, 1: 160 MHz from PLL) member
Dapb_saradc_struct.h210 uint32_t clk_sel : 2; /*Set this bit to enable clk_apll*/ member
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Di2s_struct.h364 uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ member
Dapb_saradc_struct.h172 uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ member
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dapb_saradc_struct.h214 uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ member