1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: FIFO R/W registers */ 14 /** Type of chndata register 15 * Read and write data for channel n via APB FIFO 16 */ 17 typedef union { 18 struct { 19 /** chn_data : RO; bitpos: [31:0]; default: 0; 20 * This register is used to read and write data for channel n via APB FIFO. 21 */ 22 uint32_t chn_data: 32; 23 }; 24 uint32_t val; 25 } rmt_chndata_reg_t; 26 27 28 /** Group: Configuration registers */ 29 /** Type of chnconf0 register 30 * Channel n configuration register 0 31 */ 32 typedef union { 33 struct { 34 /** div_cnt_chn : R/W; bitpos: [7:0]; default: 2; 35 * This field is used to configure clock divider for channel n. 36 */ 37 uint32_t div_cnt_chn: 8; 38 /** idle_thres_chn : R/W; bitpos: [23:8]; default: 4096; 39 * Receiving ends when no edge is detected on input signals for continuous clock 40 * cycles longer than this field value. 41 */ 42 uint32_t idle_thres_chn: 16; 43 /** mem_size_chn : R/W; bitpos: [26:24]; default: 1; 44 * This field is used to configure the maximum blocks allocated to channel n. The 45 * valid range is from 1 ~ 4-n. 46 */ 47 uint32_t mem_size_chn: 3; 48 /** carrier_eff_en_chn : R/W; bitpos: [27]; default: 1; 49 * 1: Add carrier modulation on output signals only at data sending state for channel 50 * n. 0: Add carrier modulation on signals at all states for channel n. States here 51 * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data 52 * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CHn is set to 1. 53 */ 54 uint32_t carrier_eff_en_chn: 1; 55 /** carrier_en_chn : R/W; bitpos: [28]; default: 1; 56 * This bit is used to enable carrier modulation for channel n. 1: Add carrier 57 * modulation on output signals. 0: No carrier modulation is added on output signals. 58 */ 59 uint32_t carrier_en_chn: 1; 60 /** carrier_out_lv_chn : R/W; bitpos: [29]; default: 1; 61 * This bit is used to configure the position of carrier wave for channel n. 62 * 63 * 1'h0: Add carrier wave on low-level output signals. 64 * 65 * 1'h1: Add carrier wave on high-level output signals. 66 */ 67 uint32_t carrier_out_lv_chn: 1; 68 uint32_t reserved_30: 2; 69 }; 70 uint32_t val; 71 } rmt_chnconf0_reg_t; 72 73 /** Type of chnconf1 register 74 * Channel n configuration register 1 75 */ 76 typedef union { 77 struct { 78 /** tx_start_chn : R/W; bitpos: [0]; default: 0; 79 * Set this bit to start sending data on channel n. 80 */ 81 uint32_t tx_start_chn: 1; 82 /** rx_en_chn : R/W; bitpos: [1]; default: 0; 83 * Set this bit to enable receiver to receive data on channel n. 84 */ 85 uint32_t rx_en_chn: 1; 86 /** mem_wr_rst_chn : WO; bitpos: [2]; default: 0; 87 * Set this bit to reset RAM write address accessed by the receiver for channel n. 88 */ 89 uint32_t mem_wr_rst_chn: 1; 90 /** mem_rd_rst_chn : WO; bitpos: [3]; default: 0; 91 * Set this bit to reset RAM read address accessed by the transmitter for channel n. 92 */ 93 uint32_t mem_rd_rst_chn: 1; 94 /** apb_mem_rst_chn : WO; bitpos: [4]; default: 0; 95 * Set this bit to reset W/R ram address for channel n by accessing apb fifo. 96 */ 97 uint32_t apb_mem_rst_chn: 1; 98 /** mem_owner_chn : R/W; bitpos: [5]; default: 1; 99 * This bit marks the ownership of channel n's RAM block. 100 * 101 * 1'h1: Receiver is using the RAM. 102 * 103 * 1'h0: Transmitter is using the RAM. 104 */ 105 uint32_t mem_owner_chn: 1; 106 /** tx_conti_mode_chn : R/W; bitpos: [6]; default: 0; 107 * Set this bit to restart transmission in continuous node from the first data in 108 * channel n. 109 */ 110 uint32_t tx_conti_mode_chn: 1; 111 /** rx_filter_en_chn : R/W; bitpos: [7]; default: 0; 112 * Set this bit to enable the receiver's filter for channel n. 113 */ 114 uint32_t rx_filter_en_chn: 1; 115 /** rx_filter_thres_chn : R/W; bitpos: [15:8]; default: 15; 116 * Set this field to ignore the input pulse when its width is less than 117 * RMT_RX_FILTER_THRES_CHn APB clock cycles in receive mode. 118 */ 119 uint32_t rx_filter_thres_chn: 8; 120 /** chk_rx_carrier_en_chn : R/W; bitpos: [16]; default: 0; 121 * Set this bit to enable memory loop read mode when carrier modulation is enabled for 122 * channel n. 123 */ 124 uint32_t chk_rx_carrier_en_chn: 1; 125 /** ref_always_on_chn : R/W; bitpos: [17]; default: 0; 126 * Set this bit to select a base clock for channel n. 127 * 128 * 1'h1: APB_CLK 1'h0: REF_TICK 129 */ 130 uint32_t ref_always_on_chn: 1; 131 /** idle_out_lv_chn : R/W; bitpos: [18]; default: 0; 132 * This bit configures the level of output signals in channel n when the transmitter 133 * is in idle state. 134 */ 135 uint32_t idle_out_lv_chn: 1; 136 /** idle_out_en_chn : R/W; bitpos: [19]; default: 0; 137 * This is the output enable bit for channel n in idle state. 138 */ 139 uint32_t idle_out_en_chn: 1; 140 /** tx_stop_chn : R/W; bitpos: [20]; default: 0; 141 * Set this bit to stop the transmitter of channel n sending data out. 142 */ 143 uint32_t tx_stop_chn: 1; 144 uint32_t reserved_21: 11; 145 }; 146 uint32_t val; 147 } rmt_chnconf1_reg_t; 148 149 /** Type of apb_conf register 150 * RMT APB configuration register 151 */ 152 typedef union { 153 struct { 154 /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; 155 * 1'h1: Access memory directly. 1'h0: access memory via APB FIFO. 156 */ 157 uint32_t apb_fifo_mask: 1; 158 /** mem_tx_wrap_en : R/W; bitpos: [1]; default: 0; 159 * Set this bit to enable wrap mode. 160 */ 161 uint32_t mem_tx_wrap_en: 1; 162 /** mem_clk_force_on : R/W; bitpos: [2]; default: 1; 163 * Set this bit to enable the clock for RAM when RMT module starts working, disable 164 * this clock when RMT stops working, to achieve low-power scheme. 165 */ 166 uint32_t mem_clk_force_on: 1; 167 /** mem_force_pd : R/W; bitpos: [3]; default: 0; 168 * Set this bit to power down RMT memory. 169 */ 170 uint32_t mem_force_pd: 1; 171 /** mem_force_pu : R/W; bitpos: [4]; default: 0; 172 * 1: Disable RAM's Light-sleep power down function. 0: power down RMT RAM when RMT is 173 * in Light-sleep mode. 174 */ 175 uint32_t mem_force_pu: 1; 176 uint32_t reserved_5: 26; 177 /** clk_en : R/W; bitpos: [31]; default: 0; 178 * Clock gating enable bit for RMT registers to achieve low-power scheme. 1: Power up 179 * drive clock for RMT registers. 0: Power down drive clock for RMT registers. 180 */ 181 uint32_t clk_en: 1; 182 }; 183 uint32_t val; 184 } rmt_apb_conf_reg_t; 185 186 /** Type of ref_cnt_rst register 187 * RMT clock divider reset register 188 */ 189 typedef union { 190 struct { 191 /** ref_cnt_rst_ch0 : R/W; bitpos: [0]; default: 0; 192 * This bit is used to reset the clock divider of channel 0. 193 */ 194 uint32_t ref_cnt_rst_ch0: 1; 195 /** ref_cnt_rst_ch1 : R/W; bitpos: [1]; default: 0; 196 * This bit is used to reset the clock divider of channel 1. 197 */ 198 uint32_t ref_cnt_rst_ch1: 1; 199 /** ref_cnt_rst_ch2 : R/W; bitpos: [2]; default: 0; 200 * This bit is used to reset the clock divider of channel 2. 201 */ 202 uint32_t ref_cnt_rst_ch2: 1; 203 /** ref_cnt_rst_ch3 : R/W; bitpos: [3]; default: 0; 204 * This bit is used to reset the clock divider of channel 3. 205 */ 206 uint32_t ref_cnt_rst_ch3: 1; 207 uint32_t reserved_4: 28; 208 }; 209 uint32_t val; 210 } rmt_ref_cnt_rst_reg_t; 211 212 /** Type of chn_rx_carrier_rm register 213 * Channel n carrier remove register 214 */ 215 typedef union { 216 struct { 217 /** carrier_low_thres_chn : R/W; bitpos: [15:0]; default: 0; 218 * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CHn + 1) 219 * clock cycles for channel n. 220 */ 221 uint32_t carrier_low_thres_chn: 16; 222 /** carrier_high_thres_chn : R/W; bitpos: [31:16]; default: 0; 223 * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CHn + 224 * 1) clock cycles for channel n. 225 */ 226 uint32_t carrier_high_thres_chn: 16; 227 }; 228 uint32_t val; 229 } rmt_chn_rx_carrier_rm_reg_t; 230 231 232 /** Group: Status registers */ 233 /** Type of chnstatus register 234 * Channel n status register 235 */ 236 typedef union { 237 struct { 238 /** mem_waddr_ex_chn : RO; bitpos: [8:0]; default: 0; 239 * This field records the memory address offset when receiver of channel n is using 240 * the RAM. 241 */ 242 uint32_t mem_waddr_ex_chn: 9; 243 uint32_t reserved_9: 1; 244 /** mem_raddr_ex_chn : RO; bitpos: [18:10]; default: 0; 245 * This field records the memory address offset when transmitter of channel n is using 246 * the RAM. 247 */ 248 uint32_t mem_raddr_ex_chn: 9; 249 uint32_t reserved_19: 1; 250 /** state_chn : RO; bitpos: [22:20]; default: 0; 251 * This field records the FSM status of channel n. 252 */ 253 uint32_t state_chn: 3; 254 /** mem_owner_err_chn : RO; bitpos: [23]; default: 0; 255 * This status bit will be set when the ownership of memory block is violated. 256 */ 257 uint32_t mem_owner_err_chn: 1; 258 /** mem_full_chn : RO; bitpos: [24]; default: 0; 259 * This status bit will be set if the receiver receives more data than the memory 260 * allows. 261 */ 262 uint32_t mem_full_chn: 1; 263 /** mem_empty_chn : RO; bitpos: [25]; default: 0; 264 * This status bit will be set when the data to be sent is more than memory allows and 265 * the wrap mode is disabled. 266 */ 267 uint32_t mem_empty_chn: 1; 268 /** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0; 269 * This status bit will be set if the offset address out of memory size when writes 270 * RAM via APB bus. 271 */ 272 uint32_t apb_mem_wr_err_chn: 1; 273 /** apb_mem_rd_err_chn : RO; bitpos: [27]; default: 0; 274 * This status bit will be set if the offset address out of memory size when reads RAM 275 * via APB bus. 276 */ 277 uint32_t apb_mem_rd_err_chn: 1; 278 uint32_t reserved_28: 4; 279 }; 280 uint32_t val; 281 } rmt_chnstatus_reg_t; 282 283 /** Type of chnaddr register 284 * Channel n address register 285 */ 286 typedef union { 287 struct { 288 /** apb_mem_waddr_chn : RO; bitpos: [8:0]; default: 0; 289 * This field records the memory address offset when channel n writes RAM via APB bus. 290 */ 291 uint32_t apb_mem_waddr_chn: 9; 292 uint32_t reserved_9: 1; 293 /** apb_mem_raddr_chn : RO; bitpos: [18:10]; default: 0; 294 * This field records the memory address offset when channel n reads RAM via APB bus. 295 */ 296 uint32_t apb_mem_raddr_chn: 9; 297 uint32_t reserved_19: 13; 298 }; 299 uint32_t val; 300 } rmt_chnaddr_reg_t; 301 302 303 /** Group: Interrupt registers */ 304 /** Type of int_raw register 305 * Raw interrupt status register 306 */ 307 typedef union { 308 struct { 309 /** ch0_tx_end_int_raw : RO; bitpos: [0]; default: 0; 310 * The interrupt raw bit for channel 0. Triggered when transmitting ends. 311 */ 312 uint32_t ch0_tx_end_int_raw: 1; 313 /** ch0_rx_end_int_raw : RO; bitpos: [1]; default: 0; 314 * The interrupt raw bit for channel 0. Triggered when receiving ends. 315 */ 316 uint32_t ch0_rx_end_int_raw: 1; 317 /** ch0_err_int_raw : RO; bitpos: [2]; default: 0; 318 * The interrupt raw bit for channel 0. Triggered when error occurs. 319 */ 320 uint32_t ch0_err_int_raw: 1; 321 /** ch1_tx_end_int_raw : RO; bitpos: [3]; default: 0; 322 * The interrupt raw bit for channel 1. Triggered when transmitting ends. 323 */ 324 uint32_t ch1_tx_end_int_raw: 1; 325 /** ch1_rx_end_int_raw : RO; bitpos: [4]; default: 0; 326 * The interrupt raw bit for channel 1. Triggered when receiving ends. 327 */ 328 uint32_t ch1_rx_end_int_raw: 1; 329 /** ch1_err_int_raw : RO; bitpos: [5]; default: 0; 330 * The interrupt raw bit for channel 1. Triggered when error occurs. 331 */ 332 uint32_t ch1_err_int_raw: 1; 333 /** ch2_tx_end_int_raw : RO; bitpos: [6]; default: 0; 334 * The interrupt raw bit for channel 2. Triggered when transmitting ends. 335 */ 336 uint32_t ch2_tx_end_int_raw: 1; 337 /** ch2_rx_end_int_raw : RO; bitpos: [7]; default: 0; 338 * The interrupt raw bit for channel 2. Triggered when receiving ends. 339 */ 340 uint32_t ch2_rx_end_int_raw: 1; 341 /** ch2_err_int_raw : RO; bitpos: [8]; default: 0; 342 * The interrupt raw bit for channel 2. Triggered when error occurs. 343 */ 344 uint32_t ch2_err_int_raw: 1; 345 /** ch3_tx_end_int_raw : RO; bitpos: [9]; default: 0; 346 * The interrupt raw bit for channel 3. Triggered when transmitting ends. 347 */ 348 uint32_t ch3_tx_end_int_raw: 1; 349 /** ch3_rx_end_int_raw : RO; bitpos: [10]; default: 0; 350 * The interrupt raw bit for channel 3. Triggered when receiving ends. 351 */ 352 uint32_t ch3_rx_end_int_raw: 1; 353 /** ch3_err_int_raw : RO; bitpos: [11]; default: 0; 354 * The interrupt raw bit for channel 3. Triggered when error occurs. 355 */ 356 uint32_t ch3_err_int_raw: 1; 357 /** ch0_tx_thr_event_int_raw : RO; bitpos: [12]; default: 0; 358 * The interrupt raw bit for channel 0. Triggered when transmitter sends more data 359 * than configured value. 360 */ 361 uint32_t ch0_tx_thr_event_int_raw: 1; 362 /** ch1_tx_thr_event_int_raw : RO; bitpos: [13]; default: 0; 363 * The interrupt raw bit for channel 1. Triggered when transmitter sends more data 364 * than configured value. 365 */ 366 uint32_t ch1_tx_thr_event_int_raw: 1; 367 /** ch2_tx_thr_event_int_raw : RO; bitpos: [14]; default: 0; 368 * The interrupt raw bit for channel 2. Triggered when transmitter sends more data 369 * than configured value. 370 */ 371 uint32_t ch2_tx_thr_event_int_raw: 1; 372 /** ch3_tx_thr_event_int_raw : RO; bitpos: [15]; default: 0; 373 * The interrupt raw bit for channel 3. Triggered when transmitter sends more data 374 * than configured value. 375 */ 376 uint32_t ch3_tx_thr_event_int_raw: 1; 377 /** ch0_tx_loop_int_raw : RO; bitpos: [16]; default: 0; 378 * The interrupt raw bit for channel 0. Triggered when loop counting reaches the 379 * configured threshold value. 380 */ 381 uint32_t ch0_tx_loop_int_raw: 1; 382 /** ch1_tx_loop_int_raw : RO; bitpos: [17]; default: 0; 383 * The interrupt raw bit for channel 1. Triggered when loop counting reaches the 384 * configured threshold value. 385 */ 386 uint32_t ch1_tx_loop_int_raw: 1; 387 /** ch2_tx_loop_int_raw : RO; bitpos: [18]; default: 0; 388 * The interrupt raw bit for channel 2. Triggered when loop counting reaches the 389 * configured threshold value. 390 */ 391 uint32_t ch2_tx_loop_int_raw: 1; 392 /** ch3_tx_loop_int_raw : RO; bitpos: [19]; default: 0; 393 * The interrupt raw bit for channel 3. Triggered when loop counting reaches the 394 * configured threshold value. 395 */ 396 uint32_t ch3_tx_loop_int_raw: 1; 397 uint32_t reserved_20: 12; 398 }; 399 uint32_t val; 400 } rmt_int_raw_reg_t; 401 402 /** Type of int_st register 403 * Masked interrupt status register 404 */ 405 typedef union { 406 struct { 407 /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; 408 * The masked interrupt status bit for RMT_CH0_TX_END_INT. 409 */ 410 uint32_t ch0_tx_end_int_st: 1; 411 /** ch0_rx_end_int_st : RO; bitpos: [1]; default: 0; 412 * The masked interrupt status bit for RMT_CH0_RX_END_INT. 413 */ 414 uint32_t ch0_rx_end_int_st: 1; 415 /** ch0_err_int_st : RO; bitpos: [2]; default: 0; 416 * The masked interrupt status bit for RMT_CH0_ERR_INT. 417 */ 418 uint32_t ch0_err_int_st: 1; 419 /** ch1_tx_end_int_st : RO; bitpos: [3]; default: 0; 420 * The masked interrupt status bit for RMT_CH1_TX_END_INT. 421 */ 422 uint32_t ch1_tx_end_int_st: 1; 423 /** ch1_rx_end_int_st : RO; bitpos: [4]; default: 0; 424 * The masked interrupt status bit for RMT_CH1_RX_END_INT. 425 */ 426 uint32_t ch1_rx_end_int_st: 1; 427 /** ch1_err_int_st : RO; bitpos: [5]; default: 0; 428 * The masked interrupt status bit for RMT_CH1_ERR_INT. 429 */ 430 uint32_t ch1_err_int_st: 1; 431 /** ch2_tx_end_int_st : RO; bitpos: [6]; default: 0; 432 * The masked interrupt status bit for RMT_CH2_TX_END_INT. 433 */ 434 uint32_t ch2_tx_end_int_st: 1; 435 /** ch2_rx_end_int_st : RO; bitpos: [7]; default: 0; 436 * The masked interrupt status bit for RMT_CH2_RX_END_INT. 437 */ 438 uint32_t ch2_rx_end_int_st: 1; 439 /** ch2_err_int_st : RO; bitpos: [8]; default: 0; 440 * The masked interrupt status bit for RMT_CH2_ERR_INT. 441 */ 442 uint32_t ch2_err_int_st: 1; 443 /** ch3_tx_end_int_st : RO; bitpos: [9]; default: 0; 444 * The masked interrupt status bit for RMT_CH3_TX_END_INT. 445 */ 446 uint32_t ch3_tx_end_int_st: 1; 447 /** ch3_rx_end_int_st : RO; bitpos: [10]; default: 0; 448 * The masked interrupt status bit for RMT_CH3_RX_END_INT. 449 */ 450 uint32_t ch3_rx_end_int_st: 1; 451 /** ch3_err_int_st : RO; bitpos: [11]; default: 0; 452 * The masked interrupt status bit for RMT_CH3_ERR_INT. 453 */ 454 uint32_t ch3_err_int_st: 1; 455 /** ch0_tx_thr_event_int_st : RO; bitpos: [12]; default: 0; 456 * The masked interrupt status bit for RMT_CH0_TX_THR_EVENT_INT. 457 */ 458 uint32_t ch0_tx_thr_event_int_st: 1; 459 /** ch1_tx_thr_event_int_st : RO; bitpos: [13]; default: 0; 460 * The masked interrupt status bit for RMT_CH1_TX_THR_EVENT_INT. 461 */ 462 uint32_t ch1_tx_thr_event_int_st: 1; 463 /** ch2_tx_thr_event_int_st : RO; bitpos: [14]; default: 0; 464 * The masked interrupt status bit for RMT_CH2_TX_THR_EVENT_INT. 465 */ 466 uint32_t ch2_tx_thr_event_int_st: 1; 467 /** ch3_tx_thr_event_int_st : RO; bitpos: [15]; default: 0; 468 * The masked interrupt status bit for RMT_CH3_TX_THR_EVENT_INT. 469 */ 470 uint32_t ch3_tx_thr_event_int_st: 1; 471 /** ch0_tx_loop_int_st : RO; bitpos: [16]; default: 0; 472 * The masked interrupt status bit for RMT_CH0_TX_LOOP_INT. 473 */ 474 uint32_t ch0_tx_loop_int_st: 1; 475 /** ch1_tx_loop_int_st : RO; bitpos: [17]; default: 0; 476 * The masked interrupt status bit for RMT_CH1_TX_LOOP_INT. 477 */ 478 uint32_t ch1_tx_loop_int_st: 1; 479 /** ch2_tx_loop_int_st : RO; bitpos: [18]; default: 0; 480 * The masked interrupt status bit for RMT_CH2_TX_LOOP_INT. 481 */ 482 uint32_t ch2_tx_loop_int_st: 1; 483 /** ch3_tx_loop_int_st : RO; bitpos: [19]; default: 0; 484 * The masked interrupt status bit for RMT_CH3_TX_LOOP_INT. 485 */ 486 uint32_t ch3_tx_loop_int_st: 1; 487 uint32_t reserved_20: 12; 488 }; 489 uint32_t val; 490 } rmt_int_st_reg_t; 491 492 /** Type of int_ena register 493 * Interrupt enable register 494 */ 495 typedef union { 496 struct { 497 /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; 498 * The interrupt enabled bit for RMT_CH0_TX_END_INT. 499 */ 500 uint32_t ch0_tx_end_int_ena: 1; 501 /** ch0_rx_end_int_ena : R/W; bitpos: [1]; default: 0; 502 * The interrupt enabled bit for RMT_CH0_RX_END_INT. 503 */ 504 uint32_t ch0_rx_end_int_ena: 1; 505 /** ch0_err_int_ena : R/W; bitpos: [2]; default: 0; 506 * The interrupt enabled bit for RMT_CH0_ERR_INT. 507 */ 508 uint32_t ch0_err_int_ena: 1; 509 /** ch1_tx_end_int_ena : R/W; bitpos: [3]; default: 0; 510 * The interrupt enabled bit for RMT_CH1_TX_END_INT. 511 */ 512 uint32_t ch1_tx_end_int_ena: 1; 513 /** ch1_rx_end_int_ena : R/W; bitpos: [4]; default: 0; 514 * The interrupt enabled bit for RMT_CH1_RX_END_INT. 515 */ 516 uint32_t ch1_rx_end_int_ena: 1; 517 /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; 518 * The interrupt enabled bit for RMT_CH1_ERR_INT. 519 */ 520 uint32_t ch1_err_int_ena: 1; 521 /** ch2_tx_end_int_ena : R/W; bitpos: [6]; default: 0; 522 * The interrupt enabled bit for RMT_CH2_TX_END_INT. 523 */ 524 uint32_t ch2_tx_end_int_ena: 1; 525 /** ch2_rx_end_int_ena : R/W; bitpos: [7]; default: 0; 526 * The interrupt enabled bit for RMT_CH2_RX_END_INT. 527 */ 528 uint32_t ch2_rx_end_int_ena: 1; 529 /** ch2_err_int_ena : R/W; bitpos: [8]; default: 0; 530 * The interrupt enabled bit for RMT_CH2_ERR_INT. 531 */ 532 uint32_t ch2_err_int_ena: 1; 533 /** ch3_tx_end_int_ena : R/W; bitpos: [9]; default: 0; 534 * The interrupt enabled bit for RMT_CH3_TX_END_INT. 535 */ 536 uint32_t ch3_tx_end_int_ena: 1; 537 /** ch3_rx_end_int_ena : R/W; bitpos: [10]; default: 0; 538 * The interrupt enabled bit for RMT_CH3_RX_END_INT. 539 */ 540 uint32_t ch3_rx_end_int_ena: 1; 541 /** ch3_err_int_ena : R/W; bitpos: [11]; default: 0; 542 * The interrupt enabled bit for RMT_CH3_ERR_INT. 543 */ 544 uint32_t ch3_err_int_ena: 1; 545 /** ch0_tx_thr_event_int_ena : R/W; bitpos: [12]; default: 0; 546 * The interrupt enabled bit for RMT_CH0_TX_THR_EVENT_INT. 547 */ 548 uint32_t ch0_tx_thr_event_int_ena: 1; 549 /** ch1_tx_thr_event_int_ena : R/W; bitpos: [13]; default: 0; 550 * The interrupt enabled bit for RMT_CH1_TX_THR_EVENT_INT. 551 */ 552 uint32_t ch1_tx_thr_event_int_ena: 1; 553 /** ch2_tx_thr_event_int_ena : R/W; bitpos: [14]; default: 0; 554 * The interrupt enabled bit for RMT_CH2_TX_THR_EVENT_INT. 555 */ 556 uint32_t ch2_tx_thr_event_int_ena: 1; 557 /** ch3_tx_thr_event_int_ena : R/W; bitpos: [15]; default: 0; 558 * The interrupt enabled bit for RMT_CH3_TX_THR_EVENT_INT. 559 */ 560 uint32_t ch3_tx_thr_event_int_ena: 1; 561 /** ch0_tx_loop_int_ena : R/W; bitpos: [16]; default: 0; 562 * The interrupt enabled bit for RMT_CH0_TX_LOOP_INT. 563 */ 564 uint32_t ch0_tx_loop_int_ena: 1; 565 /** ch1_tx_loop_int_ena : R/W; bitpos: [17]; default: 0; 566 * The interrupt enabled bit for RMT_CH1_TX_LOOP_INT. 567 */ 568 uint32_t ch1_tx_loop_int_ena: 1; 569 /** ch2_tx_loop_int_ena : R/W; bitpos: [18]; default: 0; 570 * The interrupt enabled bit for RMT_CH2_TX_LOOP_INT. 571 */ 572 uint32_t ch2_tx_loop_int_ena: 1; 573 /** ch3_tx_loop_int_ena : R/W; bitpos: [19]; default: 0; 574 * The interrupt enabled bit for RMT_CH3_TX_LOOP_INT. 575 */ 576 uint32_t ch3_tx_loop_int_ena: 1; 577 uint32_t reserved_20: 12; 578 }; 579 uint32_t val; 580 } rmt_int_ena_reg_t; 581 582 /** Type of int_clr register 583 * Interrupt clear register 584 */ 585 typedef union { 586 struct { 587 /** ch0_tx_end_int_clr : WO; bitpos: [0]; default: 0; 588 * Set this bit to clear RMT_CH0_TX_END_INT interrupt. 589 */ 590 uint32_t ch0_tx_end_int_clr: 1; 591 /** ch0_rx_end_int_clr : WO; bitpos: [1]; default: 0; 592 * Set this bit to clear RMT_CH0_RX_END_INT interrupt. 593 */ 594 uint32_t ch0_rx_end_int_clr: 1; 595 /** ch0_err_int_clr : WO; bitpos: [2]; default: 0; 596 * Set this bit to clear RMT_CH0_ERR_INT interrupt. 597 */ 598 uint32_t ch0_err_int_clr: 1; 599 /** ch1_tx_end_int_clr : WO; bitpos: [3]; default: 0; 600 * Set this bit to clear RMT_CH1_TX_END_INT interrupt. 601 */ 602 uint32_t ch1_tx_end_int_clr: 1; 603 /** ch1_rx_end_int_clr : WO; bitpos: [4]; default: 0; 604 * Set this bit to clear RMT_CH1_RX_END_INT interrupt. 605 */ 606 uint32_t ch1_rx_end_int_clr: 1; 607 /** ch1_err_int_clr : WO; bitpos: [5]; default: 0; 608 * Set this bit to clear RMT_CH1_ERR_INT interrupt. 609 */ 610 uint32_t ch1_err_int_clr: 1; 611 /** ch2_tx_end_int_clr : WO; bitpos: [6]; default: 0; 612 * Set this bit to clear RMT_CH2_TX_END_INT interrupt. 613 */ 614 uint32_t ch2_tx_end_int_clr: 1; 615 /** ch2_rx_end_int_clr : WO; bitpos: [7]; default: 0; 616 * Set this bit to clear RMT_CH2_RX_END_INT interrupt. 617 */ 618 uint32_t ch2_rx_end_int_clr: 1; 619 /** ch2_err_int_clr : WO; bitpos: [8]; default: 0; 620 * Set this bit to clear RMT_CH2_ERR_INT interrupt. 621 */ 622 uint32_t ch2_err_int_clr: 1; 623 /** ch3_tx_end_int_clr : WO; bitpos: [9]; default: 0; 624 * Set this bit to clear RMT_CH3_TX_END_INT interrupt. 625 */ 626 uint32_t ch3_tx_end_int_clr: 1; 627 /** ch3_rx_end_int_clr : WO; bitpos: [10]; default: 0; 628 * Set this bit to clear RMT_CH3_RX_END_INT interrupt. 629 */ 630 uint32_t ch3_rx_end_int_clr: 1; 631 /** ch3_err_int_clr : WO; bitpos: [11]; default: 0; 632 * Set this bit to clear RMT_CH3_ERR_INT interrupt. 633 */ 634 uint32_t ch3_err_int_clr: 1; 635 /** ch0_tx_thr_event_int_clr : WO; bitpos: [12]; default: 0; 636 * Set this bit to clear RMT_CH0_TX_THR_EVENT_INT interrupt. 637 */ 638 uint32_t ch0_tx_thr_event_int_clr: 1; 639 /** ch1_tx_thr_event_int_clr : WO; bitpos: [13]; default: 0; 640 * Set this bit to clear RMT_CH1_TX_THR_EVENT_INT interrupt. 641 */ 642 uint32_t ch1_tx_thr_event_int_clr: 1; 643 /** ch2_tx_thr_event_int_clr : WO; bitpos: [14]; default: 0; 644 * Set this bit to clear RMT_CH2_TX_THR_EVENT_INT interrupt. 645 */ 646 uint32_t ch2_tx_thr_event_int_clr: 1; 647 /** ch3_tx_thr_event_int_clr : WO; bitpos: [15]; default: 0; 648 * Set this bit to clear RMT_CH3_TX_THR_EVENT_INT interrupt. 649 */ 650 uint32_t ch3_tx_thr_event_int_clr: 1; 651 /** ch0_tx_loop_int_clr : WO; bitpos: [16]; default: 0; 652 * Set this bit to clear RMT_CH0_TX_LOOP_INT interrupt. 653 */ 654 uint32_t ch0_tx_loop_int_clr: 1; 655 /** ch1_tx_loop_int_clr : WO; bitpos: [17]; default: 0; 656 * Set this bit to clear RMT_CH1_TX_LOOP_INT interrupt. 657 */ 658 uint32_t ch1_tx_loop_int_clr: 1; 659 /** ch2_tx_loop_int_clr : WO; bitpos: [18]; default: 0; 660 * Set this bit to clear RMT_CH2_TX_LOOP_INT interrupt. 661 */ 662 uint32_t ch2_tx_loop_int_clr: 1; 663 /** ch3_tx_loop_int_clr : WO; bitpos: [19]; default: 0; 664 * Set this bit to clear RMT_CH3_TX_LOOP_INT interrupt. 665 */ 666 uint32_t ch3_tx_loop_int_clr: 1; 667 uint32_t reserved_20: 12; 668 }; 669 uint32_t val; 670 } rmt_int_clr_reg_t; 671 672 673 /** Group: Carrier wave duty cycle registers */ 674 /** Type of chncarrier_duty register 675 * Channel n duty cycle configuration register 676 */ 677 typedef union { 678 struct { 679 /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; 680 * This field is used to configure the clock cycles of carrier wave at low level for 681 * channel n. 682 */ 683 uint32_t carrier_low_chn: 16; 684 /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; 685 * This field is used to configure the clock cycles of carrier wave at high level for 686 * channel n. 687 */ 688 uint32_t carrier_high_chn: 16; 689 }; 690 uint32_t val; 691 } rmt_chncarrier_duty_reg_t; 692 693 694 /** Group: Tx event configuration registers */ 695 /** Type of chn_tx_lim register 696 * Channel n Tx event configuration register 697 */ 698 typedef union { 699 struct { 700 /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; 701 * This field is used to configure the maximum entries that channel n can send out. 702 * When RMT_MEM_SIZE_CHn = 1, this field can be set to any value among 0 ~ 128 703 * (64*32/16 = 128). When RMT_MEM_SIZE_CHn > 1, this field can be set to any value 704 * among (0 ~ 128)*RMT_MEM_SIZE_CHn. 705 */ 706 uint32_t tx_lim_chn: 9; 707 /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; 708 * This field is used to configure the maximum loop times when continuous transmission 709 * mode is enabled. 710 */ 711 uint32_t tx_loop_num_chn: 10; 712 /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; 713 * This bit is used to enable loop counting. 714 */ 715 uint32_t tx_loop_cnt_en_chn: 1; 716 /** loop_count_reset_chn : WO; bitpos: [20]; default: 0; 717 * This bit is used to reset loop counting when continuous transmission mode is valid. 718 */ 719 uint32_t loop_count_reset_chn: 1; 720 uint32_t reserved_21: 11; 721 }; 722 uint32_t val; 723 } rmt_chn_tx_lim_reg_t; 724 725 /** Type of tx_sim register 726 * Enable RMT simultaneous transmission 727 */ 728 typedef union { 729 struct { 730 /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; 731 * Set this bit to enable channel 0 to start sending data simultaneously with other 732 * enabled channels. 733 */ 734 uint32_t tx_sim_ch0: 1; 735 /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; 736 * Set this bit to enable channel 1 to start sending data simultaneously with other 737 * enabled channels. 738 */ 739 uint32_t tx_sim_ch1: 1; 740 /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0; 741 * Set this bit to enable channel 2 to start sending data simultaneously with other 742 * enabled channels. 743 */ 744 uint32_t tx_sim_ch2: 1; 745 /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0; 746 * Set this bit to enable channel 3 to start sending data simultaneously with other 747 * enabled channels. 748 */ 749 uint32_t tx_sim_ch3: 1; 750 /** tx_sim_en : R/W; bitpos: [4]; default: 0; 751 * This bit is used to enable multiple channels to start sending data simultaneously. 752 */ 753 uint32_t tx_sim_en: 1; 754 uint32_t reserved_5: 27; 755 }; 756 uint32_t val; 757 } rmt_tx_sim_reg_t; 758 759 760 /** Group: Version register */ 761 /** Type of date register 762 * Version control register 763 */ 764 typedef union { 765 struct { 766 /** date : R/W; bitpos: [31:0]; default: 419898881; 767 * Version control register 768 */ 769 uint32_t date: 32; 770 }; 771 uint32_t val; 772 } rmt_date_reg_t; 773 774 775 typedef struct rmt_dev_t { 776 volatile rmt_chndata_reg_t chndata[4]; 777 volatile struct { 778 rmt_chnconf0_reg_t conf0; 779 rmt_chnconf1_reg_t conf1; 780 } conf_ch[4]; 781 volatile rmt_chnstatus_reg_t chnstatus[4]; 782 volatile rmt_chnaddr_reg_t chnaddr[4]; 783 volatile rmt_int_raw_reg_t int_raw; 784 volatile rmt_int_st_reg_t int_st; 785 volatile rmt_int_ena_reg_t int_ena; 786 volatile rmt_int_clr_reg_t int_clr; 787 volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4]; 788 volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4]; 789 volatile rmt_apb_conf_reg_t apb_conf; 790 volatile rmt_tx_sim_reg_t tx_sim; 791 volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; 792 volatile rmt_chn_rx_carrier_rm_reg_t chn_rx_carrier_rm[4]; 793 uint32_t reserved_09c[24]; 794 volatile rmt_date_reg_t date; 795 } rmt_dev_t; 796 797 798 #ifndef __cplusplus 799 _Static_assert(sizeof(rmt_dev_t) == 0x100, "Invalid size of rmt_dev_t structure"); 800 #endif 801 802 extern rmt_dev_t RMT; 803 804 #ifdef __cplusplus 805 } 806 #endif 807
