1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: PGM Data Register */ 14 /** Type of pgm_data0 register 15 * Register 0 that stores data to be programmed. 16 */ 17 typedef union { 18 struct { 19 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 20 * The content of the 0th 32-bit data to be programmed. 21 */ 22 uint32_t pgm_data_0:32; 23 }; 24 uint32_t val; 25 } efuse_pgm_data0_reg_t; 26 27 /** Type of pgm_data1 register 28 * Register 1 that stores data to be programmed. 29 */ 30 typedef union { 31 struct { 32 /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; 33 * The content of the 1st 32-bit data to be programmed. 34 */ 35 uint32_t pgm_data_1:32; 36 }; 37 uint32_t val; 38 } efuse_pgm_data1_reg_t; 39 40 /** Type of pgm_data2 register 41 * Register 2 that stores data to be programmed. 42 */ 43 typedef union { 44 struct { 45 /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; 46 * The content of the 2nd 32-bit data to be programmed. 47 */ 48 uint32_t pgm_data_2:32; 49 }; 50 uint32_t val; 51 } efuse_pgm_data2_reg_t; 52 53 /** Type of pgm_data3 register 54 * Register 3 that stores data to be programmed. 55 */ 56 typedef union { 57 struct { 58 /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; 59 * The content of the 3rd 32-bit data to be programmed. 60 */ 61 uint32_t pgm_data_3:32; 62 }; 63 uint32_t val; 64 } efuse_pgm_data3_reg_t; 65 66 /** Type of pgm_data4 register 67 * Register 4 that stores data to be programmed. 68 */ 69 typedef union { 70 struct { 71 /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; 72 * The content of the 4th 32-bit data to be programmed. 73 */ 74 uint32_t pgm_data_4:32; 75 }; 76 uint32_t val; 77 } efuse_pgm_data4_reg_t; 78 79 /** Type of pgm_data5 register 80 * Register 5 that stores data to be programmed. 81 */ 82 typedef union { 83 struct { 84 /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; 85 * The content of the 5th 32-bit data to be programmed. 86 */ 87 uint32_t pgm_data_5:32; 88 }; 89 uint32_t val; 90 } efuse_pgm_data5_reg_t; 91 92 /** Type of pgm_data6 register 93 * Register 6 that stores data to be programmed. 94 */ 95 typedef union { 96 struct { 97 /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; 98 * The content of the 6th 32-bit data to be programmed. 99 */ 100 uint32_t pgm_data_6:32; 101 }; 102 uint32_t val; 103 } efuse_pgm_data6_reg_t; 104 105 /** Type of pgm_data7 register 106 * Register 7 that stores data to be programmed. 107 */ 108 typedef union { 109 struct { 110 /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; 111 * The content of the 7th 32-bit data to be programmed. 112 */ 113 uint32_t pgm_data_7:32; 114 }; 115 uint32_t val; 116 } efuse_pgm_data7_reg_t; 117 118 /** Type of pgm_check_value0 register 119 * Register 0 that stores the RS code to be programmed. 120 */ 121 typedef union { 122 struct { 123 /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; 124 * The content of the 0th 32-bit RS code to be programmed. 125 */ 126 uint32_t pgm_rs_data_0:32; 127 }; 128 uint32_t val; 129 } efuse_pgm_check_value0_reg_t; 130 131 /** Type of pgm_check_value1 register 132 * Register 1 that stores the RS code to be programmed. 133 */ 134 typedef union { 135 struct { 136 /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; 137 * The content of the 1st 32-bit RS code to be programmed. 138 */ 139 uint32_t pgm_rs_data_1:32; 140 }; 141 uint32_t val; 142 } efuse_pgm_check_value1_reg_t; 143 144 /** Type of pgm_check_value2 register 145 * Register 2 that stores the RS code to be programmed. 146 */ 147 typedef union { 148 struct { 149 /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; 150 * The content of the 2nd 32-bit RS code to be programmed. 151 */ 152 uint32_t pgm_rs_data_2:32; 153 }; 154 uint32_t val; 155 } efuse_pgm_check_value2_reg_t; 156 157 158 /** Group: Read Data Register */ 159 /** Type of rd_wr_dis register 160 * BLOCK0 data register 0. 161 */ 162 typedef union { 163 struct { 164 /** wr_dis : RO; bitpos: [7:0]; default: 0; 165 * Disable programming of individual eFuses. 166 */ 167 uint32_t wr_dis:8; 168 /** reserved_0_8 : RW; bitpos: [31:8]; default: 0; */ 169 uint32_t reserved_0_8:24; 170 }; 171 uint32_t val; 172 } efuse_rd_wr_dis_reg_t; 173 174 /** Type of rd_repeat_data0 register 175 * BLOCK0 data register 1. 176 */ 177 typedef union { 178 struct { 179 /** rd_dis : RO; bitpos: [1:0]; default: 0; 180 * The bit be set to disable software read high/low 128-bit of BLK3. 181 */ 182 uint32_t rd_dis:2; 183 /** wdt_delay_sel : RO; bitpos: [3:2]; default: 0; 184 * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 185 * 80000. 2: 160000. 3:320000. 186 */ 187 uint32_t wdt_delay_sel:2; 188 /** dis_pad_jtag : RO; bitpos: [4]; default: 0; 189 * Set this bit to disable pad jtag. 190 */ 191 uint32_t dis_pad_jtag:1; 192 /** dis_download_icache : RO; bitpos: [5]; default: 0; 193 * The bit be set to disable icache in download mode. 194 */ 195 uint32_t dis_download_icache:1; 196 /** dis_download_manual_encrypt : RO; bitpos: [6]; default: 0; 197 * The bit be set to disable manual encryption. 198 */ 199 uint32_t dis_download_manual_encrypt:1; 200 /** spi_boot_crypt_cnt : RO; bitpos: [9:7]; default: 0; 201 * These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even 202 * number of 1: disable. 203 */ 204 uint32_t spi_boot_crypt_cnt:3; 205 /** xts_key_length_256 : RO; bitpos: [10]; default: 0; 206 * The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, 207 * XTS_AES use 128-bit eFuse data in BLOCK3. 208 */ 209 uint32_t xts_key_length_256:1; 210 /** uart_print_control : RO; bitpos: [12:11]; default: 0; 211 * Set this bit to disable usb printing. 212 */ 213 uint32_t uart_print_control:2; 214 /** force_send_resume : RO; bitpos: [13]; default: 0; 215 * Set this bit to force ROM code to send a resume command during SPI boot. 216 */ 217 uint32_t force_send_resume:1; 218 /** dis_download_mode : RO; bitpos: [14]; default: 0; 219 * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). 220 */ 221 uint32_t dis_download_mode:1; 222 /** dis_direct_boot : RO; bitpos: [15]; default: 0; 223 * This bit set means disable direct_boot mode. 224 */ 225 uint32_t dis_direct_boot:1; 226 /** enable_security_download : RO; bitpos: [16]; default: 0; 227 * Set this bit to enable secure UART download mode. 228 */ 229 uint32_t enable_security_download:1; 230 /** flash_tpuw : RO; bitpos: [20:17]; default: 0; 231 * Configures flash waiting time after power-up, in unit of ms. If the value is less 232 * than 15, the waiting time is the configurable value. Otherwise, the waiting time 233 * is twice the configurable value. 234 */ 235 uint32_t flash_tpuw:4; 236 /** secure_boot_en : RO; bitpos: [21]; default: 0; 237 * The bit be set to enable secure boot. 238 */ 239 uint32_t secure_boot_en:1; 240 /** secure_version : R; bitpos: [25:22]; default: 0; 241 * Secure version for anti-rollback 242 */ 243 uint32_t secure_version:4; 244 /** custom_mac_used : R; bitpos: [26]; default: 0; 245 * True if MAC_CUSTOM is burned 246 */ 247 uint32_t custom_mac_used:1; 248 /** disable_wafer_version_major : R; bitpos: [27]; default: 0; 249 * Disables check of wafer version major 250 */ 251 uint32_t disable_wafer_version_major:1; 252 /** disable_blk_version_major : R; bitpos: [28]; default: 0; 253 * Disables check of blk version major 254 */ 255 uint32_t disable_blk_version_major:1; 256 /** reserved_0_61 : R; bitpos: [31:29]; default: 0; 257 * reserved 258 */ 259 uint32_t reserved_0_61:3; 260 }; 261 uint32_t val; 262 } efuse_rd_repeat_data0_reg_t; 263 264 /** Type of rd_blk1_data0 register 265 * BLOCK1 data register 0. 266 */ 267 typedef union { 268 struct { 269 /** custom_mac : R; bitpos: [31:0]; default: 0; 270 * Custom MAC address 271 */ 272 uint32_t custom_mac:32; 273 }; 274 uint32_t val; 275 } efuse_rd_blk1_data0_reg_t; 276 277 /** Type of rd_blk1_data1 register 278 * BLOCK1 data register 1. 279 */ 280 typedef union { 281 struct { 282 /** custom_mac_1 : R; bitpos: [15:0]; default: 0; 283 * Custom MAC address 284 */ 285 uint32_t custom_mac_1:16; 286 /** reserved_1_48 : R; bitpos: [31:16]; default: 0; 287 * reserved 288 */ 289 uint32_t reserved_1_48:16; 290 }; 291 uint32_t val; 292 } efuse_rd_blk1_data1_reg_t; 293 294 /** Type of rd_blk1_data2 register 295 * BLOCK1 data register 2. 296 */ 297 typedef union { 298 struct { 299 /** system_data2 : RO; bitpos: [23:0]; default: 0; 300 * Stores the bits [64:87] of system data. 301 */ 302 uint32_t system_data2:24; 303 uint32_t reserved_24:8; 304 }; 305 uint32_t val; 306 } efuse_rd_blk1_data2_reg_t; 307 308 /** Type of rd_blk2_data0 register 309 * Register 0 of BLOCK2. 310 */ 311 typedef union { 312 struct { 313 /** mac : R; bitpos: [31:0]; default: 0; 314 * MAC address 315 */ 316 uint32_t mac:32; 317 }; 318 uint32_t val; 319 } efuse_rd_blk2_data0_reg_t; 320 321 /** Type of rd_blk2_data1 register 322 * Register 1 of BLOCK2. 323 */ 324 typedef union { 325 struct { 326 /** mac_1 : R; bitpos: [15:0]; default: 0; 327 * MAC address 328 */ 329 uint32_t mac_1:16; 330 /** wafer_version_minor : R; bitpos: [19:16]; default: 0; 331 * WAFER_VERSION_MINOR 332 */ 333 uint32_t wafer_version_minor:4; 334 /** wafer_version_major : R; bitpos: [21:20]; default: 0; 335 * WAFER_VERSION_MAJOR 336 */ 337 uint32_t wafer_version_major:2; 338 /** pkg_version : R; bitpos: [24:22]; default: 0; 339 * EFUSE_PKG_VERSION 340 */ 341 uint32_t pkg_version:3; 342 /** blk_version_minor : R; bitpos: [27:25]; default: 0; 343 * Minor version of BLOCK2 344 */ 345 uint32_t blk_version_minor:3; 346 /** blk_version_major : R; bitpos: [29:28]; default: 0; 347 * Major version of BLOCK2 348 */ 349 uint32_t blk_version_major:2; 350 /** ocode : R; bitpos: [31:30]; default: 0; 351 * OCode 352 */ 353 uint32_t ocode:2; 354 }; 355 uint32_t val; 356 } efuse_rd_blk2_data1_reg_t; 357 358 /** Type of rd_blk2_data2 register 359 * Register 2 of BLOCK2. 360 */ 361 typedef union { 362 struct { 363 /** ocode_1 : R; bitpos: [4:0]; default: 0; 364 * OCode 365 */ 366 uint32_t ocode_1:5; 367 /** temp_calib : R; bitpos: [13:5]; default: 0; 368 * Temperature calibration data 369 */ 370 uint32_t temp_calib:9; 371 /** adc1_init_code_atten0 : R; bitpos: [21:14]; default: 0; 372 * ADC1 init code at atten0 373 */ 374 uint32_t adc1_init_code_atten0:8; 375 /** adc1_init_code_atten3 : R; bitpos: [26:22]; default: 0; 376 * ADC1 init code at atten3 377 */ 378 uint32_t adc1_init_code_atten3:5; 379 /** adc1_cal_vol_atten0 : R; bitpos: [31:27]; default: 0; 380 * ADC1 calibration voltage at atten0 381 */ 382 uint32_t adc1_cal_vol_atten0:5; 383 }; 384 uint32_t val; 385 } efuse_rd_blk2_data2_reg_t; 386 387 /** Type of rd_blk2_data3 register 388 * Register 3 of BLOCK2. 389 */ 390 typedef union { 391 struct { 392 /** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0; 393 * ADC1 calibration voltage at atten0 394 */ 395 uint32_t adc1_cal_vol_atten0_1:3; 396 /** adc1_cal_vol_atten3 : R; bitpos: [8:3]; default: 0; 397 * ADC1 calibration voltage at atten3 398 */ 399 uint32_t adc1_cal_vol_atten3:6; 400 /** dig_dbias_hvt : R; bitpos: [13:9]; default: 0; 401 * BLOCK2 digital dbias when hvt 402 */ 403 uint32_t dig_dbias_hvt:5; 404 /** dig_ldo_slp_dbias2 : R; bitpos: [20:14]; default: 0; 405 * BLOCK2 DIG_LDO_DBG0_DBIAS2 406 */ 407 uint32_t dig_ldo_slp_dbias2:7; 408 /** dig_ldo_slp_dbias26 : R; bitpos: [28:21]; default: 0; 409 * BLOCK2 DIG_LDO_DBG0_DBIAS26 410 */ 411 uint32_t dig_ldo_slp_dbias26:8; 412 /** dig_ldo_act_dbias26 : R; bitpos: [31:29]; default: 0; 413 * BLOCK2 DIG_LDO_ACT_DBIAS26 414 */ 415 uint32_t dig_ldo_act_dbias26:3; 416 }; 417 uint32_t val; 418 } efuse_rd_blk2_data3_reg_t; 419 420 /** Type of rd_blk2_data4 register 421 * Register 4 of BLOCK2. 422 */ 423 typedef union { 424 struct { 425 /** dig_ldo_act_dbias26_1 : R; bitpos: [2:0]; default: 0; 426 * BLOCK2 DIG_LDO_ACT_DBIAS26 427 */ 428 uint32_t dig_ldo_act_dbias26_1:3; 429 /** dig_ldo_act_stepd10 : R; bitpos: [6:3]; default: 0; 430 * BLOCK2 DIG_LDO_ACT_STEPD10 431 */ 432 uint32_t dig_ldo_act_stepd10:4; 433 /** rtc_ldo_slp_dbias13 : R; bitpos: [13:7]; default: 0; 434 * BLOCK2 DIG_LDO_SLP_DBIAS13 435 */ 436 uint32_t rtc_ldo_slp_dbias13:7; 437 /** rtc_ldo_slp_dbias29 : R; bitpos: [22:14]; default: 0; 438 * BLOCK2 DIG_LDO_SLP_DBIAS29 439 */ 440 uint32_t rtc_ldo_slp_dbias29:9; 441 /** rtc_ldo_slp_dbias31 : R; bitpos: [28:23]; default: 0; 442 * BLOCK2 DIG_LDO_SLP_DBIAS31 443 */ 444 uint32_t rtc_ldo_slp_dbias31:6; 445 /** rtc_ldo_act_dbias31 : R; bitpos: [31:29]; default: 0; 446 * BLOCK2 DIG_LDO_ACT_DBIAS31 447 */ 448 uint32_t rtc_ldo_act_dbias31:3; 449 }; 450 uint32_t val; 451 } efuse_rd_blk2_data4_reg_t; 452 453 /** Type of rd_blk2_data5 register 454 * Register 5 of BLOCK2. 455 */ 456 typedef union { 457 struct { 458 /** rtc_ldo_act_dbias31_1 : R; bitpos: [2:0]; default: 0; 459 * BLOCK2 DIG_LDO_ACT_DBIAS31 460 */ 461 uint32_t rtc_ldo_act_dbias31_1:3; 462 /** rtc_ldo_act_dbias13 : R; bitpos: [10:3]; default: 0; 463 * BLOCK2 DIG_LDO_ACT_DBIAS13 464 */ 465 uint32_t rtc_ldo_act_dbias13:8; 466 /** reserved_2_171 : R; bitpos: [31:11]; default: 0; 467 * reserved 468 */ 469 uint32_t reserved_2_171:21; 470 }; 471 uint32_t val; 472 } efuse_rd_blk2_data5_reg_t; 473 474 /** Type of rd_blk2_data6 register 475 * Register 6 of BLOCK2. 476 */ 477 typedef union { 478 struct { 479 /** adc_calibration_3 : RO; bitpos: [10:0]; default: 0; 480 * Store the bit [86:96] of ADC calibration data. 481 */ 482 uint32_t adc_calibration_3:11; 483 /** blk2_reserved_data_0 : RO; bitpos: [31:11]; default: 0; 484 * Store the bit [0:20] of block2 reserved data. 485 */ 486 uint32_t blk2_reserved_data_0:21; 487 }; 488 uint32_t val; 489 } efuse_rd_blk2_data6_reg_t; 490 491 /** Type of rd_blk2_data7 register 492 * Register 7 of BLOCK2. 493 */ 494 typedef union { 495 struct { 496 /** blk2_reserved_data_1 : RO; bitpos: [31:0]; default: 0; 497 * Store the bit [21:52] of block2 reserved data. 498 */ 499 uint32_t blk2_reserved_data_1:32; 500 }; 501 uint32_t val; 502 } efuse_rd_blk2_data7_reg_t; 503 504 /** Type of rd_blk3_data0 register 505 * Register 0 of BLOCK3. 506 */ 507 typedef union { 508 struct { 509 /** blk3_data0 : RO; bitpos: [31:0]; default: 0; 510 * Store the first 32-bit of Block3. 511 */ 512 uint32_t blk3_data0:32; 513 }; 514 uint32_t val; 515 } efuse_rd_blk3_data0_reg_t; 516 517 /** Type of rd_blk3_data1 register 518 * Register 1 of BLOCK3. 519 */ 520 typedef union { 521 struct { 522 /** blk3_data1 : RO; bitpos: [31:0]; default: 0; 523 * Store the second 32-bit of Block3. 524 */ 525 uint32_t blk3_data1:32; 526 }; 527 uint32_t val; 528 } efuse_rd_blk3_data1_reg_t; 529 530 /** Type of rd_blk3_data2 register 531 * Register 2 of BLOCK3. 532 */ 533 typedef union { 534 struct { 535 /** blk3_data2 : RO; bitpos: [31:0]; default: 0; 536 * Store the third 32-bit of Block3. 537 */ 538 uint32_t blk3_data2:32; 539 }; 540 uint32_t val; 541 } efuse_rd_blk3_data2_reg_t; 542 543 /** Type of rd_blk3_data3 register 544 * Register 3 of BLOCK3. 545 */ 546 typedef union { 547 struct { 548 /** blk3_data3 : RO; bitpos: [31:0]; default: 0; 549 * Store the fourth 32-bit of Block3. 550 */ 551 uint32_t blk3_data3:32; 552 }; 553 uint32_t val; 554 } efuse_rd_blk3_data3_reg_t; 555 556 /** Type of rd_blk3_data4 register 557 * Register 4 of BLOCK3. 558 */ 559 typedef union { 560 struct { 561 /** blk3_data4 : RO; bitpos: [31:0]; default: 0; 562 * Store the fifth 32-bit of Block3. 563 */ 564 uint32_t blk3_data4:32; 565 }; 566 uint32_t val; 567 } efuse_rd_blk3_data4_reg_t; 568 569 /** Type of rd_blk3_data5 register 570 * Register 5 of BLOCK3. 571 */ 572 typedef union { 573 struct { 574 /** blk3_data5 : RO; bitpos: [31:0]; default: 0; 575 * Store the sixth 32-bit of Block3. 576 */ 577 uint32_t blk3_data5:32; 578 }; 579 uint32_t val; 580 } efuse_rd_blk3_data5_reg_t; 581 582 /** Type of rd_blk3_data6 register 583 * Register 6 of BLOCK3. 584 */ 585 typedef union { 586 struct { 587 /** blk3_data6 : RO; bitpos: [31:0]; default: 0; 588 * Store the seventh 32-bit of Block3. 589 */ 590 uint32_t blk3_data6:32; 591 }; 592 uint32_t val; 593 } efuse_rd_blk3_data6_reg_t; 594 595 /** Type of rd_blk3_data7 register 596 * Register 7 of BLOCK3. 597 */ 598 typedef union { 599 struct { 600 /** blk3_data7 : RO; bitpos: [31:0]; default: 0; 601 * Store the eighth 32-bit of Block3. 602 */ 603 uint32_t blk3_data7:32; 604 }; 605 uint32_t val; 606 } efuse_rd_blk3_data7_reg_t; 607 608 609 /** Group: Report Register */ 610 /** Type of rd_repeat_err register 611 * Programming error record register 0 of BLOCK0. 612 */ 613 typedef union { 614 struct { 615 /** rd_dis_err : RO; bitpos: [1:0]; default: 0; 616 * If any bit in RD_DIS is 1, then it indicates a programming error. 617 */ 618 uint32_t rd_dis_err:2; 619 /** wdt_delay_sel_err : RO; bitpos: [3:2]; default: 0; 620 * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. 621 */ 622 uint32_t wdt_delay_sel_err:2; 623 /** dis_pad_jtag_err : RO; bitpos: [4]; default: 0; 624 * If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error. 625 */ 626 uint32_t dis_pad_jtag_err:1; 627 /** dis_download_icache_err : RO; bitpos: [5]; default: 0; 628 * If any bit in this filed is 1, then it indicates a programming error. 629 */ 630 uint32_t dis_download_icache_err:1; 631 /** dis_download_manual_encrypt_err : RO; bitpos: [6]; default: 0; 632 * If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming 633 * error. 634 */ 635 uint32_t dis_download_manual_encrypt_err:1; 636 /** spi_boot_encrypt_decrypt_cnt_err : RO; bitpos: [9:7]; default: 0; 637 * If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming 638 * error. 639 */ 640 uint32_t spi_boot_encrypt_decrypt_cnt_err:3; 641 /** xts_key_length_256_err : RO; bitpos: [10]; default: 0; 642 * If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error. 643 */ 644 uint32_t xts_key_length_256_err:1; 645 /** uart_print_control_err : RO; bitpos: [12:11]; default: 0; 646 * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. 647 */ 648 uint32_t uart_print_control_err:2; 649 /** force_send_resume_err : RO; bitpos: [13]; default: 0; 650 * If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error. 651 */ 652 uint32_t force_send_resume_err:1; 653 /** dis_download_mode_err : RO; bitpos: [14]; default: 0; 654 * If any bit in this filed is 1, then it indicates a programming error. 655 */ 656 uint32_t dis_download_mode_err:1; 657 /** dis_direct_boot_err : RO; bitpos: [15]; default: 0; 658 * If any bit in this filed is 1, then it indicates a programming error. 659 */ 660 uint32_t dis_direct_boot_err:1; 661 /** enable_security_download_err : RO; bitpos: [16]; default: 0; 662 * If any bit in this filed is 1, then it indicates a programming error. 663 */ 664 uint32_t enable_security_download_err:1; 665 /** flash_tpuw_err : RO; bitpos: [20:17]; default: 0; 666 * If any bit in this filed is 1, then it indicates a programming error. 667 */ 668 uint32_t flash_tpuw_err:4; 669 /** secure_boot_en_err : RO; bitpos: [21]; default: 0; 670 * If any bit in this filed is 1, then it indicates a programming error. 671 */ 672 uint32_t secure_boot_en_err:1; 673 /** rpt4_reserved_err : RO; bitpos: [31:22]; default: 0; 674 * Reserved. 675 */ 676 uint32_t rpt4_reserved_err:10; 677 }; 678 uint32_t val; 679 } efuse_rd_repeat_err_reg_t; 680 681 /** Type of rd_rs_err register 682 * Programming error record register 0 of BLOCK1-10. 683 */ 684 typedef union { 685 struct { 686 /** blk1_err_num : RO; bitpos: [2:0]; default: 0; 687 * The value of this signal means the number of error bytes in block1. 688 */ 689 uint32_t blk1_err_num:3; 690 /** blk1_fail : RO; bitpos: [3]; default: 0; 691 * 0: Means no failure and that the data of block1 is reliable 1: Means that 692 * programming user data failed and the number of error bytes is over 6. 693 */ 694 uint32_t blk1_fail:1; 695 /** blk2_err_num : RO; bitpos: [6:4]; default: 0; 696 * The value of this signal means the number of error bytes in block2. 697 */ 698 uint32_t blk2_err_num:3; 699 /** blk2_fail : RO; bitpos: [7]; default: 0; 700 * 0: Means no failure and that the data of block2 is reliable 1: Means that 701 * programming user data failed and the number of error bytes is over 6. 702 */ 703 uint32_t blk2_fail:1; 704 /** blk3_err_num : RO; bitpos: [10:8]; default: 0; 705 * The value of this signal means the number of error bytes in block3. 706 */ 707 uint32_t blk3_err_num:3; 708 /** blk3_fail : RO; bitpos: [11]; default: 0; 709 * 0: Means no failure and that the block3 data is reliable 1: Means that programming 710 * user data failed and the number of error bytes is over 6. 711 */ 712 uint32_t blk3_fail:1; 713 uint32_t reserved_12:20; 714 }; 715 uint32_t val; 716 } efuse_rd_rs_err_reg_t; 717 718 719 /** Group: Configuration Register */ 720 /** Type of clk register 721 * eFuse clcok configuration register. 722 */ 723 typedef union { 724 struct { 725 /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; 726 * Set this bit to force eFuse SRAM into power-saving mode. 727 */ 728 uint32_t efuse_mem_force_pd:1; 729 /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; 730 * Set this bit and force to activate clock signal of eFuse SRAM. 731 */ 732 uint32_t mem_clk_force_on:1; 733 /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; 734 * Set this bit to force eFuse SRAM into working mode. 735 */ 736 uint32_t efuse_mem_force_pu:1; 737 uint32_t reserved_3:13; 738 /** clk_en : R/W; bitpos: [16]; default: 0; 739 * Set this bit and force to enable clock signal of eFuse memory. 740 */ 741 uint32_t clk_en:1; 742 uint32_t reserved_17:15; 743 }; 744 uint32_t val; 745 } efuse_clk_reg_t; 746 747 /** Type of conf register 748 * eFuse operation mode configuraiton register 749 */ 750 typedef union { 751 struct { 752 /** op_code : R/W; bitpos: [15:0]; default: 0; 753 * 0x5A5A: Operate programming command 0x5AA5: Operate read command. 754 */ 755 uint32_t op_code:16; 756 uint32_t reserved_16:16; 757 }; 758 uint32_t val; 759 } efuse_conf_reg_t; 760 761 /** Type of cmd register 762 * eFuse command register. 763 */ 764 typedef union { 765 struct { 766 /** read_cmd : R/W/SC; bitpos: [0]; default: 0; 767 * Set this bit to send read command. 768 */ 769 uint32_t read_cmd:1; 770 /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; 771 * Set this bit to send programming command. 772 */ 773 uint32_t pgm_cmd:1; 774 /** blk_num : R/W; bitpos: [3:2]; default: 0; 775 * The serial number of the block to be programmed. Value 0-3 corresponds to block 776 * number 0-3, respectively. 777 */ 778 uint32_t blk_num:2; 779 uint32_t reserved_4:28; 780 }; 781 uint32_t val; 782 } efuse_cmd_reg_t; 783 784 /** Type of dac_conf register 785 * Controls the eFuse programming voltage. 786 */ 787 typedef union { 788 struct { 789 /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; 790 * Controls the division factor of the rising clock of the programming voltage. 791 */ 792 uint32_t dac_clk_div:8; 793 /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; 794 * Don't care. 795 */ 796 uint32_t dac_clk_pad_sel:1; 797 /** dac_num : R/W; bitpos: [16:9]; default: 255; 798 * Controls the rising period of the programming voltage. 799 */ 800 uint32_t dac_num:8; 801 /** oe_clr : R/W; bitpos: [17]; default: 0; 802 * Reduces the power supply of the programming voltage. 803 */ 804 uint32_t oe_clr:1; 805 uint32_t reserved_18:14; 806 }; 807 uint32_t val; 808 } efuse_dac_conf_reg_t; 809 810 /** Type of rd_tim_conf register 811 * Configures read timing parameters. 812 */ 813 typedef union { 814 struct { 815 /** thr_a : R/W; bitpos: [7:0]; default: 1; 816 * Configures hold time for efuse read. 817 */ 818 uint32_t thr_a:8; 819 /** trd : R/W; bitpos: [15:8]; default: 2; 820 * Configures pulse time for efuse read. 821 */ 822 uint32_t trd:8; 823 /** tsur_a : R/W; bitpos: [23:16]; default: 1; 824 * Configures setup time for efuse read. 825 */ 826 uint32_t tsur_a:8; 827 /** read_init_num : R/W; bitpos: [31:24]; default: 18; 828 * Configures the initial read time of eFuse. 829 */ 830 uint32_t read_init_num:8; 831 }; 832 uint32_t val; 833 } efuse_rd_tim_conf_reg_t; 834 835 /** Type of wr_tim_conf0 register 836 * Configurarion register 0 of eFuse programming timing parameters. 837 */ 838 typedef union { 839 struct { 840 /** thp_a : R/W; bitpos: [7:0]; default: 1; 841 * Configures hold time for efuse program. 842 */ 843 uint32_t thp_a:8; 844 /** tpgm_inactive : R/W; bitpos: [15:8]; default: 1; 845 * Configures pulse time for burning '0' bit. 846 */ 847 uint32_t tpgm_inactive:8; 848 /** tpgm : R/W; bitpos: [31:16]; default: 200; 849 * Configures pulse time for burning '1' bit. 850 */ 851 uint32_t tpgm:16; 852 }; 853 uint32_t val; 854 } efuse_wr_tim_conf0_reg_t; 855 856 /** Type of wr_tim_conf1 register 857 * Configurarion register 1 of eFuse programming timing parameters. 858 */ 859 typedef union { 860 struct { 861 /** tsup_a : R/W; bitpos: [7:0]; default: 1; 862 * Configures setup time for efuse program. 863 */ 864 uint32_t tsup_a:8; 865 /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; 866 * Configures the power up time for VDDQ. 867 */ 868 uint32_t pwr_on_num:16; 869 uint32_t reserved_24:8; 870 }; 871 uint32_t val; 872 } efuse_wr_tim_conf1_reg_t; 873 874 /** Type of wr_tim_conf2 register 875 * Configurarion register 2 of eFuse programming timing parameters. 876 */ 877 typedef union { 878 struct { 879 /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; 880 * Configures the power outage time for VDDQ. 881 */ 882 uint32_t pwr_off_num:16; 883 uint32_t reserved_16:16; 884 }; 885 uint32_t val; 886 } efuse_wr_tim_conf2_reg_t; 887 888 889 /** Group: Status Register */ 890 /** Type of status register 891 * eFuse status register. 892 */ 893 typedef union { 894 struct { 895 /** state : RO; bitpos: [3:0]; default: 0; 896 * Indicates the state of the eFuse state machine. 897 */ 898 uint32_t state:4; 899 /** otp_load_sw : RO; bitpos: [4]; default: 0; 900 * The value of OTP_LOAD_SW. 901 */ 902 uint32_t otp_load_sw:1; 903 /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; 904 * The value of OTP_VDDQ_C_SYNC2. 905 */ 906 uint32_t otp_vddq_c_sync2:1; 907 /** otp_strobe_sw : RO; bitpos: [6]; default: 0; 908 * The value of OTP_STROBE_SW. 909 */ 910 uint32_t otp_strobe_sw:1; 911 /** otp_csb_sw : RO; bitpos: [7]; default: 0; 912 * The value of OTP_CSB_SW. 913 */ 914 uint32_t otp_csb_sw:1; 915 /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; 916 * The value of OTP_PGENB_SW. 917 */ 918 uint32_t otp_pgenb_sw:1; 919 /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; 920 * The value of OTP_VDDQ_IS_SW. 921 */ 922 uint32_t otp_vddq_is_sw:1; 923 /** blk0_valid_bit_cnt : RO; bitpos: [15:10]; default: 0; 924 * Record the number of bit '1' in BLOCK0. 925 */ 926 uint32_t blk0_valid_bit_cnt:6; 927 uint32_t reserved_16:16; 928 }; 929 uint32_t val; 930 } efuse_status_reg_t; 931 932 933 /** Group: Interrupt Register */ 934 /** Type of int_raw register 935 * eFuse raw interrupt register. 936 */ 937 typedef union { 938 struct { 939 /** read_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 940 * The raw bit signal for read_done interrupt. 941 */ 942 uint32_t read_done_int_raw:1; 943 /** pgm_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; 944 * The raw bit signal for pgm_done interrupt. 945 */ 946 uint32_t pgm_done_int_raw:1; 947 uint32_t reserved_2:30; 948 }; 949 uint32_t val; 950 } efuse_int_raw_reg_t; 951 952 /** Type of int_st register 953 * eFuse interrupt status register. 954 */ 955 typedef union { 956 struct { 957 /** read_done_int_st : RO; bitpos: [0]; default: 0; 958 * The status signal for read_done interrupt. 959 */ 960 uint32_t read_done_int_st:1; 961 /** pgm_done_int_st : RO; bitpos: [1]; default: 0; 962 * The status signal for pgm_done interrupt. 963 */ 964 uint32_t pgm_done_int_st:1; 965 uint32_t reserved_2:30; 966 }; 967 uint32_t val; 968 } efuse_int_st_reg_t; 969 970 /** Type of int_ena register 971 * eFuse interrupt enable register. 972 */ 973 typedef union { 974 struct { 975 /** read_done_int_ena : R/W; bitpos: [0]; default: 0; 976 * The enable signal for read_done interrupt. 977 */ 978 uint32_t read_done_int_ena:1; 979 /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; 980 * The enable signal for pgm_done interrupt. 981 */ 982 uint32_t pgm_done_int_ena:1; 983 uint32_t reserved_2:30; 984 }; 985 uint32_t val; 986 } efuse_int_ena_reg_t; 987 988 /** Type of int_clr register 989 * eFuse interrupt clear register. 990 */ 991 typedef union { 992 struct { 993 /** read_done_int_clr : WT; bitpos: [0]; default: 0; 994 * The clear signal for read_done interrupt. 995 */ 996 uint32_t read_done_int_clr:1; 997 /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; 998 * The clear signal for pgm_done interrupt. 999 */ 1000 uint32_t pgm_done_int_clr:1; 1001 uint32_t reserved_2:30; 1002 }; 1003 uint32_t val; 1004 } efuse_int_clr_reg_t; 1005 1006 1007 /** Group: Version Register */ 1008 /** Type of date register 1009 * eFuse version register. 1010 */ 1011 typedef union { 1012 struct { 1013 /** date : R/W; bitpos: [27:0]; default: 34636176; 1014 * Stores eFuse version. 1015 */ 1016 uint32_t date:28; 1017 uint32_t reserved_28:4; 1018 }; 1019 uint32_t val; 1020 } efuse_date_reg_t; 1021 1022 1023 typedef struct { 1024 volatile efuse_pgm_data0_reg_t pgm_data0; 1025 volatile efuse_pgm_data1_reg_t pgm_data1; 1026 volatile efuse_pgm_data2_reg_t pgm_data2; 1027 volatile efuse_pgm_data3_reg_t pgm_data3; 1028 volatile efuse_pgm_data4_reg_t pgm_data4; 1029 volatile efuse_pgm_data5_reg_t pgm_data5; 1030 volatile efuse_pgm_data6_reg_t pgm_data6; 1031 volatile efuse_pgm_data7_reg_t pgm_data7; 1032 volatile efuse_pgm_check_value0_reg_t pgm_check_value0; 1033 volatile efuse_pgm_check_value1_reg_t pgm_check_value1; 1034 volatile efuse_pgm_check_value2_reg_t pgm_check_value2; 1035 volatile efuse_rd_wr_dis_reg_t rd_wr_dis; 1036 volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; 1037 volatile efuse_rd_blk1_data0_reg_t rd_blk1_data0; 1038 volatile efuse_rd_blk1_data1_reg_t rd_blk1_data1; 1039 volatile efuse_rd_blk1_data2_reg_t rd_blk1_data2; 1040 volatile efuse_rd_blk2_data0_reg_t rd_blk2_data0; 1041 volatile efuse_rd_blk2_data1_reg_t rd_blk2_data1; 1042 volatile efuse_rd_blk2_data2_reg_t rd_blk2_data2; 1043 volatile efuse_rd_blk2_data3_reg_t rd_blk2_data3; 1044 volatile efuse_rd_blk2_data4_reg_t rd_blk2_data4; 1045 volatile efuse_rd_blk2_data5_reg_t rd_blk2_data5; 1046 volatile efuse_rd_blk2_data6_reg_t rd_blk2_data6; 1047 volatile efuse_rd_blk2_data7_reg_t rd_blk2_data7; 1048 volatile efuse_rd_blk3_data0_reg_t rd_blk3_data0; 1049 volatile efuse_rd_blk3_data1_reg_t rd_blk3_data1; 1050 volatile efuse_rd_blk3_data2_reg_t rd_blk3_data2; 1051 volatile efuse_rd_blk3_data3_reg_t rd_blk3_data3; 1052 volatile efuse_rd_blk3_data4_reg_t rd_blk3_data4; 1053 volatile efuse_rd_blk3_data5_reg_t rd_blk3_data5; 1054 volatile efuse_rd_blk3_data6_reg_t rd_blk3_data6; 1055 volatile efuse_rd_blk3_data7_reg_t rd_blk3_data7; 1056 volatile efuse_rd_repeat_err_reg_t rd_repeat_err; 1057 volatile efuse_rd_rs_err_reg_t rd_rs_err; 1058 volatile efuse_clk_reg_t clk; 1059 volatile efuse_conf_reg_t conf; 1060 volatile efuse_status_reg_t status; 1061 volatile efuse_cmd_reg_t cmd; 1062 volatile efuse_int_raw_reg_t int_raw; 1063 volatile efuse_int_st_reg_t int_st; 1064 uint32_t reserved_0a0[24]; 1065 volatile efuse_int_ena_reg_t int_ena; 1066 volatile efuse_int_clr_reg_t int_clr; 1067 volatile efuse_dac_conf_reg_t dac_conf; 1068 volatile efuse_rd_tim_conf_reg_t rd_tim_conf; 1069 volatile efuse_wr_tim_conf0_reg_t wr_tim_conf0; 1070 volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; 1071 volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; 1072 uint32_t reserved_11c[56]; 1073 volatile efuse_date_reg_t date; 1074 } efuse_dev_t; 1075 1076 extern efuse_dev_t EFUSE; 1077 1078 #ifndef __cplusplus 1079 _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); 1080 #endif 1081 1082 #ifdef __cplusplus 1083 } 1084 #endif 1085
