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/hal_espressif-latest/zephyr/esp32/src/hal/
Dwindowspill_asm.S129 rsr.windowstart a3
130 srl a2, a3 // a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar
131 sll a3, a3 // a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar)
132 bgez a3, .Linvalid_ws // verify that msbit is indeed set
134 srli a3, a3, 32-WSBITS // a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4)
135 or a2, a2, a3 // a2 is 0... | 1yyyyyxxxxxxxxxx
150 neg a3, a2 // keep only the least-significant bit set of a2 ...
151 and a3, a3, a2 // ... in a3
152 nsau a3, a3 // get index of that bit, numbered from msbit (32 if absent)
153 ssl a3 // set sar = 32 - a3 = bit index numbered from lsbit + 1
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/hal_espressif-latest/components/bt/controller/esp32/
Dhli_vectors.S78 s32i a3, a0, 12
118 movi a3, _l4_save_ctx + 4 * 4
124 s32i a4, a3, 0
125 s32i a5, a3, 4
126 s32i a6, a3, 8
127 s32i a7, a3, 12
128 s32i a8, a3, 16
129 s32i a9, a3, 20
130 s32i a10, a3, 24
131 s32i a11, a3, 28
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/hal_espressif-latest/components/xtensa/include/xtensa/
Dcacheattrasm.h115 movi a3, XCHAL_SPANNING_WAY
116 1: add a3, a3, a5 // next segment
117 r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
122 bgeui a3, 16, 1b
187 srl a5, a3 // ...and get CA's mask bit in a5 bit 0
217 movi a3, XCHAL_FCA_ENAMASK
237 movi a3, XCHAL_LSCA_ENAMASK
257 movi a3, XCHAL_ALLCA_ENAMASK
260 movi a3, XCHAL_FCA_ENAMASK
263 movi a3, XCHAL_LSCA_ENAMASK
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Dsemihosting.h29 register long a3 asm ("a3") = (long)data; in semihosting_call_noerrno()
33 : "+r"(a2) : "r"(a3) in semihosting_call_noerrno()
Dxtensa_context.h123 STRUCT_FIELD (long, 4, XT_STK_A3, a3)
249 STRUCT_FIELD (long, 4, XT_SOL_A3, a3)
Dxtruntime-frames.h102 STRUCT_FIELD (long,4,UEXC_,a3)
/hal_espressif-latest/components/esp_system/port/soc/esp32/
Dhighint_hdl.S76 movi a3, TIMG_WDT_WKEY_VALUE
77 s32i a3, a2, TIMG1_WDTWPROTECT_OFFSET /* disable write protect */
81 movi a3, 4
82 or a3, a4, a3
83 s32i a3, a2, TIMG1_INT_CLR_OFFSET /* clear 1st stage timeout interrupt */
85 movi a3, 0
86 s32i a3, a2, TIMG1_WDTWPROTECT_OFFSET /* enable write protect */
92 movi a3, TIMG_WDT_WKEY_VALUE
93 s32i a3, a2, TIMG1_WDTWPROTECT_OFFSET /* disable write protect */
99 movi a3, (CONFIG_ESP_INT_WDT_TIMEOUT_MS<<1)
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/hal_espressif-latest/components/xtensa/
Dxtensa_intr_asm.S162 movi a3, 0
164 xsr a3, INTENABLE /* Disables all interrupts */
166 l32i a3, a4, 0 /* a3 = _xt_intenable */
168 or a5, a3, a2 /* a5 = _xt_intenable | mask */
172 mov a2, a3 /* Previous mask */
174 movi a3, 0
175 xsr a3, INTENABLE /* Disables all interrupts */
177 or a2, a3, a2 /* set bits in mask */
180 mov a2, a3 /* return prev mask */
211 movi a3, 0
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/hal_espressif-latest/components/esp_system/port/arch/xtensa/
Desp_ipc_isr_handler.S56 s32i a3, a0, LX_INTR_A3_OFFSET
77 movi a3, (1 << ETS_IPC_ISR_INUM)
78 wsr a3, INTCLEAR
82 getcoreid a3
83 beqz a3, 1f
86 movi a3, SYSTEM_CPU_INTR_FROM_CPU_3_REG
88 s32i a4, a3, 0 /* clear intr */
92 movi a3, SYSTEM_CPU_INTR_FROM_CPU_2_REG
94 s32i a4, a3, 0 /* clear intr */
112 l32i a3, a0, LX_INTR_A3_OFFSET
Desp_ipc_isr_routines.S27 l32i a3, a2, 0
28 beqz a3, .check_finish_cmd
Ddebug_helpers_asm.S54 s32i a5, a3, 0 //Store i SP to arg *sp
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_cache_writeback_esp32s3.S81 s32i a3, a4, 0
85 movi a3, EXTMEM_DCACHE_SYNC_CTRL_REG
106 l32i a4, a3, 0 /* a4 = *(EXTMEM_DCACHE_SYNC_CTRL_REG) */
109 s32i a4, a3, 0 /* *(EXTMEM_DCACHE_SYNC_CTRL_REG) = a4 */
114 l32i a4, a3, 0 /* a4 = *(EXTMEM_DCACHE_SYNC_CTRL_REG) */
Desp_rom_longjmp.S144 movnez a2, a3, a3
/hal_espressif-latest/components/xtensa/esp32/include/xtensa/config/
Dcore.h1011 #define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6
1012 #define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6
1015 #define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6
1016 #define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6
1017 #define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6
1018 #define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6
1019 #define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6
1020 #define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6
1021 #define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6
1022 #define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6
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/hal_espressif-latest/components/xtensa/esp32s2/include/xtensa/config/
Dcore.h1065 #define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6
1066 #define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6
1069 #define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6
1070 #define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6
1071 #define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6
1072 #define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6
1073 #define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6
1074 #define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6
1075 #define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6
1076 #define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6
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/hal_espressif-latest/components/xtensa/esp32s3/include/xtensa/config/
Dcore.h1071 #define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6
1072 #define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6
1075 #define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6
1076 #define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6
1077 #define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6
1078 #define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6
1079 #define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6
1080 #define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6
1081 #define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6
1082 #define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6
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/hal_espressif-latest/components/wpa_supplicant/src/crypto/
Dccmp.c82 const u8 *a3, const u8 *pn, in ccmp_aad_nonce_pv1() argument
121 if (a3) { in ccmp_aad_nonce_pv1()
122 os_memcpy(pos, a3, ETH_ALEN); in ccmp_aad_nonce_pv1()
240 u8 * ccmp_encrypt_pv1(const u8 *tk, const u8 *a1, const u8 *a2, const u8 *a3, in ccmp_encrypt_pv1() argument
264 ccmp_aad_nonce_pv1(crypt, a1, a2, a3, pn, aad, &aad_len, nonce); in ccmp_encrypt_pv1()
Dccmp.h17 u8 * ccmp_encrypt_pv1(const u8 *tk, const u8 *a1, const u8 *a2, const u8 *a3,
/hal_espressif-latest/components/esp_hw_support/
Dsleep_cpu_asm.S65 sw a3, RV_SLP_CTX_A3(t0)
230 lw a3, RV_SLP_CTX_A3(t0)
/hal_espressif-latest/components/riscv/
Dvectors.S35 sw a3, RV_STK_A3(sp)
75 lw a3, RV_STK_A3(sp)
/hal_espressif-latest/components/riscv/include/riscv/
Drvruntime-frames.h59 STRUCT_FIELD (long, 4, RV_STK_A3, a3)
Drvsleep-frames.h61 STRUCT_FIELD (long, 4, RV_SLP_CTX_A3, a3)
/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/
Dburn-key-digest-cmd.rst170 …= a3 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d …