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Searched refs:_DPORT_REG_READ (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-latest/components/soc/esp32c6/include/soc/
Ddport_access.h33 #define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) macro
39 #define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
40 #define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
81 #define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
82 #define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Ddport_access.h30 #define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) macro
36 #define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
37 #define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
78 #define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
79 #define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Ddport_access.h32 #define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) macro
38 #define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
39 #define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
80 #define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
81 #define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Ddport_access.h33 #define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) macro
39 #define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
40 #define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
81 #define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
82 #define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Ddport_access.h33 #define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) macro
39 #define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
40 #define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
81 #define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
82 #define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Ddport_access.h31 #define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) macro
37 #define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
38 #define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
79 #define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
80 #define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
/hal_espressif-latest/components/soc/esp32/include/soc/
Ddport_access.h47 #define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) macro
113 #define DPORT_REG_READ(reg) _DPORT_REG_READ(reg)
114 #define DPORT_SEQUENCE_REG_READ(reg) _DPORT_REG_READ(reg)
172 #define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
173 #define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
/hal_espressif-latest/components/soc/esp32/
Ddport_access.c16 return _DPORT_REG_READ(reg); in esp_dport_access_reg_read()
38 return _DPORT_REG_READ(reg); in esp_dport_access_sequence_reg_read()
/hal_espressif-latest/components/bootloader_support/src/esp32/
Dbootloader_sha.c47 while (_DPORT_REG_READ(SHA_256_BUSY_REG) != 0) { } in bootloader_sha256_data()
106 while (_DPORT_REG_READ(SHA_256_BUSY_REG) == 1) { } in bootloader_sha256_finish()
108 while (_DPORT_REG_READ(SHA_256_BUSY_REG) == 1) { } in bootloader_sha256_finish()
/hal_espressif-latest/components/esp_hw_support/
Dsleep_modes.c370 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR); in esp_default_wake_deep_sleep()
372 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR)); in esp_default_wake_deep_sleep()