Searched refs:XTENSA_DBREGN_SREG (Results 1 – 1 of 1) sorted by relevance
82 #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) /* special registers 0..255 (core) */ macro83 #define XTENSA_DBREGN_BR XTENSA_DBREGN_SREG(0x04) /* all 16 boolean bits, BR */84 #define XTENSA_DBREGN_MR(n) XTENSA_DBREGN_SREG(0x20+(n)) /* MAC16 registers m0..m3 */123 #define XTENSA_DBREGN_IS_BR(tn) (((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04)) /* is BR */124 #define XTENSA_DBREGN_IS_MR(tn) (((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20)) /* m0..m3 */
