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Searched refs:SYSCON_SARADC_SAR_CLK_DIV (Results 1 – 3 of 3) sorted by relevance

/hal_espressif-latest/zephyr/esp32/src/
Dsoc_random.c52 SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, in soc_random_enable()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32.c62 …SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_… in bootloader_random_enable()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dsyscon_reg.h115 #define SYSCON_SARADC_SAR_CLK_DIV 0x000000FF macro