1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef _SOC_SYSCON_REG_H_
15 #define _SOC_SYSCON_REG_H_
16 
17 #include "soc.h"
18 #define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
19 /* SYSCON_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
20 /*description: */
21 #define SYSCON_QUICK_CLK_CHNG  (BIT(13))
22 #define SYSCON_QUICK_CLK_CHNG_M  (BIT(13))
23 #define SYSCON_QUICK_CLK_CHNG_V  0x1
24 #define SYSCON_QUICK_CLK_CHNG_S  13
25 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
26 /*description: */
27 #define SYSCON_RST_TICK_CNT  (BIT(12))
28 #define SYSCON_RST_TICK_CNT_M  (BIT(12))
29 #define SYSCON_RST_TICK_CNT_V  0x1
30 #define SYSCON_RST_TICK_CNT_S  12
31 /* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
32 /*description: */
33 #define SYSCON_CLK_EN  (BIT(11))
34 #define SYSCON_CLK_EN_M  (BIT(11))
35 #define SYSCON_CLK_EN_V  0x1
36 #define SYSCON_CLK_EN_S  11
37 /* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
38 /*description: */
39 #define SYSCON_CLK_320M_EN  (BIT(10))
40 #define SYSCON_CLK_320M_EN_M  (BIT(10))
41 #define SYSCON_CLK_320M_EN_V  0x1
42 #define SYSCON_CLK_320M_EN_S  10
43 /* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
44 /*description: */
45 #define SYSCON_PRE_DIV_CNT  0x000003FF
46 #define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
47 #define SYSCON_PRE_DIV_CNT_V  0x3FF
48 #define SYSCON_PRE_DIV_CNT_S  0
49 
50 #define SYSCON_XTAL_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
51 /* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
52 /*description: */
53 #define SYSCON_XTAL_TICK_NUM  0x000000FF
54 #define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
55 #define SYSCON_XTAL_TICK_NUM_V  0xFF
56 #define SYSCON_XTAL_TICK_NUM_S  0
57 
58 #define SYSCON_PLL_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x8)
59 /* SYSCON_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */
60 /*description: */
61 #define SYSCON_PLL_TICK_NUM  0x000000FF
62 #define SYSCON_PLL_TICK_NUM_M  ((SYSCON_PLL_TICK_NUM_V)<<(SYSCON_PLL_TICK_NUM_S))
63 #define SYSCON_PLL_TICK_NUM_V  0xFF
64 #define SYSCON_PLL_TICK_NUM_S  0
65 
66 #define SYSCON_CK8M_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0xC)
67 /* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */
68 /*description: */
69 #define SYSCON_CK8M_TICK_NUM  0x000000FF
70 #define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
71 #define SYSCON_CK8M_TICK_NUM_V  0xFF
72 #define SYSCON_CK8M_TICK_NUM_S  0
73 
74 #define SYSCON_SARADC_CTRL_REG          (DR_REG_SYSCON_BASE + 0x10)
75 /* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
76 /*description: 1: I2S input data is from SAR ADC (for DMA)  0: I2S input data
77  is from GPIO matrix*/
78 #define SYSCON_SARADC_DATA_TO_I2S  (BIT(26))
79 #define SYSCON_SARADC_DATA_TO_I2S_M  (BIT(26))
80 #define SYSCON_SARADC_DATA_TO_I2S_V  0x1
81 #define SYSCON_SARADC_DATA_TO_I2S_S  26
82 /* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
83 /*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
84   in this case the resolution should not be larger than 11 bits.*/
85 #define SYSCON_SARADC_DATA_SAR_SEL  (BIT(25))
86 #define SYSCON_SARADC_DATA_SAR_SEL_M  (BIT(25))
87 #define SYSCON_SARADC_DATA_SAR_SEL_V  0x1
88 #define SYSCON_SARADC_DATA_SAR_SEL_S  25
89 /* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
90 /*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
91 #define SYSCON_SARADC_SAR2_PATT_P_CLEAR  (BIT(24))
92 #define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
93 #define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V  0x1
94 #define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S  24
95 /* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
96 /*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
97 #define SYSCON_SARADC_SAR1_PATT_P_CLEAR  (BIT(23))
98 #define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
99 #define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V  0x1
100 #define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S  23
101 /* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
102 /*description: 0 ~ 15 means length 1 ~ 16*/
103 #define SYSCON_SARADC_SAR2_PATT_LEN  0x0000000F
104 #define SYSCON_SARADC_SAR2_PATT_LEN_M  ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S))
105 #define SYSCON_SARADC_SAR2_PATT_LEN_V  0xF
106 #define SYSCON_SARADC_SAR2_PATT_LEN_S  19
107 /* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
108 /*description: 0 ~ 15 means length 1 ~ 16*/
109 #define SYSCON_SARADC_SAR1_PATT_LEN  0x0000000F
110 #define SYSCON_SARADC_SAR1_PATT_LEN_M  ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S))
111 #define SYSCON_SARADC_SAR1_PATT_LEN_V  0xF
112 #define SYSCON_SARADC_SAR1_PATT_LEN_S  15
113 /* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
114 /*description: SAR clock divider*/
115 #define SYSCON_SARADC_SAR_CLK_DIV  0x000000FF
116 #define SYSCON_SARADC_SAR_CLK_DIV_M  ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S))
117 #define SYSCON_SARADC_SAR_CLK_DIV_V  0xFF
118 #define SYSCON_SARADC_SAR_CLK_DIV_S  7
119 /* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
120 /*description: */
121 #define SYSCON_SARADC_SAR_CLK_GATED  (BIT(6))
122 #define SYSCON_SARADC_SAR_CLK_GATED_M  (BIT(6))
123 #define SYSCON_SARADC_SAR_CLK_GATED_V  0x1
124 #define SYSCON_SARADC_SAR_CLK_GATED_S  6
125 /* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
126 /*description: 0: SAR1  1: SAR2  only work for single SAR mode*/
127 #define SYSCON_SARADC_SAR_SEL  (BIT(5))
128 #define SYSCON_SARADC_SAR_SEL_M  (BIT(5))
129 #define SYSCON_SARADC_SAR_SEL_V  0x1
130 #define SYSCON_SARADC_SAR_SEL_S  5
131 /* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
132 /*description: 0: single mode  1: double mode  2: alternate mode*/
133 #define SYSCON_SARADC_WORK_MODE  0x00000003
134 #define SYSCON_SARADC_WORK_MODE_M  ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S))
135 #define SYSCON_SARADC_WORK_MODE_V  0x3
136 #define SYSCON_SARADC_WORK_MODE_S  3
137 /* SYSCON_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */
138 /*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled
139  by PWDET CTRL*/
140 #define SYSCON_SARADC_SAR2_MUX  (BIT(2))
141 #define SYSCON_SARADC_SAR2_MUX_M  (BIT(2))
142 #define SYSCON_SARADC_SAR2_MUX_V  0x1
143 #define SYSCON_SARADC_SAR2_MUX_S  2
144 /* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
145 /*description: */
146 #define SYSCON_SARADC_START  (BIT(1))
147 #define SYSCON_SARADC_START_M  (BIT(1))
148 #define SYSCON_SARADC_START_V  0x1
149 #define SYSCON_SARADC_START_S  1
150 /* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
151 /*description: */
152 #define SYSCON_SARADC_START_FORCE  (BIT(0))
153 #define SYSCON_SARADC_START_FORCE_M  (BIT(0))
154 #define SYSCON_SARADC_START_FORCE_V  0x1
155 #define SYSCON_SARADC_START_FORCE_S  0
156 
157 #define SYSCON_SARADC_CTRL2_REG          (DR_REG_SYSCON_BASE + 0x14)
158 /* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
159 /*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
160 #define SYSCON_SARADC_SAR2_INV  (BIT(10))
161 #define SYSCON_SARADC_SAR2_INV_M  (BIT(10))
162 #define SYSCON_SARADC_SAR2_INV_V  0x1
163 #define SYSCON_SARADC_SAR2_INV_S  10
164 /* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
165 /*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
166 #define SYSCON_SARADC_SAR1_INV  (BIT(9))
167 #define SYSCON_SARADC_SAR1_INV_M  (BIT(9))
168 #define SYSCON_SARADC_SAR1_INV_V  0x1
169 #define SYSCON_SARADC_SAR1_INV_S  9
170 /* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
171 /*description: max conversion number*/
172 #define SYSCON_SARADC_MAX_MEAS_NUM  0x000000FF
173 #define SYSCON_SARADC_MAX_MEAS_NUM_M  ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S))
174 #define SYSCON_SARADC_MAX_MEAS_NUM_V  0xFF
175 #define SYSCON_SARADC_MAX_MEAS_NUM_S  1
176 /* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
177 /*description: */
178 #define SYSCON_SARADC_MEAS_NUM_LIMIT  (BIT(0))
179 #define SYSCON_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
180 #define SYSCON_SARADC_MEAS_NUM_LIMIT_V  0x1
181 #define SYSCON_SARADC_MEAS_NUM_LIMIT_S  0
182 
183 #define SYSCON_SARADC_FSM_REG          (DR_REG_SYSCON_BASE + 0x18)
184 /* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
185 /*description: sample cycles*/
186 #define SYSCON_SARADC_SAMPLE_CYCLE  0x000000FF
187 #define SYSCON_SARADC_SAMPLE_CYCLE_M  ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S))
188 #define SYSCON_SARADC_SAMPLE_CYCLE_V  0xFF
189 #define SYSCON_SARADC_SAMPLE_CYCLE_S  24
190 /* SYSCON_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */
191 /*description: */
192 #define SYSCON_SARADC_START_WAIT  0x000000FF
193 #define SYSCON_SARADC_START_WAIT_M  ((SYSCON_SARADC_START_WAIT_V)<<(SYSCON_SARADC_START_WAIT_S))
194 #define SYSCON_SARADC_START_WAIT_V  0xFF
195 #define SYSCON_SARADC_START_WAIT_S  16
196 /* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */
197 /*description: */
198 #define SYSCON_SARADC_STANDBY_WAIT  0x000000FF
199 #define SYSCON_SARADC_STANDBY_WAIT_M  ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S))
200 #define SYSCON_SARADC_STANDBY_WAIT_V  0xFF
201 #define SYSCON_SARADC_STANDBY_WAIT_S  8
202 /* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
203 /*description: */
204 #define SYSCON_SARADC_RSTB_WAIT  0x000000FF
205 #define SYSCON_SARADC_RSTB_WAIT_M  ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S))
206 #define SYSCON_SARADC_RSTB_WAIT_V  0xFF
207 #define SYSCON_SARADC_RSTB_WAIT_S  0
208 
209 #define SYSCON_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_SYSCON_BASE + 0x1C)
210 /* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
211 /*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
212 #define SYSCON_SARADC_SAR1_PATT_TAB1  0xFFFFFFFF
213 #define SYSCON_SARADC_SAR1_PATT_TAB1_M  ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S))
214 #define SYSCON_SARADC_SAR1_PATT_TAB1_V  0xFFFFFFFF
215 #define SYSCON_SARADC_SAR1_PATT_TAB1_S  0
216 
217 #define SYSCON_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_SYSCON_BASE + 0x20)
218 /* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
219 /*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
220 #define SYSCON_SARADC_SAR1_PATT_TAB2  0xFFFFFFFF
221 #define SYSCON_SARADC_SAR1_PATT_TAB2_M  ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S))
222 #define SYSCON_SARADC_SAR1_PATT_TAB2_V  0xFFFFFFFF
223 #define SYSCON_SARADC_SAR1_PATT_TAB2_S  0
224 
225 #define SYSCON_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_SYSCON_BASE + 0x24)
226 /* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
227 /*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
228 #define SYSCON_SARADC_SAR1_PATT_TAB3  0xFFFFFFFF
229 #define SYSCON_SARADC_SAR1_PATT_TAB3_M  ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S))
230 #define SYSCON_SARADC_SAR1_PATT_TAB3_V  0xFFFFFFFF
231 #define SYSCON_SARADC_SAR1_PATT_TAB3_S  0
232 
233 #define SYSCON_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_SYSCON_BASE + 0x28)
234 /* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
235 /*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
236 #define SYSCON_SARADC_SAR1_PATT_TAB4  0xFFFFFFFF
237 #define SYSCON_SARADC_SAR1_PATT_TAB4_M  ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S))
238 #define SYSCON_SARADC_SAR1_PATT_TAB4_V  0xFFFFFFFF
239 #define SYSCON_SARADC_SAR1_PATT_TAB4_S  0
240 
241 #define SYSCON_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_SYSCON_BASE + 0x2C)
242 /* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
243 /*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
244 #define SYSCON_SARADC_SAR2_PATT_TAB1  0xFFFFFFFF
245 #define SYSCON_SARADC_SAR2_PATT_TAB1_M  ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S))
246 #define SYSCON_SARADC_SAR2_PATT_TAB1_V  0xFFFFFFFF
247 #define SYSCON_SARADC_SAR2_PATT_TAB1_S  0
248 
249 #define SYSCON_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_SYSCON_BASE + 0x30)
250 /* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
251 /*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
252 #define SYSCON_SARADC_SAR2_PATT_TAB2  0xFFFFFFFF
253 #define SYSCON_SARADC_SAR2_PATT_TAB2_M  ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S))
254 #define SYSCON_SARADC_SAR2_PATT_TAB2_V  0xFFFFFFFF
255 #define SYSCON_SARADC_SAR2_PATT_TAB2_S  0
256 
257 #define SYSCON_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_SYSCON_BASE + 0x34)
258 /* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
259 /*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
260 #define SYSCON_SARADC_SAR2_PATT_TAB3  0xFFFFFFFF
261 #define SYSCON_SARADC_SAR2_PATT_TAB3_M  ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S))
262 #define SYSCON_SARADC_SAR2_PATT_TAB3_V  0xFFFFFFFF
263 #define SYSCON_SARADC_SAR2_PATT_TAB3_S  0
264 
265 #define SYSCON_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_SYSCON_BASE + 0x38)
266 /* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
267 /*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
268 #define SYSCON_SARADC_SAR2_PATT_TAB4  0xFFFFFFFF
269 #define SYSCON_SARADC_SAR2_PATT_TAB4_M  ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S))
270 #define SYSCON_SARADC_SAR2_PATT_TAB4_V  0xFFFFFFFF
271 #define SYSCON_SARADC_SAR2_PATT_TAB4_S  0
272 
273 #define SYSCON_APLL_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x3C)
274 /* SYSCON_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */
275 /*description: */
276 #define SYSCON_APLL_TICK_NUM  0x000000FF
277 #define SYSCON_APLL_TICK_NUM_M  ((SYSCON_APLL_TICK_NUM_V)<<(SYSCON_APLL_TICK_NUM_S))
278 #define SYSCON_APLL_TICK_NUM_V  0xFF
279 #define SYSCON_APLL_TICK_NUM_S  0
280 
281 #define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x7C)
282 /* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
283 /*description: */
284 #define SYSCON_DATE  0xFFFFFFFF
285 #define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
286 #define SYSCON_DATE_V  0xFFFFFFFF
287 #define SYSCON_DATE_S  0
288 
289 
290 
291 
292 #endif /*_SOC_SYSCON_REG_H_ */
293