Searched refs:SYSCON_SARADC_CTRL_REG (Results 1 – 3 of 3) sorted by relevance
| /hal_espressif-latest/zephyr/esp32/src/ |
| D | soc_random.c | 51 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX); in soc_random_enable()
52 SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, in soc_random_enable()
58 SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, in soc_random_enable()
60 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL); in soc_random_enable()
61 CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL); in soc_random_enable()
64 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S); in soc_random_enable()
95 CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX | SYSCON_SARADC_SAR_SEL | in soc_random_disable()
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| /hal_espressif-latest/components/bootloader_support/src/ |
| D | bootloader_random_esp32.c | 61 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX); in bootloader_random_enable()
62 …SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_… in bootloader_random_enable()
65 … SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S); in bootloader_random_enable()
66 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL); in bootloader_random_enable()
67 CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL); in bootloader_random_enable()
69 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S); in bootloader_random_enable()
103 CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX in bootloader_random_disable()
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| /hal_espressif-latest/components/soc/esp32/include/soc/ |
| D | syscon_reg.h | 74 #define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x10) macro
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