1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef _SOC_SPI_MEM_REG_H_
15 #define _SOC_SPI_MEM_REG_H_
16 
17 
18 #include "soc.h"
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 #define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
24 /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
25 /*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
26 he bit will be cleared once the operation done. 1: enable 0: disable. .*/
27 #define SPI_MEM_FLASH_READ    (BIT(31))
28 #define SPI_MEM_FLASH_READ_M  (BIT(31))
29 #define SPI_MEM_FLASH_READ_V  0x1
30 #define SPI_MEM_FLASH_READ_S  31
31 /* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
32 /*description: Write flash enable.  Write enable command will be sent when the bit is set. The
33 bit will be cleared once the operation done. 1: enable 0: disable. .*/
34 #define SPI_MEM_FLASH_WREN    (BIT(30))
35 #define SPI_MEM_FLASH_WREN_M  (BIT(30))
36 #define SPI_MEM_FLASH_WREN_V  0x1
37 #define SPI_MEM_FLASH_WREN_S  30
38 /* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
39 /*description: Write flash disable. Write disable command will be sent when the bit is set. The
40  bit will be cleared once the operation done. 1: enable 0: disable. .*/
41 #define SPI_MEM_FLASH_WRDI    (BIT(29))
42 #define SPI_MEM_FLASH_WRDI_M  (BIT(29))
43 #define SPI_MEM_FLASH_WRDI_V  0x1
44 #define SPI_MEM_FLASH_WRDI_S  29
45 /* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
46 /*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
47 e cleared once the operation done. 1: enable 0: disable. .*/
48 #define SPI_MEM_FLASH_RDID    (BIT(28))
49 #define SPI_MEM_FLASH_RDID_M  (BIT(28))
50 #define SPI_MEM_FLASH_RDID_V  0x1
51 #define SPI_MEM_FLASH_RDID_S  28
52 /* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
53 /*description: Read status register-1.  Read status operation will be triggered when the bit is
54  set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
55 #define SPI_MEM_FLASH_RDSR    (BIT(27))
56 #define SPI_MEM_FLASH_RDSR_M  (BIT(27))
57 #define SPI_MEM_FLASH_RDSR_V  0x1
58 #define SPI_MEM_FLASH_RDSR_S  27
59 /* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
60 /*description: Write status register enable.   Write status operation  will be triggered when t
61 he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
62 ble. .*/
63 #define SPI_MEM_FLASH_WRSR    (BIT(26))
64 #define SPI_MEM_FLASH_WRSR_M  (BIT(26))
65 #define SPI_MEM_FLASH_WRSR_V  0x1
66 #define SPI_MEM_FLASH_WRSR_S  26
67 /* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
68 /*description: Page program enable(1 byte ~64 bytes data to be programmed). Page program operat
69 ion  will be triggered when the bit is set. The bit will be cleared once the ope
70 ration done .1: enable 0: disable. .*/
71 #define SPI_MEM_FLASH_PP    (BIT(25))
72 #define SPI_MEM_FLASH_PP_M  (BIT(25))
73 #define SPI_MEM_FLASH_PP_V  0x1
74 #define SPI_MEM_FLASH_PP_S  25
75 /* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
76 /*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
77 is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
78 #define SPI_MEM_FLASH_SE    (BIT(24))
79 #define SPI_MEM_FLASH_SE_M  (BIT(24))
80 #define SPI_MEM_FLASH_SE_V  0x1
81 #define SPI_MEM_FLASH_SE_S  24
82 /* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
83 /*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
84  is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
85 #define SPI_MEM_FLASH_BE    (BIT(23))
86 #define SPI_MEM_FLASH_BE_M  (BIT(23))
87 #define SPI_MEM_FLASH_BE_V  0x1
88 #define SPI_MEM_FLASH_BE_S  23
89 /* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
90 /*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
91 he bit will be cleared once the operation done.1: enable 0: disable. .*/
92 #define SPI_MEM_FLASH_CE    (BIT(22))
93 #define SPI_MEM_FLASH_CE_M  (BIT(22))
94 #define SPI_MEM_FLASH_CE_V  0x1
95 #define SPI_MEM_FLASH_CE_S  22
96 /* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
97 /*description: Drive Flash into power down.  An operation will be triggered when the bit is set
98 . The bit will be cleared once the operation done.1: enable 0: disable. .*/
99 #define SPI_MEM_FLASH_DP    (BIT(21))
100 #define SPI_MEM_FLASH_DP_M  (BIT(21))
101 #define SPI_MEM_FLASH_DP_V  0x1
102 #define SPI_MEM_FLASH_DP_S  21
103 /* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
104 /*description: This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down
105 state or high performance mode and obtains the devices ID. The bit will be clear
106 ed once the operation done.1: enable 0: disable. .*/
107 #define SPI_MEM_FLASH_RES    (BIT(20))
108 #define SPI_MEM_FLASH_RES_M  (BIT(20))
109 #define SPI_MEM_FLASH_RES_V  0x1
110 #define SPI_MEM_FLASH_RES_S  20
111 /* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
112 /*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
113 ion done.1: enable 0: disable. .*/
114 #define SPI_MEM_FLASH_HPM    (BIT(19))
115 #define SPI_MEM_FLASH_HPM_M  (BIT(19))
116 #define SPI_MEM_FLASH_HPM_V  0x1
117 #define SPI_MEM_FLASH_HPM_S  19
118 /* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
119 /*description: User define command enable.  An operation will be triggered when the bit is set.
120  The bit will be cleared once the operation done.1: enable 0: disable. .*/
121 #define SPI_MEM_USR    (BIT(18))
122 #define SPI_MEM_USR_M  (BIT(18))
123 #define SPI_MEM_USR_V  0x1
124 #define SPI_MEM_USR_S  18
125 /* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
126 /*description: In user mode, it is set to indicate that program/erase operation will be trigger
127 ed. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the o
128 peration done.1: enable 0: disable. .*/
129 #define SPI_MEM_FLASH_PE    (BIT(17))
130 #define SPI_MEM_FLASH_PE_M  (BIT(17))
131 #define SPI_MEM_FLASH_PE_V  0x1
132 #define SPI_MEM_FLASH_PE_S  17
133 
134 #define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
135 /* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
136 /*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
137 address, the bit24-bit31 are the byte length of a transfer..*/
138 #define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
139 #define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
140 #define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
141 #define SPI_MEM_USR_ADDR_VALUE_S  0
142 
143 #define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
144 /* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
145 /*description: In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-
146 mode). 1: enable 0: disable. .*/
147 #define SPI_MEM_FREAD_QIO    (BIT(24))
148 #define SPI_MEM_FREAD_QIO_M  (BIT(24))
149 #define SPI_MEM_FREAD_QIO_V  0x1
150 #define SPI_MEM_FREAD_QIO_S  24
151 /* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
152 /*description: In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-
153 mode). 1: enable 0: disable. .*/
154 #define SPI_MEM_FREAD_DIO    (BIT(23))
155 #define SPI_MEM_FREAD_DIO_M  (BIT(23))
156 #define SPI_MEM_FREAD_DIO_V  0x1
157 #define SPI_MEM_FREAD_DIO_S  23
158 /* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
159 /*description: Two bytes data will be written to status register when it is set. 1: enable 0: d
160 isable. .*/
161 #define SPI_MEM_WRSR_2B    (BIT(22))
162 #define SPI_MEM_WRSR_2B_M  (BIT(22))
163 #define SPI_MEM_WRSR_2B_V  0x1
164 #define SPI_MEM_WRSR_2B_S  22
165 /* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
166 /*description: Write protect signal output when SPI is idle.  1: output high, 0: output low. .*/
167 #define SPI_MEM_WP_REG    (BIT(21))
168 #define SPI_MEM_WP_REG_M  (BIT(21))
169 #define SPI_MEM_WP_REG_V  0x1
170 #define SPI_MEM_WP_REG_S  21
171 /* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
172 /*description: In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enabl
173 e 0: disable. .*/
174 #define SPI_MEM_FREAD_QUAD    (BIT(20))
175 #define SPI_MEM_FREAD_QUAD_M  (BIT(20))
176 #define SPI_MEM_FREAD_QUAD_V  0x1
177 #define SPI_MEM_FREAD_QUAD_S  20
178 /* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
179 /*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
180 #define SPI_MEM_D_POL    (BIT(19))
181 #define SPI_MEM_D_POL_M  (BIT(19))
182 #define SPI_MEM_D_POL_V  0x1
183 #define SPI_MEM_D_POL_S  19
184 /* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
185 /*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
186 #define SPI_MEM_Q_POL    (BIT(18))
187 #define SPI_MEM_Q_POL_M  (BIT(18))
188 #define SPI_MEM_Q_POL_V  0x1
189 #define SPI_MEM_Q_POL_S  18
190 /* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
191 /*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
192 spi_mem_flash_res bit. 1: enable 0: disable. .*/
193 #define SPI_MEM_RESANDRES    (BIT(15))
194 #define SPI_MEM_RESANDRES_M  (BIT(15))
195 #define SPI_MEM_RESANDRES_V  0x1
196 #define SPI_MEM_RESANDRES_S  15
197 /* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
198 /*description: In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable
199 . .*/
200 #define SPI_MEM_FREAD_DUAL    (BIT(14))
201 #define SPI_MEM_FREAD_DUAL_M  (BIT(14))
202 #define SPI_MEM_FREAD_DUAL_V  0x1
203 #define SPI_MEM_FREAD_DUAL_S  14
204 /* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
205 /*description: This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_
206 QUAD or SPI_MEM_FREAD_DUAL is set..*/
207 #define SPI_MEM_FASTRD_MODE    (BIT(13))
208 #define SPI_MEM_FASTRD_MODE_M  (BIT(13))
209 #define SPI_MEM_FASTRD_MODE_V  0x1
210 #define SPI_MEM_FASTRD_MODE_S  13
211 /* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
212 /*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
213 e.*/
214 #define SPI_MEM_TX_CRC_EN    (BIT(11))
215 #define SPI_MEM_TX_CRC_EN_M  (BIT(11))
216 #define SPI_MEM_TX_CRC_EN_V  0x1
217 #define SPI_MEM_TX_CRC_EN_S  11
218 /* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
219 /*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
220 e low..*/
221 #define SPI_MEM_FCS_CRC_EN    (BIT(10))
222 #define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
223 #define SPI_MEM_FCS_CRC_EN_V  0x1
224 #define SPI_MEM_FCS_CRC_EN_S  10
225 /* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */
226 /*description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase..*/
227 #define SPI_MEM_FCMD_OCT    (BIT(9))
228 #define SPI_MEM_FCMD_OCT_M  (BIT(9))
229 #define SPI_MEM_FCMD_OCT_V  0x1
230 #define SPI_MEM_FCMD_OCT_S  9
231 /* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
232 /*description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase..*/
233 #define SPI_MEM_FCMD_QUAD    (BIT(8))
234 #define SPI_MEM_FCMD_QUAD_M  (BIT(8))
235 #define SPI_MEM_FCMD_QUAD_V  0x1
236 #define SPI_MEM_FCMD_QUAD_S  8
237 /* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
238 /*description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase..*/
239 #define SPI_MEM_FCMD_DUAL    (BIT(7))
240 #define SPI_MEM_FCMD_DUAL_M  (BIT(7))
241 #define SPI_MEM_FCMD_DUAL_V  0x1
242 #define SPI_MEM_FCMD_DUAL_S  7
243 /* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
244 /*description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase..*/
245 #define SPI_MEM_FADDR_OCT    (BIT(6))
246 #define SPI_MEM_FADDR_OCT_M  (BIT(6))
247 #define SPI_MEM_FADDR_OCT_V  0x1
248 #define SPI_MEM_FADDR_OCT_S  6
249 /* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
250 /*description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase..*/
251 #define SPI_MEM_FDIN_OCT    (BIT(5))
252 #define SPI_MEM_FDIN_OCT_M  (BIT(5))
253 #define SPI_MEM_FDIN_OCT_V  0x1
254 #define SPI_MEM_FDIN_OCT_S  5
255 /* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */
256 /*description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase..*/
257 #define SPI_MEM_FDOUT_OCT    (BIT(4))
258 #define SPI_MEM_FDOUT_OCT_M  (BIT(4))
259 #define SPI_MEM_FDOUT_OCT_V  0x1
260 #define SPI_MEM_FDOUT_OCT_S  4
261 /* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
262 /*description: In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller..*/
263 #define SPI_MEM_FDUMMY_OUT    (BIT(3))
264 #define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
265 #define SPI_MEM_FDUMMY_OUT_V  0x1
266 #define SPI_MEM_FDUMMY_OUT_S  3
267 
268 #define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
269 /* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
270 /*description: SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts
271 ..*/
272 #define SPI_MEM_RXFIFO_RST    (BIT(30))
273 #define SPI_MEM_RXFIFO_RST_M  (BIT(30))
274 #define SPI_MEM_RXFIFO_RST_V  0x1
275 #define SPI_MEM_RXFIFO_RST_S  30
276 /* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
277 /*description: After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_
278 RES[9:0] * 4 or * 256) SPI_CLK cycles..*/
279 #define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
280 #define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
281 #define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
282 #define SPI_MEM_CS_HOLD_DLY_RES_S  2
283 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
284 /*description: SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS ina
285 ctive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delaye
286 d two cycles after SPI_CS inactive 3: SPI_CLK is always on..*/
287 #define SPI_MEM_CLK_MODE    0x00000003
288 #define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
289 #define SPI_MEM_CLK_MODE_V  0x3
290 #define SPI_MEM_CLK_MODE_S  0
291 
292 #define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
293 /* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
294 /*description: The FSM will be reset..*/
295 #define SPI_MEM_SYNC_RESET    (BIT(31))
296 #define SPI_MEM_SYNC_RESET_M  (BIT(31))
297 #define SPI_MEM_SYNC_RESET_V  0x1
298 #define SPI_MEM_SYNC_RESET_S  31
299 /* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
300 /*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
301 sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
302  clock cycles..*/
303 #define SPI_MEM_CS_HOLD_DELAY    0x0000003F
304 #define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
305 #define SPI_MEM_CS_HOLD_DELAY_V  0x3F
306 #define SPI_MEM_CS_HOLD_DELAY_S  25
307 /* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
308 /*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse
309 s flash..*/
310 #define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
311 #define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
312 #define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
313 #define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
314 /* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
315 /*description: 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when acce
316 sses flash..*/
317 #define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
318 #define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
319 #define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
320 #define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
321 /* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
322 /*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC
323 mode when accessed flash..*/
324 #define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
325 #define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
326 #define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
327 #define SPI_MEM_ECC_CS_HOLD_TIME_S  10
328 /* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
329 /*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh
330 ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME
331 M_CS_HOLD bit..*/
332 #define SPI_MEM_CS_HOLD_TIME    0x0000001F
333 #define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
334 #define SPI_MEM_CS_HOLD_TIME_V  0x1F
335 #define SPI_MEM_CS_HOLD_TIME_S  5
336 /* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
337 /*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits
338 are combined with SPI_MEM_CS_SETUP bit..*/
339 #define SPI_MEM_CS_SETUP_TIME    0x0000001F
340 #define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
341 #define SPI_MEM_CS_SETUP_TIME_V  0x1F
342 #define SPI_MEM_CS_SETUP_TIME_S  0
343 
344 #define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
345 /* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
346 /*description: When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK
347  = f_MSPI_CORE_CLK..*/
348 #define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
349 #define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
350 #define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
351 #define SPI_MEM_CLK_EQU_SYSCLK_S  31
352 /* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
353 /*description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLK
354 CNT_N+1).*/
355 #define SPI_MEM_CLKCNT_N    0x000000FF
356 #define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
357 #define SPI_MEM_CLKCNT_N_V  0xFF
358 #define SPI_MEM_CLKCNT_N_S  16
359 /* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
360 /*description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1)..*/
361 #define SPI_MEM_CLKCNT_H    0x000000FF
362 #define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
363 #define SPI_MEM_CLKCNT_H_V  0xFF
364 #define SPI_MEM_CLKCNT_H_S  8
365 /* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
366 /*description: It must equal to the value of SPI_MEM_CLKCNT_N. .*/
367 #define SPI_MEM_CLKCNT_L    0x000000FF
368 #define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
369 #define SPI_MEM_CLKCNT_L_V  0xFF
370 #define SPI_MEM_CLKCNT_L_S  0
371 
372 #define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
373 /* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
374 /*description: Set this bit to enable enable the CMD phase of an operation..*/
375 #define SPI_MEM_USR_COMMAND    (BIT(31))
376 #define SPI_MEM_USR_COMMAND_M  (BIT(31))
377 #define SPI_MEM_USR_COMMAND_V  0x1
378 #define SPI_MEM_USR_COMMAND_S  31
379 /* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
380 /*description: Set this bit to enable enable the ADDR phase of an operation..*/
381 #define SPI_MEM_USR_ADDR    (BIT(30))
382 #define SPI_MEM_USR_ADDR_M  (BIT(30))
383 #define SPI_MEM_USR_ADDR_V  0x1
384 #define SPI_MEM_USR_ADDR_S  30
385 /* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
386 /*description: Set this bit to enable enable the DUMMY phase of an operation..*/
387 #define SPI_MEM_USR_DUMMY    (BIT(29))
388 #define SPI_MEM_USR_DUMMY_M  (BIT(29))
389 #define SPI_MEM_USR_DUMMY_V  0x1
390 #define SPI_MEM_USR_DUMMY_S  29
391 /* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
392 /*description: Set this bit to enable enable the DIN phase of a read-data operation..*/
393 #define SPI_MEM_USR_MISO    (BIT(28))
394 #define SPI_MEM_USR_MISO_M  (BIT(28))
395 #define SPI_MEM_USR_MISO_V  0x1
396 #define SPI_MEM_USR_MISO_S  28
397 /* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
398 /*description: Set this bit to enable the DOUT phase of an write-data operation..*/
399 #define SPI_MEM_USR_MOSI    (BIT(27))
400 #define SPI_MEM_USR_MOSI_M  (BIT(27))
401 #define SPI_MEM_USR_MOSI_V  0x1
402 #define SPI_MEM_USR_MOSI_S  27
403 /* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
404 /*description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable..*/
405 #define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
406 #define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
407 #define SPI_MEM_USR_DUMMY_IDLE_V  0x1
408 #define SPI_MEM_USR_DUMMY_IDLE_S  26
409 /* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
410 /*description: DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG
411 . 1: enable 0: disable. .*/
412 #define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
413 #define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
414 #define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
415 #define SPI_MEM_USR_MOSI_HIGHPART_S  25
416 /* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
417 /*description: DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG.
418  1: enable 0: disable. .*/
419 #define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
420 #define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
421 #define SPI_MEM_USR_MISO_HIGHPART_V  0x1
422 #define SPI_MEM_USR_MISO_HIGHPART_S  24
423 /* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
424 /*description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write ope
425 ration..*/
426 #define SPI_MEM_FWRITE_QIO    (BIT(15))
427 #define SPI_MEM_FWRITE_QIO_M  (BIT(15))
428 #define SPI_MEM_FWRITE_QIO_V  0x1
429 #define SPI_MEM_FWRITE_QIO_S  15
430 /* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
431 /*description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation..*/
432 #define SPI_MEM_FWRITE_DIO    (BIT(14))
433 #define SPI_MEM_FWRITE_DIO_M  (BIT(14))
434 #define SPI_MEM_FWRITE_DIO_V  0x1
435 #define SPI_MEM_FWRITE_DIO_S  14
436 /* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
437 /*description: Set this bit to enable 4-bm in DOUT phase in SPI1 write operation..*/
438 #define SPI_MEM_FWRITE_QUAD    (BIT(13))
439 #define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
440 #define SPI_MEM_FWRITE_QUAD_V  0x1
441 #define SPI_MEM_FWRITE_QUAD_S  13
442 /* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
443 /*description: Set this bit to enable 2-bm in DOUT phase in SPI1 write operation..*/
444 #define SPI_MEM_FWRITE_DUAL    (BIT(12))
445 #define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
446 #define SPI_MEM_FWRITE_DUAL_V  0x1
447 #define SPI_MEM_FWRITE_DUAL_S  12
448 /* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
449 /*description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mo
450 de 0~3 of SPI_CLK. .*/
451 #define SPI_MEM_CK_OUT_EDGE    (BIT(9))
452 #define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
453 #define SPI_MEM_CK_OUT_EDGE_V  0x1
454 #define SPI_MEM_CK_OUT_EDGE_S  9
455 /* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
456 /*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
457 #define SPI_MEM_CS_SETUP    (BIT(7))
458 #define SPI_MEM_CS_SETUP_M  (BIT(7))
459 #define SPI_MEM_CS_SETUP_V  0x1
460 #define SPI_MEM_CS_SETUP_S  7
461 /* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
462 /*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/
463 #define SPI_MEM_CS_HOLD    (BIT(6))
464 #define SPI_MEM_CS_HOLD_M  (BIT(6))
465 #define SPI_MEM_CS_HOLD_V  0x1
466 #define SPI_MEM_CS_HOLD_S  6
467 
468 #define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
469 /* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
470 /*description: The length in bits of ADDR phase. The register value shall be (bit_num-1)..*/
471 #define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
472 #define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
473 #define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
474 #define SPI_MEM_USR_ADDR_BITLEN_S  26
475 /* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
476 /*description: The SPI_CLK cycle length minus 1 of DUMMY phase..*/
477 #define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
478 #define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
479 #define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
480 #define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
481 
482 #define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
483 /* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
484 /*description: The length in bits of CMD phase. The register value shall be (bit_num-1).*/
485 #define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
486 #define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
487 #define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
488 #define SPI_MEM_USR_COMMAND_BITLEN_S  28
489 /* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
490 /*description: The value of user defined(USR) command..*/
491 #define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
492 #define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
493 #define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
494 #define SPI_MEM_USR_COMMAND_VALUE_S  0
495 
496 #define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
497 /* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
498 /*description: The length in bits of DOUT phase. The register value shall be (bit_num-1)..*/
499 #define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
500 #define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
501 #define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
502 #define SPI_MEM_USR_MOSI_DBITLEN_S  0
503 
504 #define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
505 /* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
506 /*description: The length in bits of DIN phase. The register value shall be (bit_num-1)..*/
507 #define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
508 #define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
509 #define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
510 #define SPI_MEM_USR_MISO_DBITLEN_S  0
511 
512 #define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
513 /* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
514 /*description: Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE b
515 it..*/
516 #define SPI_MEM_WB_MODE    0x000000FF
517 #define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
518 #define SPI_MEM_WB_MODE_V  0xFF
519 #define SPI_MEM_WB_MODE_S  16
520 /* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
521 /*description: The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit..*/
522 #define SPI_MEM_STATUS    0x0000FFFF
523 #define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
524 #define SPI_MEM_STATUS_V  0xFFFF
525 #define SPI_MEM_STATUS_S  0
526 
527 #define SPI_MEM_EXT_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x30)
528 /* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
529 /*description: The register are the higher 32bits in the 64 bits address mode..*/
530 #define SPI_MEM_EXT_ADDR    0xFFFFFFFF
531 #define SPI_MEM_EXT_ADDR_M  ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S))
532 #define SPI_MEM_EXT_ADDR_V  0xFFFFFFFF
533 #define SPI_MEM_EXT_ADDR_S  0
534 
535 #define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
536 /* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */
537 /*description: Set this bit to enable auto PER function. Hardware will sent out PER command if
538 PES command is sent..*/
539 #define SPI_MEM_AUTO_PER    (BIT(11))
540 #define SPI_MEM_AUTO_PER_M  (BIT(11))
541 #define SPI_MEM_AUTO_PER_V  0x1
542 #define SPI_MEM_AUTO_PER_S  11
543 /* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
544 /*description: SPI_CS line keep low when the bit is set..*/
545 #define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
546 #define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
547 #define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
548 #define SPI_MEM_CS_KEEP_ACTIVE_S  10
549 /* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
550 /*description: 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is i
551 dle..*/
552 #define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
553 #define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
554 #define SPI_MEM_CK_IDLE_EDGE_V  0x1
555 #define SPI_MEM_CK_IDLE_EDGE_S  9
556 /* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
557 /*description: Ext_RAM is connected to SPI SUBPIN bus..*/
558 #define SPI_MEM_SSUB_PIN    (BIT(8))
559 #define SPI_MEM_SSUB_PIN_M  (BIT(8))
560 #define SPI_MEM_SSUB_PIN_V  0x1
561 #define SPI_MEM_SSUB_PIN_S  8
562 /* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
563 /*description: Flash is connected to SPI SUBPIN bus..*/
564 #define SPI_MEM_FSUB_PIN    (BIT(7))
565 #define SPI_MEM_FSUB_PIN_M  (BIT(7))
566 #define SPI_MEM_FSUB_PIN_V  0x1
567 #define SPI_MEM_FSUB_PIN_S  7
568 /* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
569 /*description: Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM)
570  connected to SPI_CS1 is in low level when SPI1 transfer starts..*/
571 #define SPI_MEM_CS1_DIS    (BIT(1))
572 #define SPI_MEM_CS1_DIS_M  (BIT(1))
573 #define SPI_MEM_CS1_DIS_V  0x1
574 #define SPI_MEM_CS1_DIS_S  1
575 /* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
576 /*description: Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) co
577 nnected to SPI_CS is in low level when SPI1 transfer starts..*/
578 #define SPI_MEM_CS0_DIS    (BIT(0))
579 #define SPI_MEM_CS0_DIS_M  (BIT(0))
580 #define SPI_MEM_CS0_DIS_V  0x1
581 #define SPI_MEM_CS0_DIS_S  0
582 
583 #define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
584 /* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
585 /*description: For SPI1, the value of crc32..*/
586 #define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
587 #define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
588 #define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
589 #define SPI_MEM_TX_CRC_DATA_S  0
590 
591 #define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
592 /* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
593 /*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phas
594 e..*/
595 #define SPI_MEM_FADDR_QUAD    (BIT(8))
596 #define SPI_MEM_FADDR_QUAD_M  (BIT(8))
597 #define SPI_MEM_FADDR_QUAD_V  0x1
598 #define SPI_MEM_FADDR_QUAD_S  8
599 /* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
600 /*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phas
601 e..*/
602 #define SPI_MEM_FDOUT_QUAD    (BIT(7))
603 #define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
604 #define SPI_MEM_FDOUT_QUAD_V  0x1
605 #define SPI_MEM_FDOUT_QUAD_S  7
606 /* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
607 /*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase
608 ..*/
609 #define SPI_MEM_FDIN_QUAD    (BIT(6))
610 #define SPI_MEM_FDIN_QUAD_M  (BIT(6))
611 #define SPI_MEM_FDIN_QUAD_V  0x1
612 #define SPI_MEM_FDIN_QUAD_S  6
613 /* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
614 /*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phas
615 e..*/
616 #define SPI_MEM_FADDR_DUAL    (BIT(5))
617 #define SPI_MEM_FADDR_DUAL_M  (BIT(5))
618 #define SPI_MEM_FADDR_DUAL_V  0x1
619 #define SPI_MEM_FADDR_DUAL_S  5
620 /* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
621 /*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phas
622 e..*/
623 #define SPI_MEM_FDOUT_DUAL    (BIT(4))
624 #define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
625 #define SPI_MEM_FDOUT_DUAL_V  0x1
626 #define SPI_MEM_FDOUT_DUAL_S  4
627 /* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
628 /*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase
629 ..*/
630 #define SPI_MEM_FDIN_DUAL    (BIT(3))
631 #define SPI_MEM_FDIN_DUAL_M  (BIT(3))
632 #define SPI_MEM_FDIN_DUAL_V  0x1
633 #define SPI_MEM_FDIN_DUAL_S  3
634 /* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
635 /*description: 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardwa
636 re read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_M
637 EM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits..*/
638 #define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
639 #define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
640 #define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
641 #define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
642 /* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
643 /*description: Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_
644 USR_ADDR_BITLEN should be 31..*/
645 #define SPI_MEM_CACHE_USR_CMD_4BYTE    (BIT(1))
646 #define SPI_MEM_CACHE_USR_CMD_4BYTE_M  (BIT(1))
647 #define SPI_MEM_CACHE_USR_CMD_4BYTE_V  0x1
648 #define SPI_MEM_CACHE_USR_CMD_4BYTE_S  1
649 /* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
650 /*description: Set this bit to enable Cache's access and SPI0's transfer..*/
651 #define SPI_MEM_CACHE_REQ_EN    (BIT(0))
652 #define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
653 #define SPI_MEM_CACHE_REQ_EN_V  0x1
654 #define SPI_MEM_CACHE_REQ_EN_S  0
655 
656 #define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
657 /* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */
658 /*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i
659 n write data transfer..*/
660 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
661 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
662 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
663 #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
664 /* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
665 /*description: Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer..*/
666 #define SPI_MEM_SRAM_OCT    (BIT(21))
667 #define SPI_MEM_SRAM_OCT_M  (BIT(21))
668 #define SPI_MEM_SRAM_OCT_V  0x1
669 #define SPI_MEM_SRAM_OCT_S  21
670 /* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
671 /*description: 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALU
672 E. 0: The value is 0x3..*/
673 #define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
674 #define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
675 #define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
676 #define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
677 /* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
678 /*description: When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The regis
679 ter value shall be (bit_num-1)..*/
680 #define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
681 #define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
682 #define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
683 #define SPI_MEM_SRAM_ADDR_BITLEN_S  14
684 /* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */
685 /*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i
686 n read data transfer..*/
687 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
688 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
689 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
690 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
691 /* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
692 /*description: 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE
693 . 0: The value is 0x2..*/
694 #define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
695 #define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
696 #define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
697 #define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
698 /* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
699 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operat
700 ions..*/
701 #define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
702 #define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
703 #define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
704 #define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
705 /* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
706 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write opera
707 tions..*/
708 #define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
709 #define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
710 #define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
711 #define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
712 /* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
713 /*description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer..*/
714 #define SPI_MEM_USR_SRAM_QIO    (BIT(2))
715 #define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
716 #define SPI_MEM_USR_SRAM_QIO_V  0x1
717 #define SPI_MEM_USR_SRAM_QIO_S  2
718 /* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
719 /*description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer..*/
720 #define SPI_MEM_USR_SRAM_DIO    (BIT(1))
721 #define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
722 #define SPI_MEM_USR_SRAM_DIO_V  0x1
723 #define SPI_MEM_USR_SRAM_DIO_S  1
724 /* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
725 /*description: Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_
726 MEM_SRAM_ADDR_BITLEN should be 31..*/
727 #define SPI_MEM_CACHE_USR_SCMD_4BYTE    (BIT(0))
728 #define SPI_MEM_CACHE_USR_SCMD_4BYTE_M  (BIT(0))
729 #define SPI_MEM_CACHE_USR_SCMD_4BYTE_V  0x1
730 #define SPI_MEM_CACHE_USR_SCMD_4BYTE_S  0
731 
732 #define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
733 /* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */
734 /*description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is
735  output by the SPI0 controller..*/
736 #define SPI_MEM_SDUMMY_OUT    (BIT(22))
737 #define SPI_MEM_SDUMMY_OUT_M  (BIT(22))
738 #define SPI_MEM_SDUMMY_OUT_V  0x1
739 #define SPI_MEM_SDUMMY_OUT_S  22
740 /* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
741 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase..*/
742 #define SPI_MEM_SCMD_OCT    (BIT(21))
743 #define SPI_MEM_SCMD_OCT_M  (BIT(21))
744 #define SPI_MEM_SCMD_OCT_V  0x1
745 #define SPI_MEM_SCMD_OCT_S  21
746 /* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */
747 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase..*/
748 #define SPI_MEM_SADDR_OCT    (BIT(20))
749 #define SPI_MEM_SADDR_OCT_M  (BIT(20))
750 #define SPI_MEM_SADDR_OCT_V  0x1
751 #define SPI_MEM_SADDR_OCT_S  20
752 /* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */
753 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase..*/
754 #define SPI_MEM_SDOUT_OCT    (BIT(19))
755 #define SPI_MEM_SDOUT_OCT_M  (BIT(19))
756 #define SPI_MEM_SDOUT_OCT_V  0x1
757 #define SPI_MEM_SDOUT_OCT_S  19
758 /* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
759 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase..*/
760 #define SPI_MEM_SDIN_OCT    (BIT(18))
761 #define SPI_MEM_SDIN_OCT_M  (BIT(18))
762 #define SPI_MEM_SDIN_OCT_V  0x1
763 #define SPI_MEM_SDIN_OCT_S  18
764 /* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
765 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase..*/
766 #define SPI_MEM_SCMD_QUAD    (BIT(17))
767 #define SPI_MEM_SCMD_QUAD_M  (BIT(17))
768 #define SPI_MEM_SCMD_QUAD_V  0x1
769 #define SPI_MEM_SCMD_QUAD_S  17
770 /* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
771 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase..*/
772 #define SPI_MEM_SADDR_QUAD    (BIT(16))
773 #define SPI_MEM_SADDR_QUAD_M  (BIT(16))
774 #define SPI_MEM_SADDR_QUAD_V  0x1
775 #define SPI_MEM_SADDR_QUAD_S  16
776 /* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
777 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase..*/
778 #define SPI_MEM_SDOUT_QUAD    (BIT(15))
779 #define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
780 #define SPI_MEM_SDOUT_QUAD_V  0x1
781 #define SPI_MEM_SDOUT_QUAD_S  15
782 /* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
783 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase..*/
784 #define SPI_MEM_SDIN_QUAD    (BIT(14))
785 #define SPI_MEM_SDIN_QUAD_M  (BIT(14))
786 #define SPI_MEM_SDIN_QUAD_V  0x1
787 #define SPI_MEM_SDIN_QUAD_S  14
788 /* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */
789 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase..*/
790 #define SPI_MEM_SCMD_DUAL    (BIT(13))
791 #define SPI_MEM_SCMD_DUAL_M  (BIT(13))
792 #define SPI_MEM_SCMD_DUAL_V  0x1
793 #define SPI_MEM_SCMD_DUAL_S  13
794 /* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
795 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase..*/
796 #define SPI_MEM_SADDR_DUAL    (BIT(12))
797 #define SPI_MEM_SADDR_DUAL_M  (BIT(12))
798 #define SPI_MEM_SADDR_DUAL_V  0x1
799 #define SPI_MEM_SADDR_DUAL_S  12
800 /* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
801 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase..*/
802 #define SPI_MEM_SDOUT_DUAL    (BIT(11))
803 #define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
804 #define SPI_MEM_SDOUT_DUAL_V  0x1
805 #define SPI_MEM_SDOUT_DUAL_S  11
806 /* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
807 /*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase..*/
808 #define SPI_MEM_SDIN_DUAL    (BIT(10))
809 #define SPI_MEM_SDIN_DUAL_M  (BIT(10))
810 #define SPI_MEM_SDIN_DUAL_V  0x1
811 #define SPI_MEM_SDIN_DUAL_S  10
812 /* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
813 /*description: Mode bits when SPI0 accesses to Ext_RAM..*/
814 #define SPI_MEM_SWB_MODE    0x000000FF
815 #define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
816 #define SPI_MEM_SWB_MODE_V  0xFF
817 #define SPI_MEM_SWB_MODE_S  2
818 /* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
819 /*description: SPI_CLK mode bits  when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inac
820 tive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two
821  cycles after CS inactive 3: SPI_CLK is always on..*/
822 #define SPI_MEM_SCLK_MODE    0x00000003
823 #define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
824 #define SPI_MEM_SCLK_MODE_V  0x3
825 #define SPI_MEM_SCLK_MODE_S  0
826 
827 #define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
828 /* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
829 /*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register val
830 ue shall be (bit_num-1)..*/
831 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
832 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
833 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
834 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
835 /* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
836 /*description: When SPI0 reads Ext_RAM, it is the command value of CMD phase..*/
837 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
838 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
839 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
840 #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
841 
842 #define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
843 /* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
844 /*description: When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register va
845 lue shall be (bit_num-1)..*/
846 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
847 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
848 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
849 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
850 /* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
851 /*description: When SPI0 writes Ext_RAM, it is the command value of CMD phase..*/
852 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
853 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
854 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
855 #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
856 
857 #define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
858 /* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
859 /*description: When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MS
860 PI_CORE_CLK..*/
861 #define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
862 #define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
863 #define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
864 #define SPI_MEM_SCLK_EQU_SYSCLK_S  31
865 /* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
866 /*description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1).*/
867 #define SPI_MEM_SCLKCNT_N    0x000000FF
868 #define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
869 #define SPI_MEM_SCLKCNT_N_V  0xFF
870 #define SPI_MEM_SCLKCNT_N_S  16
871 /* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
872 /*description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1)..*/
873 #define SPI_MEM_SCLKCNT_H    0x000000FF
874 #define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
875 #define SPI_MEM_SCLKCNT_H_V  0xFF
876 #define SPI_MEM_SCLKCNT_H_S  8
877 /* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
878 /*description: It must equal to the value of SPI_MEM_SCLKCNT_N. .*/
879 #define SPI_MEM_SCLKCNT_L    0x000000FF
880 #define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
881 #define SPI_MEM_SCLKCNT_L_V  0xFF
882 #define SPI_MEM_SCLKCNT_L_S  0
883 
884 #define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
885 /* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
886 /*description: The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP
887 ), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DI
888 N), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)..*/
889 #define SPI_MEM_ST    0x00000007
890 #define SPI_MEM_ST_M  ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S))
891 #define SPI_MEM_ST_V  0x7
892 #define SPI_MEM_ST_S  0
893 
894 #define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
895 /* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
896 /*description: data buffer.*/
897 #define SPI_MEM_BUF0    0xFFFFFFFF
898 #define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
899 #define SPI_MEM_BUF0_V  0xFFFFFFFF
900 #define SPI_MEM_BUF0_S  0
901 
902 #define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
903 /* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
904 /*description: data buffer.*/
905 #define SPI_MEM_BUF1    0xFFFFFFFF
906 #define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
907 #define SPI_MEM_BUF1_V  0xFFFFFFFF
908 #define SPI_MEM_BUF1_S  0
909 
910 #define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
911 /* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
912 /*description: data buffer.*/
913 #define SPI_MEM_BUF2    0xFFFFFFFF
914 #define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
915 #define SPI_MEM_BUF2_V  0xFFFFFFFF
916 #define SPI_MEM_BUF2_S  0
917 
918 #define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
919 /* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
920 /*description: data buffer.*/
921 #define SPI_MEM_BUF3    0xFFFFFFFF
922 #define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
923 #define SPI_MEM_BUF3_V  0xFFFFFFFF
924 #define SPI_MEM_BUF3_S  0
925 
926 #define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
927 /* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
928 /*description: data buffer.*/
929 #define SPI_MEM_BUF4    0xFFFFFFFF
930 #define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
931 #define SPI_MEM_BUF4_V  0xFFFFFFFF
932 #define SPI_MEM_BUF4_S  0
933 
934 #define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
935 /* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
936 /*description: data buffer.*/
937 #define SPI_MEM_BUF5    0xFFFFFFFF
938 #define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
939 #define SPI_MEM_BUF5_V  0xFFFFFFFF
940 #define SPI_MEM_BUF5_S  0
941 
942 #define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
943 /* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
944 /*description: data buffer.*/
945 #define SPI_MEM_BUF6    0xFFFFFFFF
946 #define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
947 #define SPI_MEM_BUF6_V  0xFFFFFFFF
948 #define SPI_MEM_BUF6_S  0
949 
950 #define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
951 /* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
952 /*description: data buffer.*/
953 #define SPI_MEM_BUF7    0xFFFFFFFF
954 #define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
955 #define SPI_MEM_BUF7_V  0xFFFFFFFF
956 #define SPI_MEM_BUF7_S  0
957 
958 #define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
959 /* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
960 /*description: data buffer.*/
961 #define SPI_MEM_BUF8    0xFFFFFFFF
962 #define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
963 #define SPI_MEM_BUF8_V  0xFFFFFFFF
964 #define SPI_MEM_BUF8_S  0
965 
966 #define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
967 /* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
968 /*description: data buffer.*/
969 #define SPI_MEM_BUF9    0xFFFFFFFF
970 #define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
971 #define SPI_MEM_BUF9_V  0xFFFFFFFF
972 #define SPI_MEM_BUF9_S  0
973 
974 #define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
975 /* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
976 /*description: data buffer.*/
977 #define SPI_MEM_BUF10    0xFFFFFFFF
978 #define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
979 #define SPI_MEM_BUF10_V  0xFFFFFFFF
980 #define SPI_MEM_BUF10_S  0
981 
982 #define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
983 /* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
984 /*description: data buffer.*/
985 #define SPI_MEM_BUF11    0xFFFFFFFF
986 #define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
987 #define SPI_MEM_BUF11_V  0xFFFFFFFF
988 #define SPI_MEM_BUF11_S  0
989 
990 #define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
991 /* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
992 /*description: data buffer.*/
993 #define SPI_MEM_BUF12    0xFFFFFFFF
994 #define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
995 #define SPI_MEM_BUF12_V  0xFFFFFFFF
996 #define SPI_MEM_BUF12_S  0
997 
998 #define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
999 /* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
1000 /*description: data buffer.*/
1001 #define SPI_MEM_BUF13    0xFFFFFFFF
1002 #define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
1003 #define SPI_MEM_BUF13_V  0xFFFFFFFF
1004 #define SPI_MEM_BUF13_S  0
1005 
1006 #define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
1007 /* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
1008 /*description: data buffer.*/
1009 #define SPI_MEM_BUF14    0xFFFFFFFF
1010 #define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
1011 #define SPI_MEM_BUF14_V  0xFFFFFFFF
1012 #define SPI_MEM_BUF14_S  0
1013 
1014 #define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
1015 /* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
1016 /*description: data buffer.*/
1017 #define SPI_MEM_BUF15    0xFFFFFFFF
1018 #define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
1019 #define SPI_MEM_BUF15_V  0xFFFFFFFF
1020 #define SPI_MEM_BUF15_S  0
1021 
1022 #define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
1023 /* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
1024 /*description: The dummy cycle length when wait flash idle(RDSR)..*/
1025 #define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
1026 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
1027 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
1028 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
1029 /* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
1030 /*description: The command value of auto wait flash idle transfer(RDSR)..*/
1031 #define SPI_MEM_WAITI_CMD    0x000000FF
1032 #define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
1033 #define SPI_MEM_WAITI_CMD_V  0xFF
1034 #define SPI_MEM_WAITI_CMD_S  2
1035 /* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
1036 /*description: Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR)..*/
1037 #define SPI_MEM_WAITI_DUMMY    (BIT(1))
1038 #define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
1039 #define SPI_MEM_WAITI_DUMMY_V  0x1
1040 #define SPI_MEM_WAITI_DUMMY_S  1
1041 /* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
1042 /*description: Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/P
1043 ES command is sent..*/
1044 #define SPI_MEM_WAITI_EN    (BIT(0))
1045 #define SPI_MEM_WAITI_EN_M  (BIT(0))
1046 #define SPI_MEM_WAITI_EN_V  0x1
1047 #define SPI_MEM_WAITI_EN_S  0
1048 
1049 #define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
1050 /* SPI_MEM_PESR_IDLE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
1051 /*description: 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate..*/
1052 #define SPI_MEM_PESR_IDLE_EN    (BIT(5))
1053 #define SPI_MEM_PESR_IDLE_EN_M  (BIT(5))
1054 #define SPI_MEM_PESR_IDLE_EN_V  0x1
1055 #define SPI_MEM_PESR_IDLE_EN_S  5
1056 /* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
1057 /*description: Set this bit to enable PES transfer trigger PES transfer option..*/
1058 #define SPI_MEM_PES_PER_EN    (BIT(4))
1059 #define SPI_MEM_PES_PER_EN_M  (BIT(4))
1060 #define SPI_MEM_PES_PER_EN_V  0x1
1061 #define SPI_MEM_PES_PER_EN_S  4
1062 /* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
1063 /*description: Set this bit to add delay time after program erase suspend(PES) command is sent..*/
1064 #define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
1065 #define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
1066 #define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
1067 #define SPI_MEM_FLASH_PES_WAIT_EN_S  3
1068 /* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
1069 /*description: Set this bit to add delay time after program erase resume(PER) is sent..*/
1070 #define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
1071 #define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
1072 #define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
1073 #define SPI_MEM_FLASH_PER_WAIT_EN_S  2
1074 /* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */
1075 /*description: program erase suspend bit, program erase suspend operation will be triggered whe
1076 n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
1077 isable. .*/
1078 #define SPI_MEM_FLASH_PES    (BIT(1))
1079 #define SPI_MEM_FLASH_PES_M  (BIT(1))
1080 #define SPI_MEM_FLASH_PES_V  0x1
1081 #define SPI_MEM_FLASH_PES_S  1
1082 /* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */
1083 /*description: program erase resume bit, program erase suspend operation will be triggered when
1084  the bit is set. The bit will be cleared once the operation done.1: enable 0: di
1085 sable. .*/
1086 #define SPI_MEM_FLASH_PER    (BIT(0))
1087 #define SPI_MEM_FLASH_PER_M  (BIT(0))
1088 #define SPI_MEM_FLASH_PER_V  0x1
1089 #define SPI_MEM_FLASH_PER_S  0
1090 
1091 #define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
1092 /* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */
1093 /*description: Program/Erase suspend command value..*/
1094 #define SPI_MEM_FLASH_PES_COMMAND    0x000000FF
1095 #define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
1096 #define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
1097 #define SPI_MEM_FLASH_PES_COMMAND_S  9
1098 /* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */
1099 /*description: Program/Erase resume command value..*/
1100 #define SPI_MEM_FLASH_PER_COMMAND    0x000000FF
1101 #define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
1102 #define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
1103 #define SPI_MEM_FLASH_PER_COMMAND_S  1
1104 /* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
1105 /*description: Set this bit to enable auto-suspend function..*/
1106 #define SPI_MEM_FLASH_PES_EN    (BIT(0))
1107 #define SPI_MEM_FLASH_PES_EN_M  (BIT(0))
1108 #define SPI_MEM_FLASH_PES_EN_V  0x1
1109 #define SPI_MEM_FLASH_PES_EN_S  0
1110 
1111 #define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
1112 /* SPI_MEM_FLASH_PES_DLY_256 : R/W ;bitpos:[6] ;default: 1'b0 ; */
1113 /*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
1114 RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
1115 _CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
1116 #define SPI_MEM_FLASH_PES_DLY_256    (BIT(6))
1117 #define SPI_MEM_FLASH_PES_DLY_256_M  (BIT(6))
1118 #define SPI_MEM_FLASH_PES_DLY_256_V  0x1
1119 #define SPI_MEM_FLASH_PES_DLY_256_S  6
1120 /* SPI_MEM_FLASH_PER_DLY_256 : R/W ;bitpos:[5] ;default: 1'b0 ; */
1121 /*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
1122 RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
1123 _CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
1124 #define SPI_MEM_FLASH_PER_DLY_256    (BIT(5))
1125 #define SPI_MEM_FLASH_PER_DLY_256_M  (BIT(5))
1126 #define SPI_MEM_FLASH_PER_DLY_256_V  0x1
1127 #define SPI_MEM_FLASH_PER_DLY_256_S  5
1128 /* SPI_MEM_FLASH_DP_DLY_256 : R/W ;bitpos:[4] ;default: 1'b0 ; */
1129 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP com
1130 mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
1131 after DP command is sent..*/
1132 #define SPI_MEM_FLASH_DP_DLY_256    (BIT(4))
1133 #define SPI_MEM_FLASH_DP_DLY_256_M  (BIT(4))
1134 #define SPI_MEM_FLASH_DP_DLY_256_V  0x1
1135 #define SPI_MEM_FLASH_DP_DLY_256_S  4
1136 /* SPI_MEM_FLASH_RES_DLY_256 : R/W ;bitpos:[3] ;default: 1'b0 ; */
1137 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES co
1138 mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
1139  after RES command is sent..*/
1140 #define SPI_MEM_FLASH_RES_DLY_256    (BIT(3))
1141 #define SPI_MEM_FLASH_RES_DLY_256_M  (BIT(3))
1142 #define SPI_MEM_FLASH_RES_DLY_256_V  0x1
1143 #define SPI_MEM_FLASH_RES_DLY_256_S  3
1144 /* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */
1145 /*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM co
1146 mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
1147  after HPM command is sent..*/
1148 #define SPI_MEM_FLASH_HPM_DLY_256    (BIT(2))
1149 #define SPI_MEM_FLASH_HPM_DLY_256_M  (BIT(2))
1150 #define SPI_MEM_FLASH_HPM_DLY_256_V  0x1
1151 #define SPI_MEM_FLASH_HPM_DLY_256_S  2
1152 /* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
1153 /*description: The status of flash suspend. This bit is set when PES command is sent, and clear
1154 ed when PER is sent. Only used in SPI1..*/
1155 #define SPI_MEM_FLASH_SUS    (BIT(0))
1156 #define SPI_MEM_FLASH_SUS_M  (BIT(0))
1157 #define SPI_MEM_FLASH_SUS_V  0x1
1158 #define SPI_MEM_FLASH_SUS_S  0
1159 
1160 #define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA8)
1161 /* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
1162 /*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when S
1163 PI_MEM_TIMING_CALI bit is set..*/
1164 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
1165 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
1166 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
1167 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
1168 /* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
1169 /*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio
1170 ns..*/
1171 #define SPI_MEM_TIMING_CALI    (BIT(1))
1172 #define SPI_MEM_TIMING_CALI_M  (BIT(1))
1173 #define SPI_MEM_TIMING_CALI_V  0x1
1174 #define SPI_MEM_TIMING_CALI_S  1
1175 /* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
1176 /*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
1177 als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
1178 #define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
1179 #define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
1180 #define SPI_MEM_TIMING_CLK_ENA_V  0x1
1181 #define SPI_MEM_TIMING_CLK_ENA_S  0
1182 
1183 #define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xAC)
1184 /* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
1185 /*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles
1186 at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK
1187  positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
1188 EM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negat
1189 ive edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one
1190  cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles
1191 at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1192 #define SPI_MEM_DINS_MODE    0x00000007
1193 #define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
1194 #define SPI_MEM_DINS_MODE_V  0x7
1195 #define SPI_MEM_DINS_MODE_S  24
1196 /* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
1197 /*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
1198  at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
1199 LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
1200 _MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
1201 gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
1202  one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
1203 cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1204 #define SPI_MEM_DIN7_MODE    0x00000007
1205 #define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
1206 #define SPI_MEM_DIN7_MODE_V  0x7
1207 #define SPI_MEM_DIN7_MODE_S  21
1208 /* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
1209 /*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
1210  at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
1211 LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
1212 _MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
1213 gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
1214  one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
1215 cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1216 #define SPI_MEM_DIN6_MODE    0x00000007
1217 #define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
1218 #define SPI_MEM_DIN6_MODE_V  0x7
1219 #define SPI_MEM_DIN6_MODE_S  18
1220 /* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
1221 /*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
1222  at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
1223 LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
1224 _MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
1225 gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
1226  one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
1227 cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1228 #define SPI_MEM_DIN5_MODE    0x00000007
1229 #define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
1230 #define SPI_MEM_DIN5_MODE_V  0x7
1231 #define SPI_MEM_DIN5_MODE_S  15
1232 /* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
1233 /*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
1234  at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
1235 LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
1236 _MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
1237 gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
1238  one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
1239 cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1240 #define SPI_MEM_DIN4_MODE    0x00000007
1241 #define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
1242 #define SPI_MEM_DIN4_MODE_V  0x7
1243 #define SPI_MEM_DIN4_MODE_S  12
1244 /* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
1245 /*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
1246 at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
1247 K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
1248 MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg
1249 ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
1250 one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
1251 les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1252 #define SPI_MEM_DIN3_MODE    0x00000007
1253 #define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
1254 #define SPI_MEM_DIN3_MODE_V  0x7
1255 #define SPI_MEM_DIN3_MODE_S  9
1256 /* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
1257 /*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
1258 at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
1259 K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
1260 MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg
1261 ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
1262 one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
1263 les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1264 #define SPI_MEM_DIN2_MODE    0x00000007
1265 #define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
1266 #define SPI_MEM_DIN2_MODE_V  0x7
1267 #define SPI_MEM_DIN2_MODE_S  6
1268 /* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
1269 /*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a
1270 t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK
1271  positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
1272 EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega
1273 tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o
1274 ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl
1275 es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1276 #define SPI_MEM_DIN1_MODE    0x00000007
1277 #define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
1278 #define SPI_MEM_DIN1_MODE_V  0x7
1279 #define SPI_MEM_DIN1_MODE_S  3
1280 /* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
1281 /*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a
1282 t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK
1283  positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
1284 EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega
1285 tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o
1286 ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl
1287 es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1288 #define SPI_MEM_DIN0_MODE    0x00000007
1289 #define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
1290 #define SPI_MEM_DIN0_MODE_V  0x7
1291 #define SPI_MEM_DIN0_MODE_S  0
1292 
1293 #define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB0)
1294 /* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
1295 /*description: SPI_DQS input delay number..*/
1296 #define SPI_MEM_DINS_NUM    0x00000003
1297 #define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
1298 #define SPI_MEM_DINS_NUM_V  0x3
1299 #define SPI_MEM_DINS_NUM_S  16
1300 /* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
1301 /*description: SPI_IO7 input delay number..*/
1302 #define SPI_MEM_DIN7_NUM    0x00000003
1303 #define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
1304 #define SPI_MEM_DIN7_NUM_V  0x3
1305 #define SPI_MEM_DIN7_NUM_S  14
1306 /* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
1307 /*description: SPI_IO6 input delay number..*/
1308 #define SPI_MEM_DIN6_NUM    0x00000003
1309 #define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
1310 #define SPI_MEM_DIN6_NUM_V  0x3
1311 #define SPI_MEM_DIN6_NUM_S  12
1312 /* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
1313 /*description: SPI_IO5 input delay number..*/
1314 #define SPI_MEM_DIN5_NUM    0x00000003
1315 #define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
1316 #define SPI_MEM_DIN5_NUM_V  0x3
1317 #define SPI_MEM_DIN5_NUM_S  10
1318 /* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
1319 /*description: SPI_IO4 input delay number..*/
1320 #define SPI_MEM_DIN4_NUM    0x00000003
1321 #define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
1322 #define SPI_MEM_DIN4_NUM_V  0x3
1323 #define SPI_MEM_DIN4_NUM_S  8
1324 /* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
1325 /*description: SPI_HD input delay number..*/
1326 #define SPI_MEM_DIN3_NUM    0x00000003
1327 #define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
1328 #define SPI_MEM_DIN3_NUM_V  0x3
1329 #define SPI_MEM_DIN3_NUM_S  6
1330 /* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
1331 /*description: SPI_WP input delay number..*/
1332 #define SPI_MEM_DIN2_NUM    0x00000003
1333 #define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
1334 #define SPI_MEM_DIN2_NUM_V  0x3
1335 #define SPI_MEM_DIN2_NUM_S  4
1336 /* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
1337 /*description: SPI_Q input delay number..*/
1338 #define SPI_MEM_DIN1_NUM    0x00000003
1339 #define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
1340 #define SPI_MEM_DIN1_NUM_V  0x3
1341 #define SPI_MEM_DIN1_NUM_S  2
1342 /* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
1343 /*description: SPI_D input delay number..*/
1344 #define SPI_MEM_DIN0_NUM    0x00000003
1345 #define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
1346 #define SPI_MEM_DIN0_NUM_V  0x3
1347 #define SPI_MEM_DIN0_NUM_S  0
1348 
1349 #define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB4)
1350 /* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
1351 /*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1352 tive edge..*/
1353 #define SPI_MEM_DOUTS_MODE    (BIT(8))
1354 #define SPI_MEM_DOUTS_MODE_M  (BIT(8))
1355 #define SPI_MEM_DOUTS_MODE_V  0x1
1356 #define SPI_MEM_DOUTS_MODE_S  8
1357 /* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
1358 /*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1359 tive edge..*/
1360 #define SPI_MEM_DOUT7_MODE    (BIT(7))
1361 #define SPI_MEM_DOUT7_MODE_M  (BIT(7))
1362 #define SPI_MEM_DOUT7_MODE_V  0x1
1363 #define SPI_MEM_DOUT7_MODE_S  7
1364 /* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
1365 /*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1366 tive edge..*/
1367 #define SPI_MEM_DOUT6_MODE    (BIT(6))
1368 #define SPI_MEM_DOUT6_MODE_M  (BIT(6))
1369 #define SPI_MEM_DOUT6_MODE_V  0x1
1370 #define SPI_MEM_DOUT6_MODE_S  6
1371 /* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
1372 /*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1373 tive edge..*/
1374 #define SPI_MEM_DOUT5_MODE    (BIT(5))
1375 #define SPI_MEM_DOUT5_MODE_M  (BIT(5))
1376 #define SPI_MEM_DOUT5_MODE_V  0x1
1377 #define SPI_MEM_DOUT5_MODE_S  5
1378 /* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
1379 /*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1380 tive edge..*/
1381 #define SPI_MEM_DOUT4_MODE    (BIT(4))
1382 #define SPI_MEM_DOUT4_MODE_M  (BIT(4))
1383 #define SPI_MEM_DOUT4_MODE_V  0x1
1384 #define SPI_MEM_DOUT4_MODE_S  4
1385 /* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
1386 /*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
1387 ive edge..*/
1388 #define SPI_MEM_DOUT3_MODE    (BIT(3))
1389 #define SPI_MEM_DOUT3_MODE_M  (BIT(3))
1390 #define SPI_MEM_DOUT3_MODE_V  0x1
1391 #define SPI_MEM_DOUT3_MODE_S  3
1392 /* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
1393 /*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
1394 ive edge..*/
1395 #define SPI_MEM_DOUT2_MODE    (BIT(2))
1396 #define SPI_MEM_DOUT2_MODE_M  (BIT(2))
1397 #define SPI_MEM_DOUT2_MODE_V  0x1
1398 #define SPI_MEM_DOUT2_MODE_S  2
1399 /* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
1400 /*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
1401 ve edge..*/
1402 #define SPI_MEM_DOUT1_MODE    (BIT(1))
1403 #define SPI_MEM_DOUT1_MODE_M  (BIT(1))
1404 #define SPI_MEM_DOUT1_MODE_V  0x1
1405 #define SPI_MEM_DOUT1_MODE_S  1
1406 /* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
1407 /*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
1408 ve edge..*/
1409 #define SPI_MEM_DOUT0_MODE    (BIT(0))
1410 #define SPI_MEM_DOUT0_MODE_M  (BIT(0))
1411 #define SPI_MEM_DOUT0_MODE_V  0x1
1412 #define SPI_MEM_DOUT0_MODE_S  0
1413 
1414 #define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xBC)
1415 /* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
1416 /*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 acc
1417 esses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set..*/
1418 #define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
1419 #define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
1420 #define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
1421 #define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
1422 /* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
1423 /*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio
1424 ns..*/
1425 #define SPI_MEM_SPI_SMEM_TIMING_CALI    (BIT(1))
1426 #define SPI_MEM_SPI_SMEM_TIMING_CALI_M  (BIT(1))
1427 #define SPI_MEM_SPI_SMEM_TIMING_CALI_V  0x1
1428 #define SPI_MEM_SPI_SMEM_TIMING_CALI_S  1
1429 /* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
1430 /*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
1431 als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
1432 #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
1433 #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
1434 #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V  0x1
1435 #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S  0
1436 
1437 #define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
1438 /* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
1439 /*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles
1440  at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HC
1441 LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
1442 _SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
1443 gative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and
1444  one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cy
1445 cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1446 #define SPI_MEM_SPI_SMEM_DINS_MODE    0x00000007
1447 #define SPI_MEM_SPI_SMEM_DINS_MODE_M  ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S))
1448 #define SPI_MEM_SPI_SMEM_DINS_MODE_V  0x7
1449 #define SPI_MEM_SPI_SMEM_DINS_MODE_S  24
1450 /* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
1451 /*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
1452 s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
1453 HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
1454 PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
1455  negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
1456  and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
1457 1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1458 #define SPI_MEM_SPI_SMEM_DIN7_MODE    0x00000007
1459 #define SPI_MEM_SPI_SMEM_DIN7_MODE_M  ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S))
1460 #define SPI_MEM_SPI_SMEM_DIN7_MODE_V  0x7
1461 #define SPI_MEM_SPI_SMEM_DIN7_MODE_S  21
1462 /* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
1463 /*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
1464 s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
1465 HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
1466 PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
1467  negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
1468  and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
1469 1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1470 #define SPI_MEM_SPI_SMEM_DIN6_MODE    0x00000007
1471 #define SPI_MEM_SPI_SMEM_DIN6_MODE_M  ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S))
1472 #define SPI_MEM_SPI_SMEM_DIN6_MODE_V  0x7
1473 #define SPI_MEM_SPI_SMEM_DIN6_MODE_S  18
1474 /* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
1475 /*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
1476 s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
1477 HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
1478 PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
1479  negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
1480  and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
1481 1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1482 #define SPI_MEM_SPI_SMEM_DIN5_MODE    0x00000007
1483 #define SPI_MEM_SPI_SMEM_DIN5_MODE_M  ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S))
1484 #define SPI_MEM_SPI_SMEM_DIN5_MODE_V  0x7
1485 #define SPI_MEM_SPI_SMEM_DIN5_MODE_S  15
1486 /* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
1487 /*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
1488 s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
1489 HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
1490 PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
1491  negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
1492  and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
1493 1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1494 #define SPI_MEM_SPI_SMEM_DIN4_MODE    0x00000007
1495 #define SPI_MEM_SPI_SMEM_DIN4_MODE_M  ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S))
1496 #define SPI_MEM_SPI_SMEM_DIN4_MODE_V  0x7
1497 #define SPI_MEM_SPI_SMEM_DIN4_MODE_S  12
1498 /* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
1499 /*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
1500  at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H
1501 CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP
1502 I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
1503 negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
1504 and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
1505 ) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1506 #define SPI_MEM_SPI_SMEM_DIN3_MODE    0x00000007
1507 #define SPI_MEM_SPI_SMEM_DIN3_MODE_M  ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S))
1508 #define SPI_MEM_SPI_SMEM_DIN3_MODE_V  0x7
1509 #define SPI_MEM_SPI_SMEM_DIN3_MODE_S  9
1510 /* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
1511 /*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
1512  at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H
1513 CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP
1514 I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
1515 negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
1516 and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
1517 ) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1518 #define SPI_MEM_SPI_SMEM_DIN2_MODE    0x00000007
1519 #define SPI_MEM_SPI_SMEM_DIN2_MODE_M  ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S))
1520 #define SPI_MEM_SPI_SMEM_DIN2_MODE_V  0x7
1521 #define SPI_MEM_SPI_SMEM_DIN2_MODE_S  6
1522 /* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
1523 /*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
1524 at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
1525 LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
1526 _SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
1527 egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a
1528 nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
1529  cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1530 #define SPI_MEM_SPI_SMEM_DIN1_MODE    0x00000007
1531 #define SPI_MEM_SPI_SMEM_DIN1_MODE_M  ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S))
1532 #define SPI_MEM_SPI_SMEM_DIN1_MODE_V  0x7
1533 #define SPI_MEM_SPI_SMEM_DIN1_MODE_S  3
1534 /* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
1535 /*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
1536 at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
1537 LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
1538 _SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
1539 egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a
1540 nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
1541  cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
1542 #define SPI_MEM_SPI_SMEM_DIN0_MODE    0x00000007
1543 #define SPI_MEM_SPI_SMEM_DIN0_MODE_M  ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S))
1544 #define SPI_MEM_SPI_SMEM_DIN0_MODE_V  0x7
1545 #define SPI_MEM_SPI_SMEM_DIN0_MODE_S  0
1546 
1547 #define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
1548 /* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
1549 /*description: SPI_DQS input delay number..*/
1550 #define SPI_MEM_SPI_SMEM_DINS_NUM    0x00000003
1551 #define SPI_MEM_SPI_SMEM_DINS_NUM_M  ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S))
1552 #define SPI_MEM_SPI_SMEM_DINS_NUM_V  0x3
1553 #define SPI_MEM_SPI_SMEM_DINS_NUM_S  16
1554 /* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
1555 /*description: SPI_IO7 input delay number..*/
1556 #define SPI_MEM_SPI_SMEM_DIN7_NUM    0x00000003
1557 #define SPI_MEM_SPI_SMEM_DIN7_NUM_M  ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S))
1558 #define SPI_MEM_SPI_SMEM_DIN7_NUM_V  0x3
1559 #define SPI_MEM_SPI_SMEM_DIN7_NUM_S  14
1560 /* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
1561 /*description: SPI_IO6 input delay number..*/
1562 #define SPI_MEM_SPI_SMEM_DIN6_NUM    0x00000003
1563 #define SPI_MEM_SPI_SMEM_DIN6_NUM_M  ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S))
1564 #define SPI_MEM_SPI_SMEM_DIN6_NUM_V  0x3
1565 #define SPI_MEM_SPI_SMEM_DIN6_NUM_S  12
1566 /* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
1567 /*description: SPI_IO5 input delay number..*/
1568 #define SPI_MEM_SPI_SMEM_DIN5_NUM    0x00000003
1569 #define SPI_MEM_SPI_SMEM_DIN5_NUM_M  ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S))
1570 #define SPI_MEM_SPI_SMEM_DIN5_NUM_V  0x3
1571 #define SPI_MEM_SPI_SMEM_DIN5_NUM_S  10
1572 /* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
1573 /*description: SPI_IO4 input delay number..*/
1574 #define SPI_MEM_SPI_SMEM_DIN4_NUM    0x00000003
1575 #define SPI_MEM_SPI_SMEM_DIN4_NUM_M  ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S))
1576 #define SPI_MEM_SPI_SMEM_DIN4_NUM_V  0x3
1577 #define SPI_MEM_SPI_SMEM_DIN4_NUM_S  8
1578 /* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
1579 /*description: SPI_HD input delay number..*/
1580 #define SPI_MEM_SPI_SMEM_DIN3_NUM    0x00000003
1581 #define SPI_MEM_SPI_SMEM_DIN3_NUM_M  ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S))
1582 #define SPI_MEM_SPI_SMEM_DIN3_NUM_V  0x3
1583 #define SPI_MEM_SPI_SMEM_DIN3_NUM_S  6
1584 /* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
1585 /*description: SPI_WP input delay number..*/
1586 #define SPI_MEM_SPI_SMEM_DIN2_NUM    0x00000003
1587 #define SPI_MEM_SPI_SMEM_DIN2_NUM_M  ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S))
1588 #define SPI_MEM_SPI_SMEM_DIN2_NUM_V  0x3
1589 #define SPI_MEM_SPI_SMEM_DIN2_NUM_S  4
1590 /* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
1591 /*description: SPI_Q input delay number..*/
1592 #define SPI_MEM_SPI_SMEM_DIN1_NUM    0x00000003
1593 #define SPI_MEM_SPI_SMEM_DIN1_NUM_M  ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S))
1594 #define SPI_MEM_SPI_SMEM_DIN1_NUM_V  0x3
1595 #define SPI_MEM_SPI_SMEM_DIN1_NUM_S  2
1596 /* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
1597 /*description: SPI_D input delay number..*/
1598 #define SPI_MEM_SPI_SMEM_DIN0_NUM    0x00000003
1599 #define SPI_MEM_SPI_SMEM_DIN0_NUM_M  ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S))
1600 #define SPI_MEM_SPI_SMEM_DIN0_NUM_V  0x3
1601 #define SPI_MEM_SPI_SMEM_DIN0_NUM_S  0
1602 
1603 #define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
1604 /* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
1605 /*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1606 tive edge..*/
1607 #define SPI_MEM_SPI_SMEM_DOUTS_MODE    (BIT(8))
1608 #define SPI_MEM_SPI_SMEM_DOUTS_MODE_M  (BIT(8))
1609 #define SPI_MEM_SPI_SMEM_DOUTS_MODE_V  0x1
1610 #define SPI_MEM_SPI_SMEM_DOUTS_MODE_S  8
1611 /* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
1612 /*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1613 tive edge..*/
1614 #define SPI_MEM_SPI_SMEM_DOUT7_MODE    (BIT(7))
1615 #define SPI_MEM_SPI_SMEM_DOUT7_MODE_M  (BIT(7))
1616 #define SPI_MEM_SPI_SMEM_DOUT7_MODE_V  0x1
1617 #define SPI_MEM_SPI_SMEM_DOUT7_MODE_S  7
1618 /* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
1619 /*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1620 tive edge..*/
1621 #define SPI_MEM_SPI_SMEM_DOUT6_MODE    (BIT(6))
1622 #define SPI_MEM_SPI_SMEM_DOUT6_MODE_M  (BIT(6))
1623 #define SPI_MEM_SPI_SMEM_DOUT6_MODE_V  0x1
1624 #define SPI_MEM_SPI_SMEM_DOUT6_MODE_S  6
1625 /* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
1626 /*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1627 tive edge..*/
1628 #define SPI_MEM_SPI_SMEM_DOUT5_MODE    (BIT(5))
1629 #define SPI_MEM_SPI_SMEM_DOUT5_MODE_M  (BIT(5))
1630 #define SPI_MEM_SPI_SMEM_DOUT5_MODE_V  0x1
1631 #define SPI_MEM_SPI_SMEM_DOUT5_MODE_S  5
1632 /* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
1633 /*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
1634 tive edge..*/
1635 #define SPI_MEM_SPI_SMEM_DOUT4_MODE    (BIT(4))
1636 #define SPI_MEM_SPI_SMEM_DOUT4_MODE_M  (BIT(4))
1637 #define SPI_MEM_SPI_SMEM_DOUT4_MODE_V  0x1
1638 #define SPI_MEM_SPI_SMEM_DOUT4_MODE_S  4
1639 /* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
1640 /*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
1641 ive edge..*/
1642 #define SPI_MEM_SPI_SMEM_DOUT3_MODE    (BIT(3))
1643 #define SPI_MEM_SPI_SMEM_DOUT3_MODE_M  (BIT(3))
1644 #define SPI_MEM_SPI_SMEM_DOUT3_MODE_V  0x1
1645 #define SPI_MEM_SPI_SMEM_DOUT3_MODE_S  3
1646 /* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
1647 /*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
1648 ive edge..*/
1649 #define SPI_MEM_SPI_SMEM_DOUT2_MODE    (BIT(2))
1650 #define SPI_MEM_SPI_SMEM_DOUT2_MODE_M  (BIT(2))
1651 #define SPI_MEM_SPI_SMEM_DOUT2_MODE_V  0x1
1652 #define SPI_MEM_SPI_SMEM_DOUT2_MODE_S  2
1653 /* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
1654 /*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
1655 ve edge..*/
1656 #define SPI_MEM_SPI_SMEM_DOUT1_MODE    (BIT(1))
1657 #define SPI_MEM_SPI_SMEM_DOUT1_MODE_M  (BIT(1))
1658 #define SPI_MEM_SPI_SMEM_DOUT1_MODE_V  0x1
1659 #define SPI_MEM_SPI_SMEM_DOUT1_MODE_S  1
1660 /* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
1661 /*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
1662 ve edge..*/
1663 #define SPI_MEM_SPI_SMEM_DOUT0_MODE    (BIT(0))
1664 #define SPI_MEM_SPI_SMEM_DOUT0_MODE_M  (BIT(0))
1665 #define SPI_MEM_SPI_SMEM_DOUT0_MODE_V  0x1
1666 #define SPI_MEM_SPI_SMEM_DOUT0_MODE_S  0
1667 
1668 #define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
1669 /* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
1670 /*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
1671 h..*/
1672 #define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN    (BIT(8))
1673 #define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M  (BIT(8))
1674 #define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V  0x1
1675 #define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S  8
1676 /* SPI_MEM_ECC_ERR_INT_NUM : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
1677 /*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
1678 upt..*/
1679 #define SPI_MEM_ECC_ERR_INT_NUM    0x000000FF
1680 #define SPI_MEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S))
1681 #define SPI_MEM_ECC_ERR_INT_NUM_V  0xFF
1682 #define SPI_MEM_ECC_ERR_INT_NUM_S  0
1683 
1684 #define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD0)
1685 /* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[31:0] ;default: 32'h0 ; */
1686 /*description: These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SP
1687 I_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte e
1688 rror and data error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/
1689 #define SPI_MEM_ECC_ERR_ADDR    0xFFFFFFFF
1690 #define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
1691 #define SPI_MEM_ECC_ERR_ADDR_V  0xFFFFFFFF
1692 #define SPI_MEM_ECC_ERR_ADDR_S  0
1693 
1694 #define SPI_MEM_ECC_ERR_BIT_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
1695 /* SPI_MEM_ECC_ERR_CNT : RO ;bitpos:[24:17] ;default: 8'd0 ; */
1696 /*description: This bits show the error times of MSPI ECC read, including ECC byte error and da
1697 ta byte error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/
1698 #define SPI_MEM_ECC_ERR_CNT    0x000000FF
1699 #define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
1700 #define SPI_MEM_ECC_ERR_CNT_V  0xFF
1701 #define SPI_MEM_ECC_ERR_CNT_S  17
1702 /* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0 ; */
1703 /*description: It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ER
1704 R_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_
1705 INT_CLR bit..*/
1706 #define SPI_MEM_ECC_BYTE_ERR    (BIT(16))
1707 #define SPI_MEM_ECC_BYTE_ERR_M  (BIT(16))
1708 #define SPI_MEM_ECC_BYTE_ERR_V  0x1
1709 #define SPI_MEM_ECC_BYTE_ERR_S  16
1710 /* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */
1711 /*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC by
1712 te..*/
1713 #define SPI_MEM_ECC_CHK_ERR_BIT    0x00000007
1714 #define SPI_MEM_ECC_CHK_ERR_BIT_M  ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S))
1715 #define SPI_MEM_ECC_CHK_ERR_BIT_V  0x7
1716 #define SPI_MEM_ECC_CHK_ERR_BIT_S  13
1717 /* SPI_MEM_ECC_DATA_ERR_BIT : R/SS/WTC ;bitpos:[12:6] ;default: 7'd0 ; */
1718 /*description: It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_
1719 SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from
1720 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_ME
1721 M_ECC_ERR_INT_CLR bit..*/
1722 #define SPI_MEM_ECC_DATA_ERR_BIT    0x0000007F
1723 #define SPI_MEM_ECC_DATA_ERR_BIT_M  ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S))
1724 #define SPI_MEM_ECC_DATA_ERR_BIT_V  0x7F
1725 #define SPI_MEM_ECC_DATA_ERR_BIT_S  6
1726 
1727 #define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0xDC)
1728 /* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
1729 /*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
1730 sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
1731 SPI core clock cycles..*/
1732 #define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY    0x0000003F
1733 #define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S))
1734 #define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V  0x3F
1735 #define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S  25
1736 /* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
1737 /*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
1738 rnal RAM..*/
1739 #define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN    (BIT(24))
1740 #define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M  (BIT(24))
1741 #define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V  0x1
1742 #define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S  24
1743 /* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
1744 /*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse
1745 s to external RAM..*/
1746 #define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
1747 #define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
1748 #define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
1749 #define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
1750 /* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */
1751 /*description: 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner
1752  when accesses to external RAM..*/
1753 #define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
1754 #define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
1755 #define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
1756 #define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
1757 /* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
1758 /*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in
1759 ECC mode when accesses to external RAM..*/
1760 #define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
1761 #define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S))
1762 #define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
1763 #define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S  12
1764 /* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */
1765 /*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh
1766 ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME
1767 M_CS_HOLD bit..*/
1768 #define SPI_MEM_SPI_SMEM_CS_HOLD_TIME    0x0000001F
1769 #define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S))
1770 #define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V  0x1F
1771 #define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S  7
1772 /* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */
1773 /*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits
1774 are combined with SPI_MEM_CS_SETUP bit..*/
1775 #define SPI_MEM_SPI_SMEM_CS_SETUP_TIME    0x0000001F
1776 #define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S))
1777 #define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V  0x1F
1778 #define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S  2
1779 /* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
1780 /*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/
1781 #define SPI_MEM_SPI_SMEM_CS_HOLD    (BIT(1))
1782 #define SPI_MEM_SPI_SMEM_CS_HOLD_M  (BIT(1))
1783 #define SPI_MEM_SPI_SMEM_CS_HOLD_V  0x1
1784 #define SPI_MEM_SPI_SMEM_CS_HOLD_S  1
1785 /* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
1786 /*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
1787 #define SPI_MEM_SPI_SMEM_CS_SETUP    (BIT(0))
1788 #define SPI_MEM_SPI_SMEM_CS_SETUP_M  (BIT(0))
1789 #define SPI_MEM_SPI_SMEM_CS_SETUP_V  0x1
1790 #define SPI_MEM_SPI_SMEM_CS_SETUP_S  0
1791 
1792 #define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE0)
1793 /* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
1794 /*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
1795 ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
1796 #define SPI_MEM_SPI_FMEM_HYPERBUS_CA    (BIT(30))
1797 #define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M  (BIT(30))
1798 #define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V  0x1
1799 #define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S  30
1800 /* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
1801 /*description: Set this bit to enable octa_ram address out when accesses to flash, which means
1802 ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
1803 ..*/
1804 #define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
1805 #define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
1806 #define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V  0x1
1807 #define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S  29
1808 /* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
1809 /*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
1810 #define SPI_MEM_SPI_FMEM_CLK_DIFF_INV    (BIT(28))
1811 #define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
1812 #define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V  0x1
1813 #define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S  28
1814 /* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
1815 /*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
1816 ccesses flash or SPI1 accesses flash or sram..*/
1817 #define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
1818 #define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
1819 #define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
1820 #define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
1821 /* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
1822 /*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
1823 ..*/
1824 #define SPI_MEM_SPI_FMEM_DQS_CA_IN    (BIT(26))
1825 #define SPI_MEM_SPI_FMEM_DQS_CA_IN_M  (BIT(26))
1826 #define SPI_MEM_SPI_FMEM_DQS_CA_IN_V  0x1
1827 #define SPI_MEM_SPI_FMEM_DQS_CA_IN_S  26
1828 /* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */
1829 /*description: Set this bit to enable the SPI HyperBus mode..*/
1830 #define SPI_MEM_SPI_FMEM_HYPERBUS_MODE    (BIT(25))
1831 #define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M  (BIT(25))
1832 #define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V  0x1
1833 #define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S  25
1834 /* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
1835 /*description: Set this bit to enable the differential SPI_CLK#..*/
1836 #define SPI_MEM_SPI_FMEM_CLK_DIFF_EN    (BIT(24))
1837 #define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
1838 #define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V  0x1
1839 #define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S  24
1840 /* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
1841 /*description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK
1842  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is
1843  not active..*/
1844 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE    (BIT(22))
1845 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M  (BIT(22))
1846 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V  0x1
1847 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S  22
1848 /* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
1849 /*description: 1: Use internal signal  as data strobe, the strobe can not be delayed by input t
1850 iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca
1851 n be delayed by input timing module.*/
1852 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
1853 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
1854 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V  0x1
1855 #define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S  21
1856 /* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
1857 /*description: The delay number of data strobe which from memory based on SPI_CLK..*/
1858 #define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD    0x0000007F
1859 #define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S))
1860 #define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V  0x7F
1861 #define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S  14
1862 /* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
1863 /*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when
1864 accesses to flash..*/
1865 #define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
1866 #define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
1867 #define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V  0x1
1868 #define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S  13
1869 /* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
1870 /*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when
1871  accesses to flash..*/
1872 #define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
1873 #define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
1874 #define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V  0x1
1875 #define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S  12
1876 /* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
1877 /*description: It is the minimum output data length in the panda device..*/
1878 #define SPI_MEM_SPI_FMEM_OUTMINBYTELEN    0x0000007F
1879 #define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S))
1880 #define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V  0x7F
1881 #define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S  5
1882 /* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
1883 /*description: the bit is used to disable dual edge in command phase when DDR mode..*/
1884 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS    (BIT(4))
1885 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
1886 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V  0x1
1887 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S  4
1888 /* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
1889 /*description: Set the bit to reorder TX data of the word in DDR mode..*/
1890 #define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
1891 #define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
1892 #define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V  0x1
1893 #define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S  3
1894 /* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
1895 /*description: Set the bit to reorder RX data of the word in DDR mode..*/
1896 #define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
1897 #define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
1898 #define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V  0x1
1899 #define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S  2
1900 /* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
1901 /*description: Set the bit to enable variable dummy cycle in DDRmode..*/
1902 #define SPI_MEM_SPI_FMEM_VAR_DUMMY    (BIT(1))
1903 #define SPI_MEM_SPI_FMEM_VAR_DUMMY_M  (BIT(1))
1904 #define SPI_MEM_SPI_FMEM_VAR_DUMMY_V  0x1
1905 #define SPI_MEM_SPI_FMEM_VAR_DUMMY_S  1
1906 /* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
1907 /*description: 1: in DDR mode,  0: in SDR mode..*/
1908 #define SPI_MEM_SPI_FMEM_DDR_EN    (BIT(0))
1909 #define SPI_MEM_SPI_FMEM_DDR_EN_M  (BIT(0))
1910 #define SPI_MEM_SPI_FMEM_DDR_EN_V  0x1
1911 #define SPI_MEM_SPI_FMEM_DDR_EN_S  0
1912 
1913 #define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE4)
1914 /* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
1915 /*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
1916  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
1917 ]}..*/
1918 #define SPI_MEM_SPI_SMEM_HYPERBUS_CA    (BIT(30))
1919 #define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M  (BIT(30))
1920 #define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V  0x1
1921 #define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S  30
1922 /* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
1923 /*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
1924  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
1925 , 1'b0}..*/
1926 #define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
1927 #define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
1928 #define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V  0x1
1929 #define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S  29
1930 /* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
1931 /*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
1932 #define SPI_MEM_SPI_SMEM_CLK_DIFF_INV    (BIT(28))
1933 #define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
1934 #define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V  0x1
1935 #define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S  28
1936 /* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
1937 /*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
1938 ccesses to flash or SPI1 accesses flash or sram..*/
1939 #define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
1940 #define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
1941 #define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
1942 #define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
1943 /* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
1944 /*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
1945 ..*/
1946 #define SPI_MEM_SPI_SMEM_DQS_CA_IN    (BIT(26))
1947 #define SPI_MEM_SPI_SMEM_DQS_CA_IN_M  (BIT(26))
1948 #define SPI_MEM_SPI_SMEM_DQS_CA_IN_V  0x1
1949 #define SPI_MEM_SPI_SMEM_DQS_CA_IN_S  26
1950 /* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */
1951 /*description: Set this bit to enable the SPI HyperBus mode..*/
1952 #define SPI_MEM_SPI_SMEM_HYPERBUS_MODE    (BIT(25))
1953 #define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M  (BIT(25))
1954 #define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V  0x1
1955 #define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S  25
1956 /* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
1957 /*description: Set this bit to enable the differential SPI_CLK#..*/
1958 #define SPI_MEM_SPI_SMEM_CLK_DIFF_EN    (BIT(24))
1959 #define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
1960 #define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V  0x1
1961 #define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S  24
1962 /* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
1963 /*description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK
1964  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is
1965  not active..*/
1966 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE    (BIT(22))
1967 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M  (BIT(22))
1968 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V  0x1
1969 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S  22
1970 /* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
1971 /*description: 1: Use internal signal  as data strobe, the strobe can not be delayed by input t
1972 iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca
1973 n be delayed by input timing module.*/
1974 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
1975 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
1976 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V  0x1
1977 #define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S  21
1978 /* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
1979 /*description: The delay number of data strobe which from memory based on SPI_CLK..*/
1980 #define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD    0x0000007F
1981 #define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S))
1982 #define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V  0x7F
1983 #define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S  14
1984 /* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
1985 /*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when
1986 accesses to external RAM..*/
1987 #define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
1988 #define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
1989 #define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V  0x1
1990 #define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S  13
1991 /* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
1992 /*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when
1993  accesses to external RAM..*/
1994 #define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
1995 #define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
1996 #define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V  0x1
1997 #define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S  12
1998 /* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
1999 /*description: It is the minimum output data length in the ddr psram..*/
2000 #define SPI_MEM_SPI_SMEM_OUTMINBYTELEN    0x0000007F
2001 #define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S))
2002 #define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V  0x7F
2003 #define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S  5
2004 /* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
2005 /*description: the bit is used to disable dual edge in CMD phase when ddr mode..*/
2006 #define SPI_MEM_SPI_SMEM_DDR_CMD_DIS    (BIT(4))
2007 #define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
2008 #define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V  0x1
2009 #define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S  4
2010 /* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
2011 /*description: Set the bit to reorder tx data of the word in spi ddr mode..*/
2012 #define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
2013 #define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
2014 #define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V  0x1
2015 #define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S  3
2016 /* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
2017 /*description: Set the bit to reorder rx data of the word in spi ddr mode..*/
2018 #define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
2019 #define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
2020 #define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V  0x1
2021 #define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S  2
2022 /* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
2023 /*description: Set the bit to enable variable dummy cycle in spi ddr mode..*/
2024 #define SPI_MEM_SPI_SMEM_VAR_DUMMY    (BIT(1))
2025 #define SPI_MEM_SPI_SMEM_VAR_DUMMY_M  (BIT(1))
2026 #define SPI_MEM_SPI_SMEM_VAR_DUMMY_V  0x1
2027 #define SPI_MEM_SPI_SMEM_VAR_DUMMY_S  1
2028 /* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
2029 /*description: 1: in ddr mode,  0 in sdr mode.*/
2030 #define SPI_MEM_SPI_SMEM_DDR_EN    (BIT(0))
2031 #define SPI_MEM_SPI_SMEM_DDR_EN_M  (BIT(0))
2032 #define SPI_MEM_SPI_SMEM_DDR_EN_V  0x1
2033 #define SPI_MEM_SPI_SMEM_DDR_EN_S  0
2034 
2035 #define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE8)
2036 /* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
2037 /*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
2038 #define SPI_MEM_CLK_EN    (BIT(0))
2039 #define SPI_MEM_CLK_EN_M  (BIT(0))
2040 #define SPI_MEM_CLK_EN_V  0x1
2041 #define SPI_MEM_CLK_EN_S  0
2042 
2043 #define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xEC)
2044 /* SPI_MEM_CORE_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
2045 /*description: When the digital system clock selects PLL clock and the frequency of PLL clock i
2046 s 480MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: SPI0/1 module clock (MSPI_CORE_
2047 CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz.  2: MSPI_CORE_CLK is 160MHz. 3: MSPI_
2048 CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the freq
2049 uency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: MSPI_CORE_C
2050 LK is 80MHz. 1: MSPI_CORE_CLK is 80MHz.  2: MSPI_CORE_CLK 160MHz. 3: Not used. .*/
2051 #define SPI_MEM_CORE_CLK_SEL    0x00000003
2052 #define SPI_MEM_CORE_CLK_SEL_M  ((SPI_MEM_CORE_CLK_SEL_V)<<(SPI_MEM_CORE_CLK_SEL_S))
2053 #define SPI_MEM_CORE_CLK_SEL_V  0x3
2054 #define SPI_MEM_CORE_CLK_SEL_S  0
2055 
2056 #define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF0)
2057 /* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
2058 /*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
2059 #define SPI_MEM_ECC_ERR_INT_ENA    (BIT(4))
2060 #define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(4))
2061 #define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
2062 #define SPI_MEM_ECC_ERR_INT_ENA_S  4
2063 /* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
2064 /*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
2065 #define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(3))
2066 #define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(3))
2067 #define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
2068 #define SPI_MEM_BROWN_OUT_INT_ENA_S  3
2069 /* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
2070 /*description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
2071 #define SPI_MEM_TOTAL_TRANS_END_INT_ENA    (BIT(2))
2072 #define SPI_MEM_TOTAL_TRANS_END_INT_ENA_M  (BIT(2))
2073 #define SPI_MEM_TOTAL_TRANS_END_INT_ENA_V  0x1
2074 #define SPI_MEM_TOTAL_TRANS_END_INT_ENA_S  2
2075 /* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
2076 /*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
2077 #define SPI_MEM_PES_END_INT_ENA    (BIT(1))
2078 #define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
2079 #define SPI_MEM_PES_END_INT_ENA_V  0x1
2080 #define SPI_MEM_PES_END_INT_ENA_S  1
2081 /* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
2082 /*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
2083 #define SPI_MEM_PER_END_INT_ENA    (BIT(0))
2084 #define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
2085 #define SPI_MEM_PER_END_INT_ENA_V  0x1
2086 #define SPI_MEM_PER_END_INT_ENA_S  0
2087 
2088 #define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF4)
2089 /* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
2090 /*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_ME
2091 M_ECC_ERR_CNT will be cleared by the pulse of this bit..*/
2092 #define SPI_MEM_ECC_ERR_INT_CLR    (BIT(4))
2093 #define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(4))
2094 #define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
2095 #define SPI_MEM_ECC_ERR_INT_CLR_S  4
2096 /* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
2097 /*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
2098 #define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(3))
2099 #define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(3))
2100 #define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
2101 #define SPI_MEM_BROWN_OUT_INT_CLR_S  3
2102 /* SPI_MEM_TOTAL_TRANS_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
2103 /*description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
2104 #define SPI_MEM_TOTAL_TRANS_END_INT_CLR    (BIT(2))
2105 #define SPI_MEM_TOTAL_TRANS_END_INT_CLR_M  (BIT(2))
2106 #define SPI_MEM_TOTAL_TRANS_END_INT_CLR_V  0x1
2107 #define SPI_MEM_TOTAL_TRANS_END_INT_CLR_S  2
2108 /* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
2109 /*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
2110 #define SPI_MEM_PES_END_INT_CLR    (BIT(1))
2111 #define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
2112 #define SPI_MEM_PES_END_INT_CLR_V  0x1
2113 #define SPI_MEM_PES_END_INT_CLR_S  1
2114 /* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
2115 /*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
2116 #define SPI_MEM_PER_END_INT_CLR    (BIT(0))
2117 #define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
2118 #define SPI_MEM_PER_END_INT_CLR_V  0x1
2119 #define SPI_MEM_PER_END_INT_CLR_S  0
2120 
2121 #define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF8)
2122 /* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
2123 /*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is
2124 set and  APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the err
2125 or times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_
2126 NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and  APB_CTRL_SECC_ERR_INT_EN is s
2127 et, this bit is triggered when the error times of SPI0/1 ECC read external RAM a
2128 re equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN
2129 and  APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total erro
2130 r times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_C
2131 TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN
2132  are cleared, this bit will not be triggered..*/
2133 #define SPI_MEM_ECC_ERR_INT_RAW    (BIT(4))
2134 #define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(4))
2135 #define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
2136 #define SPI_MEM_ECC_ERR_INT_RAW_S  4
2137 /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
2138 /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
2139 chip is loosing power and RTC module sends out brown out close flash request to
2140 SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
2141  and MSPI returns to idle state. 0: Others..*/
2142 #define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(3))
2143 #define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(3))
2144 #define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
2145 #define SPI_MEM_BROWN_OUT_INT_RAW_S  3
2146 /* SPI_MEM_TOTAL_TRANS_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
2147 /*description: The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 tr
2148 ansfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/
2149 PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success.  0: Other
2150 s..*/
2151 #define SPI_MEM_TOTAL_TRANS_END_INT_RAW    (BIT(2))
2152 #define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M  (BIT(2))
2153 #define SPI_MEM_TOTAL_TRANS_END_INT_RAW_V  0x1
2154 #define SPI_MEM_TOTAL_TRANS_END_INT_RAW_S  2
2155 /* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
2156 /*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
2157 mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
2158 #define SPI_MEM_PES_END_INT_RAW    (BIT(1))
2159 #define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
2160 #define SPI_MEM_PES_END_INT_RAW_V  0x1
2161 #define SPI_MEM_PES_END_INT_RAW_S  1
2162 /* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
2163 /*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
2164 mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
2165 #define SPI_MEM_PER_END_INT_RAW    (BIT(0))
2166 #define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
2167 #define SPI_MEM_PER_END_INT_RAW_V  0x1
2168 #define SPI_MEM_PER_END_INT_RAW_S  0
2169 
2170 #define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xFC)
2171 /* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
2172 /*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
2173 #define SPI_MEM_ECC_ERR_INT_ST    (BIT(4))
2174 #define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(4))
2175 #define SPI_MEM_ECC_ERR_INT_ST_V  0x1
2176 #define SPI_MEM_ECC_ERR_INT_ST_S  4
2177 /* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
2178 /*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
2179 #define SPI_MEM_BROWN_OUT_INT_ST    (BIT(3))
2180 #define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(3))
2181 #define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
2182 #define SPI_MEM_BROWN_OUT_INT_ST_S  3
2183 /* SPI_MEM_TOTAL_TRANS_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
2184 /*description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
2185 #define SPI_MEM_TOTAL_TRANS_END_INT_ST    (BIT(2))
2186 #define SPI_MEM_TOTAL_TRANS_END_INT_ST_M  (BIT(2))
2187 #define SPI_MEM_TOTAL_TRANS_END_INT_ST_V  0x1
2188 #define SPI_MEM_TOTAL_TRANS_END_INT_ST_S  2
2189 /* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
2190 /*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
2191 #define SPI_MEM_PES_END_INT_ST    (BIT(1))
2192 #define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
2193 #define SPI_MEM_PES_END_INT_ST_V  0x1
2194 #define SPI_MEM_PES_END_INT_ST_S  1
2195 /* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
2196 /*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
2197 #define SPI_MEM_PER_END_INT_ST    (BIT(0))
2198 #define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
2199 #define SPI_MEM_PER_END_INT_ST_V  0x1
2200 #define SPI_MEM_PER_END_INT_ST_S  0
2201 
2202 #define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
2203 /* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */
2204 /*description: SPI register version..*/
2205 #define SPI_MEM_DATE    0x007FFFFF
2206 #define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
2207 #define SPI_MEM_DATE_V  0x7FFFFF
2208 #define SPI_MEM_DATE_S  5
2209 /* SPI_MEM_SPICLK_PAD_DRV_CTL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
2210 /*description: SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled b
2211 y the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The
2212  driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK
2213  PAD..*/
2214 #define SPI_MEM_SPICLK_PAD_DRV_CTL_EN    (BIT(4))
2215 #define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M  (BIT(4))
2216 #define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V  0x1
2217 #define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S  4
2218 /* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
2219 /*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0
2220 ] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash..*/
2221 #define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV    0x00000003
2222 #define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S))
2223 #define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V  0x3
2224 #define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S  2
2225 /* SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
2226 /*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0
2227 ] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RA
2228 M..*/
2229 #define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV    0x00000003
2230 #define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S))
2231 #define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V  0x3
2232 #define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S  0
2233 
2234 
2235 #ifdef __cplusplus
2236 }
2237 #endif
2238 
2239 
2240 
2241 #endif /*_SOC_SPI_MEM_REG_H_ */
2242