1 /* 2 * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_SPI_REG_H_ 7 #define _SOC_SPI_REG_H_ 8 9 #include "soc.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) 16 /* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ 17 /*description: User define command enable. An operation will be triggered when 18 the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ 19 #define SPI_USR (BIT(24)) 20 #define SPI_USR_M (BIT(24)) 21 #define SPI_USR_V 0x1 22 #define SPI_USR_S 24 23 /* SPI_CONF_BITLEN : R/W ;bitpos:[22:0] ;default: 23'd0 ; */ 24 /*description: Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/ 25 #define SPI_CONF_BITLEN 0x007FFFFF 26 #define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S)) 27 #define SPI_CONF_BITLEN_V 0x7FFFFF 28 #define SPI_CONF_BITLEN_S 0 29 30 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x004) 31 /* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 32 /*description: [31:8]:address to slave [7:0]:Reserved. Can be configured in CONF state.*/ 33 #define SPI_USR_ADDR_VALUE 0xFFFFFFFF 34 #define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S)) 35 #define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF 36 #define SPI_USR_ADDR_VALUE_S 0 37 38 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008) 39 /* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ 40 /*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB 41 first. Can be configured in CONF state.*/ 42 #define SPI_WR_BIT_ORDER (BIT(26)) 43 #define SPI_WR_BIT_ORDER_M (BIT(26)) 44 #define SPI_WR_BIT_ORDER_V 0x1 45 #define SPI_WR_BIT_ORDER_S 26 46 /* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ 47 /*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured 48 in CONF state.*/ 49 #define SPI_RD_BIT_ORDER (BIT(25)) 50 #define SPI_RD_BIT_ORDER_M (BIT(25)) 51 #define SPI_RD_BIT_ORDER_V 0x1 52 #define SPI_RD_BIT_ORDER_S 25 53 /* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ 54 /*description: Write protect signal output when SPI is idle. 1: output high 55 0: output low. Can be configured in CONF state.*/ 56 #define SPI_WP_REG (BIT(21)) 57 #define SPI_WP_REG_M (BIT(21)) 58 #define SPI_WP_REG_V 0x1 59 #define SPI_WP_REG_S 21 60 /* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ 61 /*description: The bit is used to set MOSI line polarity 1: high 0 low. Can 62 be configured in CONF state.*/ 63 #define SPI_D_POL (BIT(19)) 64 #define SPI_D_POL_M (BIT(19)) 65 #define SPI_D_POL_V 0x1 66 #define SPI_D_POL_S 19 67 /* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ 68 /*description: The bit is used to set MISO line polarity 1: high 0 low. Can 69 be configured in CONF state.*/ 70 #define SPI_Q_POL (BIT(18)) 71 #define SPI_Q_POL_M (BIT(18)) 72 #define SPI_Q_POL_V 0x1 73 #define SPI_Q_POL_S 18 74 /* SPI_FREAD_OCT : R/W ;bitpos:[16] ;default: 1'b0 ; */ 75 /*description: In the read operations read-data phase apply 8 signals. 1: enable 76 0: disable. Can be configured in CONF state.*/ 77 #define SPI_FREAD_OCT (BIT(16)) 78 #define SPI_FREAD_OCT_M (BIT(16)) 79 #define SPI_FREAD_OCT_V 0x1 80 #define SPI_FREAD_OCT_S 16 81 /* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 82 /*description: In the read operations read-data phase apply 4 signals. 1: enable 83 0: disable. Can be configured in CONF state.*/ 84 #define SPI_FREAD_QUAD (BIT(15)) 85 #define SPI_FREAD_QUAD_M (BIT(15)) 86 #define SPI_FREAD_QUAD_V 0x1 87 #define SPI_FREAD_QUAD_S 15 88 /* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ 89 /*description: In the read operations read-data phase apply 2 signals. 1: enable 90 0: disable. Can be configured in CONF state.*/ 91 #define SPI_FREAD_DUAL (BIT(14)) 92 #define SPI_FREAD_DUAL_M (BIT(14)) 93 #define SPI_FREAD_DUAL_V 0x1 94 #define SPI_FREAD_DUAL_S 14 95 /* SPI_FCMD_OCT : R/W ;bitpos:[10] ;default: 1'b0 ; */ 96 /*description: Apply 8 signals during command phase 1:enable 0: disable. Can 97 be configured in CONF state.*/ 98 #define SPI_FCMD_OCT (BIT(10)) 99 #define SPI_FCMD_OCT_M (BIT(10)) 100 #define SPI_FCMD_OCT_V 0x1 101 #define SPI_FCMD_OCT_S 10 102 /* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */ 103 /*description: Apply 4 signals during command phase 1:enable 0: disable. Can 104 be configured in CONF state.*/ 105 #define SPI_FCMD_QUAD (BIT(9)) 106 #define SPI_FCMD_QUAD_M (BIT(9)) 107 #define SPI_FCMD_QUAD_V 0x1 108 #define SPI_FCMD_QUAD_S 9 109 /* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */ 110 /*description: Apply 2 signals during command phase 1:enable 0: disable. Can 111 be configured in CONF state.*/ 112 #define SPI_FCMD_DUAL (BIT(8)) 113 #define SPI_FCMD_DUAL_M (BIT(8)) 114 #define SPI_FCMD_DUAL_V 0x1 115 #define SPI_FCMD_DUAL_S 8 116 /* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */ 117 /*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be 118 configured in CONF state.*/ 119 #define SPI_FADDR_OCT (BIT(7)) 120 #define SPI_FADDR_OCT_M (BIT(7)) 121 #define SPI_FADDR_OCT_V 0x1 122 #define SPI_FADDR_OCT_S 7 123 /* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 124 /*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be 125 configured in CONF state.*/ 126 #define SPI_FADDR_QUAD (BIT(6)) 127 #define SPI_FADDR_QUAD_M (BIT(6)) 128 #define SPI_FADDR_QUAD_V 0x1 129 #define SPI_FADDR_QUAD_S 6 130 /* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ 131 /*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be 132 configured in CONF state.*/ 133 #define SPI_FADDR_DUAL (BIT(5)) 134 #define SPI_FADDR_DUAL_M (BIT(5)) 135 #define SPI_FADDR_DUAL_V 0x1 136 #define SPI_FADDR_DUAL_S 5 137 /* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ 138 /*description: In the dummy phase the signal level of spi is output by the spi 139 controller. Can be configured in CONF state.*/ 140 #define SPI_DUMMY_OUT (BIT(3)) 141 #define SPI_DUMMY_OUT_M (BIT(3)) 142 #define SPI_DUMMY_OUT_V 0x1 143 #define SPI_DUMMY_OUT_S 3 144 /* SPI_EXT_HOLD_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 145 /*description: Set the bit to hold spi. The bit is combined with spi_usr_prep_hold 146 spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol. Can be configured in CONF state.*/ 147 #define SPI_EXT_HOLD_EN (BIT(2)) 148 #define SPI_EXT_HOLD_EN_M (BIT(2)) 149 #define SPI_EXT_HOLD_EN_V 0x1 150 #define SPI_EXT_HOLD_EN_S 2 151 152 #define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x00C) 153 /* SPI_CS_HOLD_DELAY : R/W ;bitpos:[19:14] ;default: 6'h1 ; */ 154 /*description: SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.*/ 155 #define SPI_CS_HOLD_DELAY 0x0000003F 156 #define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) 157 #define SPI_CS_HOLD_DELAY_V 0x3F 158 #define SPI_CS_HOLD_DELAY_S 14 159 /* SPI_W16_17_WR_ENA : R/W ;bitpos:[4] ;default: 1'h1 ; */ 160 /*description: 1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not 161 be written. Can be configured in CONF state.*/ 162 #define SPI_W16_17_WR_ENA (BIT(4)) 163 #define SPI_W16_17_WR_ENA_M (BIT(4)) 164 #define SPI_W16_17_WR_ENA_V 0x1 165 #define SPI_W16_17_WR_ENA_S 4 166 /* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'h0 ; */ 167 /*description: It saves half a cycle when tsck is the same as rsck. 1: output 168 data at rsck posedge 0: output data at tsck posedge*/ 169 #define SPI_RSCK_DATA_OUT (BIT(3)) 170 #define SPI_RSCK_DATA_OUT_M (BIT(3)) 171 #define SPI_RSCK_DATA_OUT_V 0x1 172 #define SPI_RSCK_DATA_OUT_S 3 173 /* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 174 /*description: {CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output 175 data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ 176 #define SPI_CLK_MODE_13 (BIT(2)) 177 #define SPI_CLK_MODE_13_M (BIT(2)) 178 #define SPI_CLK_MODE_13_V 0x1 179 #define SPI_CLK_MODE_13_S 2 180 /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 181 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: 182 SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ 183 #define SPI_CLK_MODE 0x00000003 184 #define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) 185 #define SPI_CLK_MODE_V 0x3 186 #define SPI_CLK_MODE_S 0 187 188 #define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x010) 189 /* SPI_CS_DELAY_NUM : R/W ;bitpos:[30:29] ;default: 2'h0 ; */ 190 /*description: spi_cs signal is delayed by system clock cycles. Can be configured 191 in CONF state.*/ 192 #define SPI_CS_DELAY_NUM 0x00000003 193 #define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) 194 #define SPI_CS_DELAY_NUM_V 0x3 195 #define SPI_CS_DELAY_NUM_S 29 196 /* SPI_CS_DELAY_MODE : R/W ;bitpos:[28:26] ;default: 3'h0 ; */ 197 /*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge 198 or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state.*/ 199 #define SPI_CS_DELAY_MODE 0x00000007 200 #define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) 201 #define SPI_CS_DELAY_MODE_V 0x7 202 #define SPI_CS_DELAY_MODE_S 26 203 /* SPI_CS_HOLD_TIME : R/W ;bitpos:[25:13] ;default: 13'h1 ; */ 204 /*description: delay cycles of cs pin by spi clock this bits are combined with 205 spi_cs_hold bit. Can be configured in CONF state.*/ 206 #define SPI_CS_HOLD_TIME 0x00001FFF 207 #define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S)) 208 #define SPI_CS_HOLD_TIME_V 0x1FFF 209 #define SPI_CS_HOLD_TIME_S 13 210 /* SPI_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h0 ; */ 211 /*description: (cycles+1) of prepare phase by spi clock this bits are combined 212 with spi_cs_setup bit. Can be configured in CONF state.*/ 213 #define SPI_CS_SETUP_TIME 0x00001FFF 214 #define SPI_CS_SETUP_TIME_M ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S)) 215 #define SPI_CS_SETUP_TIME_V 0x1FFF 216 #define SPI_CS_SETUP_TIME_S 0 217 218 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x014) 219 /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ 220 /*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is 221 divided from system clock. Can be configured in CONF state.*/ 222 #define SPI_CLK_EQU_SYSCLK (BIT(31)) 223 #define SPI_CLK_EQU_SYSCLK_M (BIT(31)) 224 #define SPI_CLK_EQU_SYSCLK_V 0x1 225 #define SPI_CLK_EQU_SYSCLK_S 31 226 /* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ 227 /*description: In the master mode it is pre-divider of spi_clk. Can be configured 228 in CONF state.*/ 229 #define SPI_CLKDIV_PRE 0x00001FFF 230 #define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) 231 #define SPI_CLKDIV_PRE_V 0x1FFF 232 #define SPI_CLKDIV_PRE_S 18 233 /* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ 234 /*description: In the master mode it is the divider of spi_clk. So spi_clk frequency 235 is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ 236 #define SPI_CLKCNT_N 0x0000003F 237 #define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) 238 #define SPI_CLKCNT_N_V 0x3F 239 #define SPI_CLKCNT_N_S 12 240 /* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ 241 /*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In 242 the slave mode it must be 0. Can be configured in CONF state.*/ 243 #define SPI_CLKCNT_H 0x0000003F 244 #define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) 245 #define SPI_CLKCNT_H_V 0x3F 246 #define SPI_CLKCNT_H_S 6 247 /* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ 248 /*description: In the master mode it must be equal to spi_clkcnt_N. In the slave 249 mode it must be 0. Can be configured in CONF state.*/ 250 #define SPI_CLKCNT_L 0x0000003F 251 #define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) 252 #define SPI_CLKCNT_L_V 0x3F 253 #define SPI_CLKCNT_L_S 0 254 255 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x018) 256 /* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ 257 /*description: This bit enable the command phase of an operation. Can be configured 258 in CONF state.*/ 259 #define SPI_USR_COMMAND (BIT(31)) 260 #define SPI_USR_COMMAND_M (BIT(31)) 261 #define SPI_USR_COMMAND_V 0x1 262 #define SPI_USR_COMMAND_S 31 263 /* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ 264 /*description: This bit enable the address phase of an operation. Can be configured 265 in CONF state.*/ 266 #define SPI_USR_ADDR (BIT(30)) 267 #define SPI_USR_ADDR_M (BIT(30)) 268 #define SPI_USR_ADDR_V 0x1 269 #define SPI_USR_ADDR_S 30 270 /* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ 271 /*description: This bit enable the dummy phase of an operation. Can be configured 272 in CONF state.*/ 273 #define SPI_USR_DUMMY (BIT(29)) 274 #define SPI_USR_DUMMY_M (BIT(29)) 275 #define SPI_USR_DUMMY_V 0x1 276 #define SPI_USR_DUMMY_S 29 277 /* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ 278 /*description: This bit enable the read-data phase of an operation. Can be configured 279 in CONF state.*/ 280 #define SPI_USR_MISO (BIT(28)) 281 #define SPI_USR_MISO_M (BIT(28)) 282 #define SPI_USR_MISO_V 0x1 283 #define SPI_USR_MISO_S 28 284 /* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ 285 /*description: This bit enable the write-data phase of an operation. Can be 286 configured in CONF state.*/ 287 #define SPI_USR_MOSI (BIT(27)) 288 #define SPI_USR_MOSI_M (BIT(27)) 289 #define SPI_USR_MOSI_V 0x1 290 #define SPI_USR_MOSI_S 27 291 /* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 292 /*description: spi clock is disable in dummy phase when the bit is enable. Can 293 be configured in CONF state.*/ 294 #define SPI_USR_DUMMY_IDLE (BIT(26)) 295 #define SPI_USR_DUMMY_IDLE_M (BIT(26)) 296 #define SPI_USR_DUMMY_IDLE_V 0x1 297 #define SPI_USR_DUMMY_IDLE_S 26 298 /* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ 299 /*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 300 1: enable 0: disable. Can be configured in CONF state.*/ 301 #define SPI_USR_MOSI_HIGHPART (BIT(25)) 302 #define SPI_USR_MOSI_HIGHPART_M (BIT(25)) 303 #define SPI_USR_MOSI_HIGHPART_V 0x1 304 #define SPI_USR_MOSI_HIGHPART_S 25 305 /* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ 306 /*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 307 1: enable 0: disable. Can be configured in CONF state.*/ 308 #define SPI_USR_MISO_HIGHPART (BIT(24)) 309 #define SPI_USR_MISO_HIGHPART_M (BIT(24)) 310 #define SPI_USR_MISO_HIGHPART_V 0x1 311 #define SPI_USR_MISO_HIGHPART_S 24 312 /* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ 313 /*description: spi is hold at prepare state the bit are combined with spi_usr_hold_pol 314 bit. Can be configured in CONF state.*/ 315 #define SPI_USR_PREP_HOLD (BIT(23)) 316 #define SPI_USR_PREP_HOLD_M (BIT(23)) 317 #define SPI_USR_PREP_HOLD_V 0x1 318 #define SPI_USR_PREP_HOLD_S 23 319 /* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ 320 /*description: spi is hold at command state the bit are combined with spi_usr_hold_pol 321 bit. Can be configured in CONF state.*/ 322 #define SPI_USR_CMD_HOLD (BIT(22)) 323 #define SPI_USR_CMD_HOLD_M (BIT(22)) 324 #define SPI_USR_CMD_HOLD_V 0x1 325 #define SPI_USR_CMD_HOLD_S 22 326 /* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 327 /*description: spi is hold at address state the bit are combined with spi_usr_hold_pol 328 bit. Can be configured in CONF state.*/ 329 #define SPI_USR_ADDR_HOLD (BIT(21)) 330 #define SPI_USR_ADDR_HOLD_M (BIT(21)) 331 #define SPI_USR_ADDR_HOLD_V 0x1 332 #define SPI_USR_ADDR_HOLD_S 21 333 /* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ 334 /*description: spi is hold at dummy state the bit are combined with spi_usr_hold_pol 335 bit. Can be configured in CONF state.*/ 336 #define SPI_USR_DUMMY_HOLD (BIT(20)) 337 #define SPI_USR_DUMMY_HOLD_M (BIT(20)) 338 #define SPI_USR_DUMMY_HOLD_V 0x1 339 #define SPI_USR_DUMMY_HOLD_S 20 340 /* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 341 /*description: spi is hold at data in state the bit are combined with spi_usr_hold_pol 342 bit. Can be configured in CONF state.*/ 343 #define SPI_USR_DIN_HOLD (BIT(19)) 344 #define SPI_USR_DIN_HOLD_M (BIT(19)) 345 #define SPI_USR_DIN_HOLD_V 0x1 346 #define SPI_USR_DIN_HOLD_S 19 347 /* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ 348 /*description: spi is hold at data out state the bit are combined with spi_usr_hold_pol 349 bit. Can be configured in CONF state.*/ 350 #define SPI_USR_DOUT_HOLD (BIT(18)) 351 #define SPI_USR_DOUT_HOLD_M (BIT(18)) 352 #define SPI_USR_DOUT_HOLD_V 0x1 353 #define SPI_USR_DOUT_HOLD_S 18 354 /* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ 355 /*description: It is combined with hold bits to set the polarity of spi hold 356 line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state.*/ 357 #define SPI_USR_HOLD_POL (BIT(17)) 358 #define SPI_USR_HOLD_POL_M (BIT(17)) 359 #define SPI_USR_HOLD_POL_V 0x1 360 #define SPI_USR_HOLD_POL_S 17 361 /* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ 362 /*description: Set the bit to enable 3-line half duplex communication mosi and 363 miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ 364 #define SPI_SIO (BIT(16)) 365 #define SPI_SIO_M (BIT(16)) 366 #define SPI_SIO_V 0x1 367 #define SPI_SIO_S 16 368 /* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */ 369 /*description: 1: Enable the DMA CONF phase of next seg-trans operation which 370 means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ 371 #define SPI_USR_CONF_NXT (BIT(15)) 372 #define SPI_USR_CONF_NXT_M (BIT(15)) 373 #define SPI_USR_CONF_NXT_V 0x1 374 #define SPI_USR_CONF_NXT_S 15 375 /* SPI_FWRITE_OCT : R/W ;bitpos:[14] ;default: 1'b0 ; */ 376 /*description: In the write operations read-data phase apply 8 signals. Can 377 be configured in CONF state.*/ 378 #define SPI_FWRITE_OCT (BIT(14)) 379 #define SPI_FWRITE_OCT_M (BIT(14)) 380 #define SPI_FWRITE_OCT_V 0x1 381 #define SPI_FWRITE_OCT_S 14 382 /* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 383 /*description: In the write operations read-data phase apply 4 signals. Can 384 be configured in CONF state.*/ 385 #define SPI_FWRITE_QUAD (BIT(13)) 386 #define SPI_FWRITE_QUAD_M (BIT(13)) 387 #define SPI_FWRITE_QUAD_V 0x1 388 #define SPI_FWRITE_QUAD_S 13 389 /* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ 390 /*description: In the write operations read-data phase apply 2 signals. Can 391 be configured in CONF state.*/ 392 #define SPI_FWRITE_DUAL (BIT(12)) 393 #define SPI_FWRITE_DUAL_M (BIT(12)) 394 #define SPI_FWRITE_DUAL_V 0x1 395 #define SPI_FWRITE_DUAL_S 12 396 /* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ 397 /*description: In command address write-data (MOSI) phases 1: big-endian 0: 398 litte_endian. Can be configured in CONF state.*/ 399 #define SPI_WR_BYTE_ORDER (BIT(11)) 400 #define SPI_WR_BYTE_ORDER_M (BIT(11)) 401 #define SPI_WR_BYTE_ORDER_V 0x1 402 #define SPI_WR_BYTE_ORDER_S 11 403 /* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ 404 /*description: In read-data (MISO) phase 1: big-endian 0: little_endian. Can 405 be configured in CONF state.*/ 406 #define SPI_RD_BYTE_ORDER (BIT(10)) 407 #define SPI_RD_BYTE_ORDER_M (BIT(10)) 408 #define SPI_RD_BYTE_ORDER_V 0x1 409 #define SPI_RD_BYTE_ORDER_S 10 410 /* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 411 /*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal 412 delay mode. Can be configured in CONF state.*/ 413 #define SPI_CK_OUT_EDGE (BIT(9)) 414 #define SPI_CK_OUT_EDGE_M (BIT(9)) 415 #define SPI_CK_OUT_EDGE_V 0x1 416 #define SPI_CK_OUT_EDGE_S 9 417 /* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */ 418 /*description: In the slave mode this bit can be used to change the polarity 419 of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ 420 #define SPI_RSCK_I_EDGE (BIT(8)) 421 #define SPI_RSCK_I_EDGE_M (BIT(8)) 422 #define SPI_RSCK_I_EDGE_V 0x1 423 #define SPI_RSCK_I_EDGE_S 8 424 /* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */ 425 /*description: spi cs is enable when spi is in prepare phase. 1: enable 0: 426 disable. Can be configured in CONF state.*/ 427 #define SPI_CS_SETUP (BIT(7)) 428 #define SPI_CS_SETUP_M (BIT(7)) 429 #define SPI_CS_SETUP_V 0x1 430 #define SPI_CS_SETUP_S 7 431 /* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */ 432 /*description: spi cs keep low when spi is in done phase. 1: enable 0: disable. 433 Can be configured in CONF state.*/ 434 #define SPI_CS_HOLD (BIT(6)) 435 #define SPI_CS_HOLD_M (BIT(6)) 436 #define SPI_CS_HOLD_V 0x1 437 #define SPI_CS_HOLD_S 6 438 /* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 439 /*description: In the slave mode this bit can be used to change the polarity 440 of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ 441 #define SPI_TSCK_I_EDGE (BIT(5)) 442 #define SPI_TSCK_I_EDGE_M (BIT(5)) 443 #define SPI_TSCK_I_EDGE_V 0x1 444 #define SPI_TSCK_I_EDGE_S 5 445 /* SPI_OPI_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 446 /*description: Just for master mode. 1: spi controller is in OPI mode (all in 447 8-b-m). 0: others. Can be configured in CONF state.*/ 448 #define SPI_OPI_MODE (BIT(4)) 449 #define SPI_OPI_MODE_M (BIT(4)) 450 #define SPI_OPI_MODE_V 0x1 451 #define SPI_OPI_MODE_S 4 452 /* SPI_QPI_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 453 /*description: Both for master mode and slave mode. 1: spi controller is in 454 QPI mode. 0: others. Can be configured in CONF state.*/ 455 #define SPI_QPI_MODE (BIT(3)) 456 #define SPI_QPI_MODE_M (BIT(3)) 457 #define SPI_QPI_MODE_V 0x1 458 #define SPI_QPI_MODE_S 3 459 /* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 460 /*description: Set the bit to enable full duplex communication. 1: enable 0: 461 disable. Can be configured in CONF state.*/ 462 #define SPI_DOUTDIN (BIT(0)) 463 #define SPI_DOUTDIN_M (BIT(0)) 464 #define SPI_DOUTDIN_V 0x1 465 #define SPI_DOUTDIN_S 0 466 467 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x01C) 468 /* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */ 469 /*description: The length in bits of address phase. The register value shall 470 be (bit_num-1). Can be configured in CONF state.*/ 471 #define SPI_USR_ADDR_BITLEN 0x0000001F 472 #define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) 473 #define SPI_USR_ADDR_BITLEN_V 0x1F 474 #define SPI_USR_ADDR_BITLEN_S 27 475 /* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ 476 /*description: The length in spi_clk cycles of dummy phase. The register value 477 shall be (cycle_num-1). Can be configured in CONF state.*/ 478 #define SPI_USR_DUMMY_CYCLELEN 0x000000FF 479 #define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) 480 #define SPI_USR_DUMMY_CYCLELEN_V 0xFF 481 #define SPI_USR_DUMMY_CYCLELEN_S 0 482 483 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x020) 484 /* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ 485 /*description: The length in bits of command phase. The register value shall 486 be (bit_num-1). Can be configured in CONF state.*/ 487 #define SPI_USR_COMMAND_BITLEN 0x0000000F 488 #define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) 489 #define SPI_USR_COMMAND_BITLEN_V 0xF 490 #define SPI_USR_COMMAND_BITLEN_S 28 491 /* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 492 /*description: The value of command. Can be configured in CONF state.*/ 493 #define SPI_USR_COMMAND_VALUE 0x0000FFFF 494 #define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) 495 #define SPI_USR_COMMAND_VALUE_V 0xFFFF 496 #define SPI_USR_COMMAND_VALUE_S 0 497 498 #define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x024) 499 /* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ 500 /*description: The length in bits of write-data. The register value shall be 501 (bit_num-1). Can be configured in CONF state.*/ 502 #define SPI_USR_MOSI_DBITLEN 0x007FFFFF 503 #define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) 504 #define SPI_USR_MOSI_DBITLEN_V 0x7FFFFF 505 #define SPI_USR_MOSI_DBITLEN_S 0 506 507 #define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x028) 508 /* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ 509 /*description: The length in bits of read-data. The register value shall be 510 (bit_num-1). Can be configured in CONF state.*/ 511 #define SPI_USR_MISO_DBITLEN 0x007FFFFF 512 #define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) 513 #define SPI_USR_MISO_DBITLEN_V 0x7FFFFF 514 #define SPI_USR_MISO_DBITLEN_S 0 515 516 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x02C) 517 /* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ 518 /*description: 1: spi quad input swap enable 0: spi quad input swap disable. 519 Can be configured in CONF state.*/ 520 #define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) 521 #define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31)) 522 #define SPI_QUAD_DIN_PIN_SWAP_V 0x1 523 #define SPI_QUAD_DIN_PIN_SWAP_S 31 524 /* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 525 /*description: spi cs line keep low when the bit is set. Can be configured in CONF state.*/ 526 #define SPI_CS_KEEP_ACTIVE (BIT(30)) 527 #define SPI_CS_KEEP_ACTIVE_M (BIT(30)) 528 #define SPI_CS_KEEP_ACTIVE_V 0x1 529 #define SPI_CS_KEEP_ACTIVE_S 30 530 /* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ 531 /*description: 1: spi clk line is high when idle 0: spi clk line is low 532 when idle. Can be configured in CONF state.*/ 533 #define SPI_CK_IDLE_EDGE (BIT(29)) 534 #define SPI_CK_IDLE_EDGE_M (BIT(29)) 535 #define SPI_CK_IDLE_EDGE_V 0x1 536 #define SPI_CK_IDLE_EDGE_S 29 537 /* SPI_CD_IDLE_EDGE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 538 /*description: The default value of spi_cd. Can be configured in CONF state.*/ 539 #define SPI_CD_IDLE_EDGE (BIT(26)) 540 #define SPI_CD_IDLE_EDGE_M (BIT(26)) 541 #define SPI_CD_IDLE_EDGE_V 0x1 542 #define SPI_CD_IDLE_EDGE_S 26 543 /* SPI_CD_CMD_SET : R/W ;bitpos:[25] ;default: 1'b0 ; */ 544 /*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD 545 state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ 546 #define SPI_CD_CMD_SET (BIT(25)) 547 #define SPI_CD_CMD_SET_M (BIT(25)) 548 #define SPI_CD_CMD_SET_V 0x1 549 #define SPI_CD_CMD_SET_S 25 550 /* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */ 551 /*description: The default value of spi_dqs. Can be configured in CONF state.*/ 552 #define SPI_DQS_IDLE_EDGE (BIT(24)) 553 #define SPI_DQS_IDLE_EDGE_M (BIT(24)) 554 #define SPI_DQS_IDLE_EDGE_V 0x1 555 #define SPI_DQS_IDLE_EDGE_S 24 556 /* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */ 557 /*description: spi slave input cs polarity select. 1: inv 0: not change. Can 558 be configured in CONF state.*/ 559 #define SPI_SLAVE_CS_POL (BIT(23)) 560 #define SPI_SLAVE_CS_POL_M (BIT(23)) 561 #define SPI_SLAVE_CS_POL_V 0x1 562 #define SPI_SLAVE_CS_POL_S 23 563 /* SPI_CD_ADDR_SET : R/W ;bitpos:[22] ;default: 1'b0 ; */ 564 /*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR 565 state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ 566 #define SPI_CD_ADDR_SET (BIT(22)) 567 #define SPI_CD_ADDR_SET_M (BIT(22)) 568 #define SPI_CD_ADDR_SET_V 0x1 569 #define SPI_CD_ADDR_SET_S 22 570 /* SPI_CD_DUMMY_SET : R/W ;bitpos:[21] ;default: 1'b0 ; */ 571 /*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY 572 state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ 573 #define SPI_CD_DUMMY_SET (BIT(21)) 574 #define SPI_CD_DUMMY_SET_M (BIT(21)) 575 #define SPI_CD_DUMMY_SET_V 0x1 576 #define SPI_CD_DUMMY_SET_S 21 577 /* SPI_CD_DATA_SET : R/W ;bitpos:[20] ;default: 1'b0 ; */ 578 /*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT 579 or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ 580 #define SPI_CD_DATA_SET (BIT(20)) 581 #define SPI_CD_DATA_SET_M (BIT(20)) 582 #define SPI_CD_DATA_SET_V 0x1 583 #define SPI_CD_DATA_SET_S 20 584 /* SPI_CMD_DTR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 585 /*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including 586 master 1/2/4/8-bm. Can be configured in CONF state.*/ 587 #define SPI_CMD_DTR_EN (BIT(19)) 588 #define SPI_CMD_DTR_EN_M (BIT(19)) 589 #define SPI_CMD_DTR_EN_V 0x1 590 #define SPI_CMD_DTR_EN_S 19 591 /* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ 592 /*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including 593 master 1/2/4/8-bm. Can be configured in CONF state.*/ 594 #define SPI_ADDR_DTR_EN (BIT(18)) 595 #define SPI_ADDR_DTR_EN_M (BIT(18)) 596 #define SPI_ADDR_DTR_EN_V 0x1 597 #define SPI_ADDR_DTR_EN_S 18 598 /* SPI_DATA_DTR_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 599 /*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR 600 mode including master 1/2/4/8-bm. Can be configured in CONF state.*/ 601 #define SPI_DATA_DTR_EN (BIT(17)) 602 #define SPI_DATA_DTR_EN_M (BIT(17)) 603 #define SPI_DATA_DTR_EN_V 0x1 604 #define SPI_DATA_DTR_EN_S 17 605 /* SPI_CLK_DATA_DTR_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ 606 /*description: 1: SPI master DTR mode is applied to SPI clk data and spi_dqs*/ 607 #define SPI_CLK_DATA_DTR_EN (BIT(16)) 608 #define SPI_CLK_DATA_DTR_EN_M (BIT(16)) 609 #define SPI_CLK_DATA_DTR_EN_V 0x1 610 #define SPI_CLK_DATA_DTR_EN_S 16 611 /* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */ 612 /*description: In the master mode the bits are the polarity of spi cs line 613 the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ 614 #define SPI_MASTER_CS_POL 0x0000003F 615 #define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) 616 #define SPI_MASTER_CS_POL_V 0x3F 617 #define SPI_MASTER_CS_POL_S 7 618 /* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */ 619 /*description: 1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/ 620 #define SPI_CK_DIS (BIT(6)) 621 #define SPI_CK_DIS_M (BIT(6)) 622 #define SPI_CK_DIS_V 0x1 623 #define SPI_CK_DIS_S 6 624 /* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */ 625 /*description: SPI CS5 pin enable 1: disable CS5 0: spi_cs5 signal is from/to 626 CS5 pin. Can be configured in CONF state.*/ 627 #define SPI_CS5_DIS (BIT(5)) 628 #define SPI_CS5_DIS_M (BIT(5)) 629 #define SPI_CS5_DIS_V 0x1 630 #define SPI_CS5_DIS_S 5 631 /* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */ 632 /*description: SPI CS4 pin enable 1: disable CS4 0: spi_cs4 signal is from/to 633 CS4 pin. Can be configured in CONF state.*/ 634 #define SPI_CS4_DIS (BIT(4)) 635 #define SPI_CS4_DIS_M (BIT(4)) 636 #define SPI_CS4_DIS_V 0x1 637 #define SPI_CS4_DIS_S 4 638 /* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */ 639 /*description: reserved*/ 640 #define SPI_CS3_DIS (BIT(3)) 641 #define SPI_CS3_DIS_M (BIT(3)) 642 #define SPI_CS3_DIS_V 0x1 643 #define SPI_CS3_DIS_S 3 644 /* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ 645 /*description: SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to 646 CS2 pin. Can be configured in CONF state.*/ 647 #define SPI_CS2_DIS (BIT(2)) 648 #define SPI_CS2_DIS_M (BIT(2)) 649 #define SPI_CS2_DIS_V 0x1 650 #define SPI_CS2_DIS_S 2 651 /* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 652 /*description: SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to 653 CS1 pin. Can be configured in CONF state.*/ 654 #define SPI_CS1_DIS (BIT(1)) 655 #define SPI_CS1_DIS_M (BIT(1)) 656 #define SPI_CS1_DIS_V 0x1 657 #define SPI_CS1_DIS_S 1 658 /* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 659 /*description: SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to 660 CS0 pin. Can be configured in CONF state.*/ 661 #define SPI_CS0_DIS (BIT(0)) 662 #define SPI_CS0_DIS_M (BIT(0)) 663 #define SPI_CS0_DIS_V 0x1 664 #define SPI_CS0_DIS_S 0 665 666 #define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x030) 667 /* SPI_SOFT_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ 668 /*description: Software reset enable reset the spi clock line cs line and data 669 lines. Can be configured in CONF state.*/ 670 #define SPI_SOFT_RESET (BIT(31)) 671 #define SPI_SOFT_RESET_M (BIT(31)) 672 #define SPI_SOFT_RESET_V 0x1 673 #define SPI_SOFT_RESET_S 31 674 /* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 675 /*description: Set SPI work mode. 1: slave mode 0: master mode.*/ 676 #define SPI_SLAVE_MODE (BIT(30)) 677 #define SPI_SLAVE_MODE_M (BIT(30)) 678 #define SPI_SLAVE_MODE_V 0x1 679 #define SPI_SLAVE_MODE_S 30 680 /* SPI_TRANS_DONE_AUTO_CLR_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ 681 /*description: spi_trans_done auto clear enable clear it 3 apb cycles after 682 the pos edge of spi_trans_done. 0:disable. 1: enable. Can be configured in CONF state.*/ 683 #define SPI_TRANS_DONE_AUTO_CLR_EN (BIT(29)) 684 #define SPI_TRANS_DONE_AUTO_CLR_EN_M (BIT(29)) 685 #define SPI_TRANS_DONE_AUTO_CLR_EN_V 0x1 686 #define SPI_TRANS_DONE_AUTO_CLR_EN_S 29 687 /* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ 688 /*description: The operations counter in both the master mode and the slave mode.*/ 689 #define SPI_TRANS_CNT 0x0000000F 690 #define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) 691 #define SPI_TRANS_CNT_V 0xF 692 #define SPI_TRANS_CNT_S 23 693 /* SPI_SEG_MAGIC_ERR_INT_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 694 /*description: 1: Enable seg magic value error interrupt. 0: Others. Can be 695 configured in CONF state.*/ 696 #define SPI_SEG_MAGIC_ERR_INT_EN (BIT(11)) 697 #define SPI_SEG_MAGIC_ERR_INT_EN_M (BIT(11)) 698 #define SPI_SEG_MAGIC_ERR_INT_EN_V 0x1 699 #define SPI_SEG_MAGIC_ERR_INT_EN_S 11 700 /* SPI_INT_DMA_SEG_TRANS_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 701 /*description: spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable. 702 Can be configured in CONF state.*/ 703 #define SPI_INT_DMA_SEG_TRANS_EN (BIT(10)) 704 #define SPI_INT_DMA_SEG_TRANS_EN_M (BIT(10)) 705 #define SPI_INT_DMA_SEG_TRANS_EN_V 0x1 706 #define SPI_INT_DMA_SEG_TRANS_EN_S 10 707 /* SPI_INT_TRANS_DONE_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 708 /*description: spi_trans_done Interrupt enable. 1: enable 0: disable. Can be 709 configured in CONF state.*/ 710 #define SPI_INT_TRANS_DONE_EN (BIT(9)) 711 #define SPI_INT_TRANS_DONE_EN_M (BIT(9)) 712 #define SPI_INT_TRANS_DONE_EN_V 0x1 713 #define SPI_INT_TRANS_DONE_EN_S 9 714 /* SPI_INT_WR_DMA_DONE_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 715 /*description: spi_slv_wr_dma Interrupt enable. 1: enable 0: disable. Can be 716 configured in CONF state.*/ 717 #define SPI_INT_WR_DMA_DONE_EN (BIT(8)) 718 #define SPI_INT_WR_DMA_DONE_EN_M (BIT(8)) 719 #define SPI_INT_WR_DMA_DONE_EN_V 0x1 720 #define SPI_INT_WR_DMA_DONE_EN_S 8 721 /* SPI_INT_RD_DMA_DONE_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 722 /*description: spi_slv_rd_dma Interrupt enable. 1: enable 0: disable. Can be 723 configured in CONF state.*/ 724 #define SPI_INT_RD_DMA_DONE_EN (BIT(7)) 725 #define SPI_INT_RD_DMA_DONE_EN_M (BIT(7)) 726 #define SPI_INT_RD_DMA_DONE_EN_V 0x1 727 #define SPI_INT_RD_DMA_DONE_EN_S 7 728 /* SPI_INT_WR_BUF_DONE_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 729 /*description: spi_slv_wr_buf Interrupt enable. 1: enable 0: disable. Can be 730 configured in CONF state.*/ 731 #define SPI_INT_WR_BUF_DONE_EN (BIT(6)) 732 #define SPI_INT_WR_BUF_DONE_EN_M (BIT(6)) 733 #define SPI_INT_WR_BUF_DONE_EN_V 0x1 734 #define SPI_INT_WR_BUF_DONE_EN_S 6 735 /* SPI_INT_RD_BUF_DONE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 736 /*description: spi_slv_rd_buf Interrupt enable. 1: enable 0: disable. Can be 737 configured in CONF state.*/ 738 #define SPI_INT_RD_BUF_DONE_EN (BIT(5)) 739 #define SPI_INT_RD_BUF_DONE_EN_M (BIT(5)) 740 #define SPI_INT_RD_BUF_DONE_EN_V 0x1 741 #define SPI_INT_RD_BUF_DONE_EN_S 5 742 /* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 743 /*description: The interrupt raw bit for the completion of any operation in 744 both the master mode and the slave mode. Can not be changed by CONF_buf.*/ 745 #define SPI_TRANS_DONE (BIT(4)) 746 #define SPI_TRANS_DONE_M (BIT(4)) 747 #define SPI_TRANS_DONE_V 0x1 748 #define SPI_TRANS_DONE_S 4 749 750 #define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x034) 751 /* SPI_SLV_LAST_ADDR : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ 752 /*description: In the slave mode it is the value of address.*/ 753 #define SPI_SLV_LAST_ADDR 0x000000FF 754 #define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S)) 755 #define SPI_SLV_LAST_ADDR_V 0xFF 756 #define SPI_SLV_LAST_ADDR_S 24 757 /* SPI_SLV_LAST_COMMAND : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ 758 /*description: In the slave mode it is the value of command.*/ 759 #define SPI_SLV_LAST_COMMAND 0x000000FF 760 #define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) 761 #define SPI_SLV_LAST_COMMAND_V 0xFF 762 #define SPI_SLV_LAST_COMMAND_S 16 763 /* SPI_SLV_WR_DMA_DONE : R/W ;bitpos:[15] ;default: 1'b0 ; */ 764 /*description: The interrupt raw bit for the completion of dma write operation 765 in the slave mode. Can not be changed by CONF_buf.*/ 766 #define SPI_SLV_WR_DMA_DONE (BIT(15)) 767 #define SPI_SLV_WR_DMA_DONE_M (BIT(15)) 768 #define SPI_SLV_WR_DMA_DONE_V 0x1 769 #define SPI_SLV_WR_DMA_DONE_S 15 770 /* SPI_SLV_CMD_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ 771 /*description: 1: The command value of the last SPI transfer is not supported 772 by SPI slave. 0: The command value is supported or no command value is received.*/ 773 #define SPI_SLV_CMD_ERR (BIT(14)) 774 #define SPI_SLV_CMD_ERR_M (BIT(14)) 775 #define SPI_SLV_CMD_ERR_V 0x1 776 #define SPI_SLV_CMD_ERR_S 14 777 /* SPI_SLV_ADDR_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ 778 /*description: 1: The address value of the last SPI transfer is not supported 779 by SPI slave. 0: The address value is supported or no address value is received.*/ 780 #define SPI_SLV_ADDR_ERR (BIT(13)) 781 #define SPI_SLV_ADDR_ERR_M (BIT(13)) 782 #define SPI_SLV_ADDR_ERR_V 0x1 783 #define SPI_SLV_ADDR_ERR_S 13 784 /* SPI_SLV_NO_QPI_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 785 /*description: 1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported.*/ 786 #define SPI_SLV_NO_QPI_EN (BIT(12)) 787 #define SPI_SLV_NO_QPI_EN_M (BIT(12)) 788 #define SPI_SLV_NO_QPI_EN_V 0x1 789 #define SPI_SLV_NO_QPI_EN_S 12 790 /* SPI_SLV_CMD_ERR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ 791 /*description: 1: Clear spi_slv_cmd_err. 0: not valid. Can be changed by CONF_buf.*/ 792 #define SPI_SLV_CMD_ERR_CLR (BIT(11)) 793 #define SPI_SLV_CMD_ERR_CLR_M (BIT(11)) 794 #define SPI_SLV_CMD_ERR_CLR_V 0x1 795 #define SPI_SLV_CMD_ERR_CLR_S 11 796 /* SPI_SLV_ADDR_ERR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ 797 /*description: 1: Clear spi_slv_addr_err. 0: not valid. Can be changed by CONF_buf.*/ 798 #define SPI_SLV_ADDR_ERR_CLR (BIT(10)) 799 #define SPI_SLV_ADDR_ERR_CLR_M (BIT(10)) 800 #define SPI_SLV_ADDR_ERR_CLR_V 0x1 801 #define SPI_SLV_ADDR_ERR_CLR_S 10 802 803 #define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x038) 804 /* SPI_CONF_BASE_BITLEN : R/W ;bitpos:[31:25] ;default: 7'd108 ; */ 805 /*description: The basic spi_clk cycles of CONF state. The real cycle length 806 of CONF state if spi_usr_conf is enabled is spi_conf_base_bitlen[6:0] + spi_conf_bitlen[23:0].*/ 807 #define SPI_CONF_BASE_BITLEN 0x0000007F 808 #define SPI_CONF_BASE_BITLEN_M ((SPI_CONF_BASE_BITLEN_V)<<(SPI_CONF_BASE_BITLEN_S)) 809 #define SPI_CONF_BASE_BITLEN_V 0x7F 810 #define SPI_CONF_BASE_BITLEN_S 25 811 /* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[24] ;default: 1'b0 ; */ 812 /*description: The interrupt raw bit for the completion of write-buffer operation 813 in the slave mode. Can not be changed by CONF_buf.*/ 814 #define SPI_SLV_WR_BUF_DONE (BIT(24)) 815 #define SPI_SLV_WR_BUF_DONE_M (BIT(24)) 816 #define SPI_SLV_WR_BUF_DONE_V 0x1 817 #define SPI_SLV_WR_BUF_DONE_S 24 818 819 #define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x03C) 820 /* SPI_SEG_MAGIC_ERR : R/W ;bitpos:[25] ;default: 1'b0 ; */ 821 /*description: 1: The recent magic value in CONF buffer is not right in master 822 DMA seg-trans mode. 0: others.*/ 823 #define SPI_SEG_MAGIC_ERR (BIT(25)) 824 #define SPI_SEG_MAGIC_ERR_M (BIT(25)) 825 #define SPI_SEG_MAGIC_ERR_V 0x1 826 #define SPI_SEG_MAGIC_ERR_S 25 827 /* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[24] ;default: 1'b0 ; */ 828 /*description: The interrupt raw bit for the completion of read-buffer operation 829 in the slave mode. Can not be changed by CONF_buf.*/ 830 #define SPI_SLV_RD_BUF_DONE (BIT(24)) 831 #define SPI_SLV_RD_BUF_DONE_M (BIT(24)) 832 #define SPI_SLV_RD_BUF_DONE_V 0x1 833 #define SPI_SLV_RD_BUF_DONE_S 24 834 /* SPI_SLV_DMA_RD_BYTELEN : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 835 /*description: In the slave mode it is the length in bytes for read operations. 836 The register value shall be byte_num.*/ 837 #define SPI_SLV_DMA_RD_BYTELEN 0x000FFFFF 838 #define SPI_SLV_DMA_RD_BYTELEN_M ((SPI_SLV_DMA_RD_BYTELEN_V)<<(SPI_SLV_DMA_RD_BYTELEN_S)) 839 #define SPI_SLV_DMA_RD_BYTELEN_V 0xFFFFF 840 #define SPI_SLV_DMA_RD_BYTELEN_S 0 841 842 #define SPI_SLV_RD_BYTE_REG(i) (REG_SPI_BASE(i) + 0x040) 843 /* SPI_USR_CONF : R/W ;bitpos:[31] ;default: 1'b0 ; */ 844 /*description: 1: Enable the DMA CONF phase of current seg-trans operation 845 which means seg-trans will start. 0: This is not seg-trans mode.*/ 846 #define SPI_USR_CONF (BIT(31)) 847 #define SPI_USR_CONF_M (BIT(31)) 848 #define SPI_USR_CONF_V 0x1 849 #define SPI_USR_CONF_S 31 850 /* SPI_SLV_RD_DMA_DONE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 851 /*description: The interrupt raw bit for the completion of Rd-DMA operation 852 in the slave mode. Can not be changed by CONF_buf.*/ 853 #define SPI_SLV_RD_DMA_DONE (BIT(30)) 854 #define SPI_SLV_RD_DMA_DONE_M (BIT(30)) 855 #define SPI_SLV_RD_DMA_DONE_V 0x1 856 #define SPI_SLV_RD_DMA_DONE_S 30 857 /* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[27:24] ;default: 4'd10 ; */ 858 /*description: The magic value of BM table in master DMA seg-trans.*/ 859 #define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F 860 #define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S)) 861 #define SPI_DMA_SEG_MAGIC_VALUE_V 0xF 862 #define SPI_DMA_SEG_MAGIC_VALUE_S 24 863 /* SPI_SLV_WRBUF_BYTELEN_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ 864 /*description: 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave 865 data length in CPU controlled mode(Wr_BUF). 0: others*/ 866 #define SPI_SLV_WRBUF_BYTELEN_EN (BIT(23)) 867 #define SPI_SLV_WRBUF_BYTELEN_EN_M (BIT(23)) 868 #define SPI_SLV_WRBUF_BYTELEN_EN_V 0x1 869 #define SPI_SLV_WRBUF_BYTELEN_EN_S 23 870 /* SPI_SLV_RDBUF_BYTELEN_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ 871 /*description: 1: spi_slv_data_bytelen stores data byte length of master-read-slave 872 data length in CPU controlled mode(Rd_BUF). 0: others*/ 873 #define SPI_SLV_RDBUF_BYTELEN_EN (BIT(22)) 874 #define SPI_SLV_RDBUF_BYTELEN_EN_M (BIT(22)) 875 #define SPI_SLV_RDBUF_BYTELEN_EN_V 0x1 876 #define SPI_SLV_RDBUF_BYTELEN_EN_S 22 877 /* SPI_SLV_WRDMA_BYTELEN_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ 878 /*description: 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave 879 data length in DMA controlled mode(Wr_DMA). 0: others*/ 880 #define SPI_SLV_WRDMA_BYTELEN_EN (BIT(21)) 881 #define SPI_SLV_WRDMA_BYTELEN_EN_M (BIT(21)) 882 #define SPI_SLV_WRDMA_BYTELEN_EN_V 0x1 883 #define SPI_SLV_WRDMA_BYTELEN_EN_S 21 884 /* SPI_SLV_RDDMA_BYTELEN_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 885 /*description: 1: spi_slv_data_bytelen stores data byte length of master-read-slave 886 data length in DMA controlled mode(Rd_DMA). 0: others*/ 887 #define SPI_SLV_RDDMA_BYTELEN_EN (BIT(20)) 888 #define SPI_SLV_RDDMA_BYTELEN_EN_M (BIT(20)) 889 #define SPI_SLV_RDDMA_BYTELEN_EN_V 0x1 890 #define SPI_SLV_RDDMA_BYTELEN_EN_S 20 891 /* SPI_SLV_DATA_BYTELEN : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ 892 /*description: The full-duplex or half-duplex data byte length of the last SPI 893 transfer in slave mode. In half-duplex mode this value is controlled by bits [23:20].*/ 894 #define SPI_SLV_DATA_BYTELEN 0x000FFFFF 895 #define SPI_SLV_DATA_BYTELEN_M ((SPI_SLV_DATA_BYTELEN_V)<<(SPI_SLV_DATA_BYTELEN_S)) 896 #define SPI_SLV_DATA_BYTELEN_V 0xFFFFF 897 #define SPI_SLV_DATA_BYTELEN_S 0 898 899 #define SPI_FSM_REG(i) (REG_SPI_BASE(i) + 0x044) 900 /* SPI_MST_DMA_RD_BYTELEN : R/W ;bitpos:[31:12] ;default: 20'h0 ; */ 901 /*description: Define the master DMA read byte length in non seg-trans or seg-trans 902 mode. Invalid when spi_rx_eof_en is 0. Can be configured in CONF state..*/ 903 #define SPI_MST_DMA_RD_BYTELEN 0x000FFFFF 904 #define SPI_MST_DMA_RD_BYTELEN_M ((SPI_MST_DMA_RD_BYTELEN_V)<<(SPI_MST_DMA_RD_BYTELEN_S)) 905 #define SPI_MST_DMA_RD_BYTELEN_V 0xFFFFF 906 #define SPI_MST_DMA_RD_BYTELEN_S 12 907 /* SPI_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 908 /*description: The status of spi state machine. 0: idle state 1: preparation 909 state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ 910 #define SPI_ST 0x0000000F 911 #define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) 912 #define SPI_ST_V 0xF 913 #define SPI_ST_S 0 914 915 #define SPI_HOLD_REG(i) (REG_SPI_BASE(i) + 0x048) 916 /* SPI_DMA_SEG_TRANS_DONE : R/W ;bitpos:[7] ;default: 1'b0 ; */ 917 /*description: 1: spi master DMA full-duplex/half-duplex seg-trans ends or 918 slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.*/ 919 #define SPI_DMA_SEG_TRANS_DONE (BIT(7)) 920 #define SPI_DMA_SEG_TRANS_DONE_M (BIT(7)) 921 #define SPI_DMA_SEG_TRANS_DONE_V 0x1 922 #define SPI_DMA_SEG_TRANS_DONE_S 7 923 /* SPI_HOLD_OUT_TIME : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ 924 /*description: set the hold cycles of output spi_hold signal when spi_hold_out_en 925 is enable. Can be configured in CONF state.*/ 926 #define SPI_HOLD_OUT_TIME 0x00000007 927 #define SPI_HOLD_OUT_TIME_M ((SPI_HOLD_OUT_TIME_V)<<(SPI_HOLD_OUT_TIME_S)) 928 #define SPI_HOLD_OUT_TIME_V 0x7 929 #define SPI_HOLD_OUT_TIME_S 4 930 /* SPI_HOLD_OUT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 931 /*description: Enable set spi output hold value to spi_hold_reg. It can be used 932 to hold spi state machine with spi_ext_hold_en and other usr hold signals. Can be configured in CONF state.*/ 933 #define SPI_HOLD_OUT_EN (BIT(3)) 934 #define SPI_HOLD_OUT_EN_M (BIT(3)) 935 #define SPI_HOLD_OUT_EN_V 0x1 936 #define SPI_HOLD_OUT_EN_S 3 937 /* SPI_HOLD_VAL_REG : R/W ;bitpos:[2] ;default: 1'b0 ; */ 938 /*description: spi hold output value which should be used with spi_hold_out_en. 939 Can be configured in CONF state.*/ 940 #define SPI_HOLD_VAL_REG (BIT(2)) 941 #define SPI_HOLD_VAL_REG_M (BIT(2)) 942 #define SPI_HOLD_VAL_REG_V 0x1 943 #define SPI_HOLD_VAL_REG_S 2 944 /* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 945 /*description: This register is for two SPI masters to share the same cs clock 946 and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state.*/ 947 #define SPI_INT_HOLD_ENA 0x00000003 948 #define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) 949 #define SPI_INT_HOLD_ENA_V 0x3 950 #define SPI_INT_HOLD_ENA_S 0 951 952 #define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x04C) 953 /* SPI_DMA_SEG_TRANS_CLR : R/W ;bitpos:[28] ;default: 1'b0 ; */ 954 /*description: 1: End slave seg-trans which acts as 0x05 command. 2 or more 955 end seg-trans signals will induce error in DMA RX.*/ 956 #define SPI_DMA_SEG_TRANS_CLR (BIT(28)) 957 #define SPI_DMA_SEG_TRANS_CLR_M (BIT(28)) 958 #define SPI_DMA_SEG_TRANS_CLR_V 0x1 959 #define SPI_DMA_SEG_TRANS_CLR_S 28 960 /* SPI_EXT_MEM_BK_SIZE : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ 961 /*description: Select the external memory block size.*/ 962 #define SPI_EXT_MEM_BK_SIZE 0x00000003 963 #define SPI_EXT_MEM_BK_SIZE_M ((SPI_EXT_MEM_BK_SIZE_V)<<(SPI_EXT_MEM_BK_SIZE_S)) 964 #define SPI_EXT_MEM_BK_SIZE_V 0x3 965 #define SPI_EXT_MEM_BK_SIZE_S 26 966 /* SPI_DMA_OUTFIFO_EMPTY_CLR : R/W ;bitpos:[23] ;default: 1'b0 ; */ 967 /*description: 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.*/ 968 #define SPI_DMA_OUTFIFO_EMPTY_CLR (BIT(23)) 969 #define SPI_DMA_OUTFIFO_EMPTY_CLR_M (BIT(23)) 970 #define SPI_DMA_OUTFIFO_EMPTY_CLR_V 0x1 971 #define SPI_DMA_OUTFIFO_EMPTY_CLR_S 23 972 /* SPI_DMA_INFIFO_FULL_CLR : R/W ;bitpos:[22] ;default: 1'b0 ; */ 973 /*description: 1:Clear spi_dma_infifo_full_vld. 0: Do not control it.*/ 974 #define SPI_DMA_INFIFO_FULL_CLR (BIT(22)) 975 #define SPI_DMA_INFIFO_FULL_CLR_M (BIT(22)) 976 #define SPI_DMA_INFIFO_FULL_CLR_V 0x1 977 #define SPI_DMA_INFIFO_FULL_CLR_S 22 978 /* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ 979 /*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data 980 bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ 981 #define SPI_RX_EOF_EN (BIT(21)) 982 #define SPI_RX_EOF_EN_M (BIT(21)) 983 #define SPI_RX_EOF_EN_V 0x1 984 #define SPI_RX_EOF_EN_S 21 985 /* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 986 /*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: 987 spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ 988 #define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) 989 #define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (BIT(20)) 990 #define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x1 991 #define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 992 /* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 993 /*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: 994 spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ 995 #define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) 996 #define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (BIT(19)) 997 #define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x1 998 #define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 999 /* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ 1000 /*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ 1001 #define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) 1002 #define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) 1003 #define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 1004 #define SPI_DMA_SLV_SEG_TRANS_EN_S 18 1005 /* SPI_SLV_LAST_SEG_POP_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1006 /*description: 1: Clear spi_slv_seg_frt_pop_mask. 0 : others*/ 1007 #define SPI_SLV_LAST_SEG_POP_CLR (BIT(17)) 1008 #define SPI_SLV_LAST_SEG_POP_CLR_M (BIT(17)) 1009 #define SPI_SLV_LAST_SEG_POP_CLR_V 0x1 1010 #define SPI_SLV_LAST_SEG_POP_CLR_S 17 1011 /* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ 1012 /*description: spi dma continue tx/rx data.*/ 1013 #define SPI_DMA_CONTINUE (BIT(16)) 1014 #define SPI_DMA_CONTINUE_M (BIT(16)) 1015 #define SPI_DMA_CONTINUE_V 0x1 1016 #define SPI_DMA_CONTINUE_S 16 1017 /* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1018 /*description: spi dma write data stop when in continue tx/rx mode.*/ 1019 #define SPI_DMA_TX_STOP (BIT(15)) 1020 #define SPI_DMA_TX_STOP_M (BIT(15)) 1021 #define SPI_DMA_TX_STOP_V 0x1 1022 #define SPI_DMA_TX_STOP_S 15 1023 /* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1024 /*description: spi dma read data stop when in continue tx/rx mode.*/ 1025 #define SPI_DMA_RX_STOP (BIT(14)) 1026 #define SPI_DMA_RX_STOP_M (BIT(14)) 1027 #define SPI_DMA_RX_STOP_V 0x1 1028 #define SPI_DMA_RX_STOP_S 14 1029 /* SPI_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1030 /*description: */ 1031 #define SPI_MEM_TRANS_EN (BIT(13)) 1032 #define SPI_MEM_TRANS_EN_M (BIT(13)) 1033 #define SPI_MEM_TRANS_EN_V 0x1 1034 #define SPI_MEM_TRANS_EN_S 13 1035 /* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1036 /*description: spi dma read data from memory in burst mode.*/ 1037 #define SPI_OUT_DATA_BURST_EN (BIT(12)) 1038 #define SPI_OUT_DATA_BURST_EN_M (BIT(12)) 1039 #define SPI_OUT_DATA_BURST_EN_V 0x1 1040 #define SPI_OUT_DATA_BURST_EN_S 12 1041 /* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1042 /*description: read descriptor use burst mode when write data to memory.*/ 1043 #define SPI_INDSCR_BURST_EN (BIT(11)) 1044 #define SPI_INDSCR_BURST_EN_M (BIT(11)) 1045 #define SPI_INDSCR_BURST_EN_V 0x1 1046 #define SPI_INDSCR_BURST_EN_S 11 1047 /* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1048 /*description: read descriptor use burst mode when read data for memory.*/ 1049 #define SPI_OUTDSCR_BURST_EN (BIT(10)) 1050 #define SPI_OUTDSCR_BURST_EN_M (BIT(10)) 1051 #define SPI_OUTDSCR_BURST_EN_V 0x1 1052 #define SPI_OUTDSCR_BURST_EN_S 10 1053 /* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ 1054 /*description: out eof flag generation mode . 1: when dma pop all data from 1055 fifo 0:when ahb push all data to fifo.*/ 1056 #define SPI_OUT_EOF_MODE (BIT(9)) 1057 #define SPI_OUT_EOF_MODE_M (BIT(9)) 1058 #define SPI_OUT_EOF_MODE_V 0x1 1059 #define SPI_OUT_EOF_MODE_S 9 1060 /* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1061 /*description: when the bit is set DMA continue to use the next inlink node 1062 when the length of inlink is 0.*/ 1063 #define SPI_OUT_AUTO_WRBACK (BIT(8)) 1064 #define SPI_OUT_AUTO_WRBACK_M (BIT(8)) 1065 #define SPI_OUT_AUTO_WRBACK_V 0x1 1066 #define SPI_OUT_AUTO_WRBACK_S 8 1067 /* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1068 /*description: Set bit to test out link.*/ 1069 #define SPI_OUT_LOOP_TEST (BIT(7)) 1070 #define SPI_OUT_LOOP_TEST_M (BIT(7)) 1071 #define SPI_OUT_LOOP_TEST_V 0x1 1072 #define SPI_OUT_LOOP_TEST_S 7 1073 /* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1074 /*description: Set bit to test in link.*/ 1075 #define SPI_IN_LOOP_TEST (BIT(6)) 1076 #define SPI_IN_LOOP_TEST_M (BIT(6)) 1077 #define SPI_IN_LOOP_TEST_V 0x1 1078 #define SPI_IN_LOOP_TEST_S 6 1079 /* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1080 /*description: Reset spi dma ahb master.*/ 1081 #define SPI_AHBM_RST (BIT(5)) 1082 #define SPI_AHBM_RST_M (BIT(5)) 1083 #define SPI_AHBM_RST_V 0x1 1084 #define SPI_AHBM_RST_S 5 1085 /* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1086 /*description: Reset spi dma ahb master fifo pointer.*/ 1087 #define SPI_AHBM_FIFO_RST (BIT(4)) 1088 #define SPI_AHBM_FIFO_RST_M (BIT(4)) 1089 #define SPI_AHBM_FIFO_RST_V 0x1 1090 #define SPI_AHBM_FIFO_RST_S 4 1091 /* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1092 /*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ 1093 #define SPI_OUT_RST (BIT(3)) 1094 #define SPI_OUT_RST_M (BIT(3)) 1095 #define SPI_OUT_RST_V 0x1 1096 #define SPI_OUT_RST_S 3 1097 /* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1098 /*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ 1099 #define SPI_IN_RST (BIT(2)) 1100 #define SPI_IN_RST_M (BIT(2)) 1101 #define SPI_IN_RST_V 0x1 1102 #define SPI_IN_RST_S 2 1103 1104 #define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x050) 1105 /* SPI_DMA_TX_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1106 /*description: spi dma write data status bit.*/ 1107 #define SPI_DMA_TX_ENA (BIT(31)) 1108 #define SPI_DMA_TX_ENA_M (BIT(31)) 1109 #define SPI_DMA_TX_ENA_V 0x1 1110 #define SPI_DMA_TX_ENA_S 31 1111 /* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1112 /*description: Set the bit to mount on new outlink descriptors.*/ 1113 #define SPI_OUTLINK_RESTART (BIT(30)) 1114 #define SPI_OUTLINK_RESTART_M (BIT(30)) 1115 #define SPI_OUTLINK_RESTART_V 0x1 1116 #define SPI_OUTLINK_RESTART_S 30 1117 /* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1118 /*description: Set the bit to start to use outlink descriptor.*/ 1119 #define SPI_OUTLINK_START (BIT(29)) 1120 #define SPI_OUTLINK_START_M (BIT(29)) 1121 #define SPI_OUTLINK_START_V 0x1 1122 #define SPI_OUTLINK_START_S 29 1123 /* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ 1124 /*description: Set the bit to stop to use outlink descriptor.*/ 1125 #define SPI_OUTLINK_STOP (BIT(28)) 1126 #define SPI_OUTLINK_STOP_M (BIT(28)) 1127 #define SPI_OUTLINK_STOP_V 0x1 1128 #define SPI_OUTLINK_STOP_S 28 1129 /* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 1130 /*description: The address of the first outlink descriptor.*/ 1131 #define SPI_OUTLINK_ADDR 0x000FFFFF 1132 #define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) 1133 #define SPI_OUTLINK_ADDR_V 0xFFFFF 1134 #define SPI_OUTLINK_ADDR_S 0 1135 1136 #define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x054) 1137 /* SPI_DMA_RX_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1138 /*description: spi dma read data status bit.*/ 1139 #define SPI_DMA_RX_ENA (BIT(31)) 1140 #define SPI_DMA_RX_ENA_M (BIT(31)) 1141 #define SPI_DMA_RX_ENA_V 0x1 1142 #define SPI_DMA_RX_ENA_S 31 1143 /* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1144 /*description: Set the bit to mount on new inlink descriptors.*/ 1145 #define SPI_INLINK_RESTART (BIT(30)) 1146 #define SPI_INLINK_RESTART_M (BIT(30)) 1147 #define SPI_INLINK_RESTART_V 0x1 1148 #define SPI_INLINK_RESTART_S 30 1149 /* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1150 /*description: Set the bit to start to use inlink descriptor.*/ 1151 #define SPI_INLINK_START (BIT(29)) 1152 #define SPI_INLINK_START_M (BIT(29)) 1153 #define SPI_INLINK_START_V 0x1 1154 #define SPI_INLINK_START_S 29 1155 /* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ 1156 /*description: Set the bit to stop to use inlink descriptor.*/ 1157 #define SPI_INLINK_STOP (BIT(28)) 1158 #define SPI_INLINK_STOP_M (BIT(28)) 1159 #define SPI_INLINK_STOP_V 0x1 1160 #define SPI_INLINK_STOP_S 28 1161 /* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ 1162 /*description: when the bit is set the inlink descriptor returns to the first 1163 link node when a packet is error.*/ 1164 #define SPI_INLINK_AUTO_RET (BIT(20)) 1165 #define SPI_INLINK_AUTO_RET_M (BIT(20)) 1166 #define SPI_INLINK_AUTO_RET_V 0x1 1167 #define SPI_INLINK_AUTO_RET_S 20 1168 /* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 1169 /*description: The address of the first inlink descriptor.*/ 1170 #define SPI_INLINK_ADDR 0x000FFFFF 1171 #define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) 1172 #define SPI_INLINK_ADDR_V 0xFFFFF 1173 #define SPI_INLINK_ADDR_S 0 1174 1175 #define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x058) 1176 /* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1177 /*description: The enable bit for SPI slave CMDA interrupt.*/ 1178 #define SPI_SLV_CMDA_INT_ENA (BIT(15)) 1179 #define SPI_SLV_CMDA_INT_ENA_M (BIT(15)) 1180 #define SPI_SLV_CMDA_INT_ENA_V 0x1 1181 #define SPI_SLV_CMDA_INT_ENA_S 15 1182 /* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1183 /*description: The enable bit for SPI slave CMD9 interrupt.*/ 1184 #define SPI_SLV_CMD9_INT_ENA (BIT(14)) 1185 #define SPI_SLV_CMD9_INT_ENA_M (BIT(14)) 1186 #define SPI_SLV_CMD9_INT_ENA_V 0x1 1187 #define SPI_SLV_CMD9_INT_ENA_S 14 1188 /* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1189 /*description: The enable bit for SPI slave CMD8 interrupt.*/ 1190 #define SPI_SLV_CMD8_INT_ENA (BIT(13)) 1191 #define SPI_SLV_CMD8_INT_ENA_M (BIT(13)) 1192 #define SPI_SLV_CMD8_INT_ENA_V 0x1 1193 #define SPI_SLV_CMD8_INT_ENA_S 13 1194 /* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1195 /*description: The enable bit for SPI slave CMD7 interrupt.*/ 1196 #define SPI_SLV_CMD7_INT_ENA (BIT(12)) 1197 #define SPI_SLV_CMD7_INT_ENA_M (BIT(12)) 1198 #define SPI_SLV_CMD7_INT_ENA_V 0x1 1199 #define SPI_SLV_CMD7_INT_ENA_S 12 1200 /* SPI_SLV_CMD6_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1201 /*description: The enable bit for SPI slave CMD6 interrupt.*/ 1202 #define SPI_SLV_CMD6_INT_ENA (BIT(11)) 1203 #define SPI_SLV_CMD6_INT_ENA_M (BIT(11)) 1204 #define SPI_SLV_CMD6_INT_ENA_V 0x1 1205 #define SPI_SLV_CMD6_INT_ENA_S 11 1206 /* SPI_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1207 /*description: The enable bit for outfifo empty error interrupt.*/ 1208 #define SPI_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(10)) 1209 #define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_M (BIT(10)) 1210 #define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x1 1211 #define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_S 10 1212 /* SPI_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1213 /*description: The enable bit for infifo full error interrupt.*/ 1214 #define SPI_INFIFO_FULL_ERR_INT_ENA (BIT(9)) 1215 #define SPI_INFIFO_FULL_ERR_INT_ENA_M (BIT(9)) 1216 #define SPI_INFIFO_FULL_ERR_INT_ENA_V 0x1 1217 #define SPI_INFIFO_FULL_ERR_INT_ENA_S 9 1218 /* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1219 /*description: The enable bit for sending all the packets to host done. Can 1220 be configured in CONF state.*/ 1221 #define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) 1222 #define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) 1223 #define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 1224 #define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 1225 /* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1226 /*description: The enable bit for sending a packet to host done. Can be configured 1227 in CONF state.*/ 1228 #define SPI_OUT_EOF_INT_ENA (BIT(7)) 1229 #define SPI_OUT_EOF_INT_ENA_M (BIT(7)) 1230 #define SPI_OUT_EOF_INT_ENA_V 0x1 1231 #define SPI_OUT_EOF_INT_ENA_S 7 1232 /* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1233 /*description: The enable bit for completing usage of a outlink descriptor . 1234 Can be configured in CONF state.*/ 1235 #define SPI_OUT_DONE_INT_ENA (BIT(6)) 1236 #define SPI_OUT_DONE_INT_ENA_M (BIT(6)) 1237 #define SPI_OUT_DONE_INT_ENA_V 0x1 1238 #define SPI_OUT_DONE_INT_ENA_S 6 1239 /* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1240 /*description: The enable bit for completing receiving all the packets from 1241 host. Can be configured in CONF state.*/ 1242 #define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) 1243 #define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) 1244 #define SPI_IN_SUC_EOF_INT_ENA_V 0x1 1245 #define SPI_IN_SUC_EOF_INT_ENA_S 5 1246 /* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1247 /*description: The enable bit for receiving error. Can be configured in CONF state.*/ 1248 #define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) 1249 #define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) 1250 #define SPI_IN_ERR_EOF_INT_ENA_V 0x1 1251 #define SPI_IN_ERR_EOF_INT_ENA_S 4 1252 /* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1253 /*description: The enable bit for completing usage of a inlink descriptor. Can 1254 be configured in CONF state.*/ 1255 #define SPI_IN_DONE_INT_ENA (BIT(3)) 1256 #define SPI_IN_DONE_INT_ENA_M (BIT(3)) 1257 #define SPI_IN_DONE_INT_ENA_V 0x1 1258 #define SPI_IN_DONE_INT_ENA_S 3 1259 /* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1260 /*description: The enable bit for inlink descriptor error. Can be configured in CONF state.*/ 1261 #define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) 1262 #define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) 1263 #define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 1264 #define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 1265 /* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1266 /*description: The enable bit for outlink descriptor error. Can be configured in CONF state.*/ 1267 #define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) 1268 #define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) 1269 #define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 1270 #define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 1271 /* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1272 /*description: The enable bit for lack of enough inlink descriptors. Can be 1273 configured in CONF state.*/ 1274 #define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) 1275 #define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) 1276 #define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 1277 #define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 1278 1279 #define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x05C) 1280 /* SPI_SLV_CMDA_INT_RAW : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1281 /*description: The raw bit for SPI slave CMDA interrupt.*/ 1282 #define SPI_SLV_CMDA_INT_RAW (BIT(15)) 1283 #define SPI_SLV_CMDA_INT_RAW_M (BIT(15)) 1284 #define SPI_SLV_CMDA_INT_RAW_V 0x1 1285 #define SPI_SLV_CMDA_INT_RAW_S 15 1286 /* SPI_SLV_CMD9_INT_RAW : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1287 /*description: The raw bit for SPI slave CMD9 interrupt.*/ 1288 #define SPI_SLV_CMD9_INT_RAW (BIT(14)) 1289 #define SPI_SLV_CMD9_INT_RAW_M (BIT(14)) 1290 #define SPI_SLV_CMD9_INT_RAW_V 0x1 1291 #define SPI_SLV_CMD9_INT_RAW_S 14 1292 /* SPI_SLV_CMD8_INT_RAW : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1293 /*description: The raw bit for SPI slave CMD8 interrupt.*/ 1294 #define SPI_SLV_CMD8_INT_RAW (BIT(13)) 1295 #define SPI_SLV_CMD8_INT_RAW_M (BIT(13)) 1296 #define SPI_SLV_CMD8_INT_RAW_V 0x1 1297 #define SPI_SLV_CMD8_INT_RAW_S 13 1298 /* SPI_SLV_CMD7_INT_RAW : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1299 /*description: The raw bit for SPI slave CMD7 interrupt.*/ 1300 #define SPI_SLV_CMD7_INT_RAW (BIT(12)) 1301 #define SPI_SLV_CMD7_INT_RAW_M (BIT(12)) 1302 #define SPI_SLV_CMD7_INT_RAW_V 0x1 1303 #define SPI_SLV_CMD7_INT_RAW_S 12 1304 /* SPI_SLV_CMD6_INT_RAW : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1305 /*description: The raw bit for SPI slave CMD6 interrupt.*/ 1306 #define SPI_SLV_CMD6_INT_RAW (BIT(11)) 1307 #define SPI_SLV_CMD6_INT_RAW_M (BIT(11)) 1308 #define SPI_SLV_CMD6_INT_RAW_V 0x1 1309 #define SPI_SLV_CMD6_INT_RAW_S 11 1310 /* SPI_OUTFIFO_EMPTY_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 1311 /*description: 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which 1312 means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/ 1313 #define SPI_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(10)) 1314 #define SPI_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(10)) 1315 #define SPI_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1 1316 #define SPI_OUTFIFO_EMPTY_ERR_INT_RAW_S 10 1317 /* SPI_INFIFO_FULL_ERR_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 1318 /*description: 1:spi_dma_infifo_full and spi_push_data_prep are valid which 1319 means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/ 1320 #define SPI_INFIFO_FULL_ERR_INT_RAW (BIT(9)) 1321 #define SPI_INFIFO_FULL_ERR_INT_RAW_M (BIT(9)) 1322 #define SPI_INFIFO_FULL_ERR_INT_RAW_V 0x1 1323 #define SPI_INFIFO_FULL_ERR_INT_RAW_S 9 1324 /* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 1325 /*description: The raw bit for sending all the packets to host done. Can be 1326 configured in CONF state.*/ 1327 #define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) 1328 #define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) 1329 #define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 1330 #define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 1331 /* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 1332 /*description: The raw bit for sending a packet to host done. Can be configured in CONF state.*/ 1333 #define SPI_OUT_EOF_INT_RAW (BIT(7)) 1334 #define SPI_OUT_EOF_INT_RAW_M (BIT(7)) 1335 #define SPI_OUT_EOF_INT_RAW_V 0x1 1336 #define SPI_OUT_EOF_INT_RAW_S 7 1337 /* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 1338 /*description: The raw bit for completing usage of a outlink descriptor. Can 1339 be configured in CONF state.*/ 1340 #define SPI_OUT_DONE_INT_RAW (BIT(6)) 1341 #define SPI_OUT_DONE_INT_RAW_M (BIT(6)) 1342 #define SPI_OUT_DONE_INT_RAW_V 0x1 1343 #define SPI_OUT_DONE_INT_RAW_S 6 1344 /* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 1345 /*description: The raw bit for completing receiving all the packets from host. 1346 Can be configured in CONF state.*/ 1347 #define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) 1348 #define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) 1349 #define SPI_IN_SUC_EOF_INT_RAW_V 0x1 1350 #define SPI_IN_SUC_EOF_INT_RAW_S 5 1351 /* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 1352 /*description: The raw bit for receiving error. Can be configured in CONF state.*/ 1353 #define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) 1354 #define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) 1355 #define SPI_IN_ERR_EOF_INT_RAW_V 0x1 1356 #define SPI_IN_ERR_EOF_INT_RAW_S 4 1357 /* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 1358 /*description: The raw bit for completing usage of a inlink descriptor. Can 1359 be configured in CONF state.*/ 1360 #define SPI_IN_DONE_INT_RAW (BIT(3)) 1361 #define SPI_IN_DONE_INT_RAW_M (BIT(3)) 1362 #define SPI_IN_DONE_INT_RAW_V 0x1 1363 #define SPI_IN_DONE_INT_RAW_S 3 1364 /* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 1365 /*description: The raw bit for inlink descriptor error. Can be configured in CONF state.*/ 1366 #define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) 1367 #define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) 1368 #define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 1369 #define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 1370 /* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 1371 /*description: The raw bit for outlink descriptor error. Can be configured in CONF state.*/ 1372 #define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) 1373 #define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) 1374 #define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 1375 #define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 1376 /* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 1377 /*description: The raw bit for lack of enough inlink descriptors. Can be configured 1378 in CONF state.*/ 1379 #define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) 1380 #define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) 1381 #define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 1382 #define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 1383 1384 #define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x060) 1385 /* SPI_SLV_CMDA_INT_ST : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1386 /*description: The status bit for SPI slave CMDA interrupt.*/ 1387 #define SPI_SLV_CMDA_INT_ST (BIT(15)) 1388 #define SPI_SLV_CMDA_INT_ST_M (BIT(15)) 1389 #define SPI_SLV_CMDA_INT_ST_V 0x1 1390 #define SPI_SLV_CMDA_INT_ST_S 15 1391 /* SPI_SLV_CMD9_INT_ST : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1392 /*description: The status bit for SPI slave CMD9 interrupt.*/ 1393 #define SPI_SLV_CMD9_INT_ST (BIT(14)) 1394 #define SPI_SLV_CMD9_INT_ST_M (BIT(14)) 1395 #define SPI_SLV_CMD9_INT_ST_V 0x1 1396 #define SPI_SLV_CMD9_INT_ST_S 14 1397 /* SPI_SLV_CMD8_INT_ST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1398 /*description: The status bit for SPI slave CMD8 interrupt.*/ 1399 #define SPI_SLV_CMD8_INT_ST (BIT(13)) 1400 #define SPI_SLV_CMD8_INT_ST_M (BIT(13)) 1401 #define SPI_SLV_CMD8_INT_ST_V 0x1 1402 #define SPI_SLV_CMD8_INT_ST_S 13 1403 /* SPI_SLV_CMD7_INT_ST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1404 /*description: The status bit for SPI slave CMD7 interrupt.*/ 1405 #define SPI_SLV_CMD7_INT_ST (BIT(12)) 1406 #define SPI_SLV_CMD7_INT_ST_M (BIT(12)) 1407 #define SPI_SLV_CMD7_INT_ST_V 0x1 1408 #define SPI_SLV_CMD7_INT_ST_S 12 1409 /* SPI_SLV_CMD6_INT_ST : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1410 /*description: The status bit for SPI slave CMD6 interrupt.*/ 1411 #define SPI_SLV_CMD6_INT_ST (BIT(11)) 1412 #define SPI_SLV_CMD6_INT_ST_M (BIT(11)) 1413 #define SPI_SLV_CMD6_INT_ST_V 0x1 1414 #define SPI_SLV_CMD6_INT_ST_S 11 1415 /* SPI_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 1416 /*description: The status bit for outfifo empty error.*/ 1417 #define SPI_OUTFIFO_EMPTY_ERR_INT_ST (BIT(10)) 1418 #define SPI_OUTFIFO_EMPTY_ERR_INT_ST_M (BIT(10)) 1419 #define SPI_OUTFIFO_EMPTY_ERR_INT_ST_V 0x1 1420 #define SPI_OUTFIFO_EMPTY_ERR_INT_ST_S 10 1421 /* SPI_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 1422 /*description: The status bit for infifo full error.*/ 1423 #define SPI_INFIFO_FULL_ERR_INT_ST (BIT(9)) 1424 #define SPI_INFIFO_FULL_ERR_INT_ST_M (BIT(9)) 1425 #define SPI_INFIFO_FULL_ERR_INT_ST_V 0x1 1426 #define SPI_INFIFO_FULL_ERR_INT_ST_S 9 1427 /* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 1428 /*description: The status bit for sending all the packets to host done.*/ 1429 #define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) 1430 #define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) 1431 #define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 1432 #define SPI_OUT_TOTAL_EOF_INT_ST_S 8 1433 /* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 1434 /*description: The status bit for sending a packet to host done.*/ 1435 #define SPI_OUT_EOF_INT_ST (BIT(7)) 1436 #define SPI_OUT_EOF_INT_ST_M (BIT(7)) 1437 #define SPI_OUT_EOF_INT_ST_V 0x1 1438 #define SPI_OUT_EOF_INT_ST_S 7 1439 /* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 1440 /*description: The status bit for completing usage of a outlink descriptor.*/ 1441 #define SPI_OUT_DONE_INT_ST (BIT(6)) 1442 #define SPI_OUT_DONE_INT_ST_M (BIT(6)) 1443 #define SPI_OUT_DONE_INT_ST_V 0x1 1444 #define SPI_OUT_DONE_INT_ST_S 6 1445 /* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 1446 /*description: The status bit for completing receiving all the packets from host.*/ 1447 #define SPI_IN_SUC_EOF_INT_ST (BIT(5)) 1448 #define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) 1449 #define SPI_IN_SUC_EOF_INT_ST_V 0x1 1450 #define SPI_IN_SUC_EOF_INT_ST_S 5 1451 /* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1452 /*description: The status bit for receiving error.*/ 1453 #define SPI_IN_ERR_EOF_INT_ST (BIT(4)) 1454 #define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) 1455 #define SPI_IN_ERR_EOF_INT_ST_V 0x1 1456 #define SPI_IN_ERR_EOF_INT_ST_S 4 1457 /* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1458 /*description: The status bit for completing usage of a inlink descriptor.*/ 1459 #define SPI_IN_DONE_INT_ST (BIT(3)) 1460 #define SPI_IN_DONE_INT_ST_M (BIT(3)) 1461 #define SPI_IN_DONE_INT_ST_V 0x1 1462 #define SPI_IN_DONE_INT_ST_S 3 1463 /* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1464 /*description: The status bit for inlink descriptor error.*/ 1465 #define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) 1466 #define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) 1467 #define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 1468 #define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 1469 /* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1470 /*description: The status bit for outlink descriptor error.*/ 1471 #define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) 1472 #define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) 1473 #define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 1474 #define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 1475 /* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1476 /*description: The status bit for lack of enough inlink descriptors.*/ 1477 #define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) 1478 #define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) 1479 #define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 1480 #define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 1481 1482 #define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x064) 1483 /* SPI_SLV_CMDA_INT_CLR : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1484 /*description: The clear bit for SPI slave CMDA interrupt.*/ 1485 #define SPI_SLV_CMDA_INT_CLR (BIT(15)) 1486 #define SPI_SLV_CMDA_INT_CLR_M (BIT(15)) 1487 #define SPI_SLV_CMDA_INT_CLR_V 0x1 1488 #define SPI_SLV_CMDA_INT_CLR_S 15 1489 /* SPI_SLV_CMD9_INT_CLR : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1490 /*description: The clear bit for SPI slave CMD9 interrupt.*/ 1491 #define SPI_SLV_CMD9_INT_CLR (BIT(14)) 1492 #define SPI_SLV_CMD9_INT_CLR_M (BIT(14)) 1493 #define SPI_SLV_CMD9_INT_CLR_V 0x1 1494 #define SPI_SLV_CMD9_INT_CLR_S 14 1495 /* SPI_SLV_CMD8_INT_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1496 /*description: The clear bit for SPI slave CMD8 interrupt.*/ 1497 #define SPI_SLV_CMD8_INT_CLR (BIT(13)) 1498 #define SPI_SLV_CMD8_INT_CLR_M (BIT(13)) 1499 #define SPI_SLV_CMD8_INT_CLR_V 0x1 1500 #define SPI_SLV_CMD8_INT_CLR_S 13 1501 /* SPI_SLV_CMD7_INT_CLR : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1502 /*description: The clear bit for SPI slave CMD7 interrupt.*/ 1503 #define SPI_SLV_CMD7_INT_CLR (BIT(12)) 1504 #define SPI_SLV_CMD7_INT_CLR_M (BIT(12)) 1505 #define SPI_SLV_CMD7_INT_CLR_V 0x1 1506 #define SPI_SLV_CMD7_INT_CLR_S 12 1507 /* SPI_SLV_CMD6_INT_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1508 /*description: The clear bit for SPI slave CMD6 interrupt.*/ 1509 #define SPI_SLV_CMD6_INT_CLR (BIT(11)) 1510 #define SPI_SLV_CMD6_INT_CLR_M (BIT(11)) 1511 #define SPI_SLV_CMD6_INT_CLR_V 0x1 1512 #define SPI_SLV_CMD6_INT_CLR_S 11 1513 /* SPI_OUTFIFO_EMPTY_ERR_INT_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1514 /*description: 1: Clear spi_dma_outfifo_empty_err signal. 0: not valid. Can 1515 be changed by CONF_buf.*/ 1516 #define SPI_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(10)) 1517 #define SPI_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(10)) 1518 #define SPI_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1 1519 #define SPI_OUTFIFO_EMPTY_ERR_INT_CLR_S 10 1520 /* SPI_INFIFO_FULL_ERR_INT_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1521 /*description: 1: Clear spi_dma_infifo_full_err. 0: not valid. Can be changed by CONF_buf.*/ 1522 #define SPI_INFIFO_FULL_ERR_INT_CLR (BIT(9)) 1523 #define SPI_INFIFO_FULL_ERR_INT_CLR_M (BIT(9)) 1524 #define SPI_INFIFO_FULL_ERR_INT_CLR_V 0x1 1525 #define SPI_INFIFO_FULL_ERR_INT_CLR_S 9 1526 /* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1527 /*description: The clear bit for sending all the packets to host done. Can be 1528 configured in CONF state.*/ 1529 #define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) 1530 #define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) 1531 #define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 1532 #define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 1533 /* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1534 /*description: The clear bit for sending a packet to host done. Can be configured 1535 in CONF state.*/ 1536 #define SPI_OUT_EOF_INT_CLR (BIT(7)) 1537 #define SPI_OUT_EOF_INT_CLR_M (BIT(7)) 1538 #define SPI_OUT_EOF_INT_CLR_V 0x1 1539 #define SPI_OUT_EOF_INT_CLR_S 7 1540 /* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1541 /*description: The clear bit for completing usage of a outlink descriptor. Can 1542 be configured in CONF state.*/ 1543 #define SPI_OUT_DONE_INT_CLR (BIT(6)) 1544 #define SPI_OUT_DONE_INT_CLR_M (BIT(6)) 1545 #define SPI_OUT_DONE_INT_CLR_V 0x1 1546 #define SPI_OUT_DONE_INT_CLR_S 6 1547 /* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1548 /*description: The clear bit for completing receiving all the packets from host. 1549 Can be configured in CONF state.*/ 1550 #define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) 1551 #define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) 1552 #define SPI_IN_SUC_EOF_INT_CLR_V 0x1 1553 #define SPI_IN_SUC_EOF_INT_CLR_S 5 1554 /* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1555 /*description: The clear bit for receiving error. Can be configured in CONF state.*/ 1556 #define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) 1557 #define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) 1558 #define SPI_IN_ERR_EOF_INT_CLR_V 0x1 1559 #define SPI_IN_ERR_EOF_INT_CLR_S 4 1560 /* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1561 /*description: The clear bit for completing usage of a inlink descriptor. Can 1562 be configured in CONF state.*/ 1563 #define SPI_IN_DONE_INT_CLR (BIT(3)) 1564 #define SPI_IN_DONE_INT_CLR_M (BIT(3)) 1565 #define SPI_IN_DONE_INT_CLR_V 0x1 1566 #define SPI_IN_DONE_INT_CLR_S 3 1567 /* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1568 /*description: The clear bit for inlink descriptor error. Can be configured in CONF state.*/ 1569 #define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) 1570 #define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) 1571 #define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 1572 #define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 1573 /* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1574 /*description: The clear bit for outlink descriptor error. Can be configured in CONF state.*/ 1575 #define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) 1576 #define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) 1577 #define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 1578 #define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 1579 /* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1580 /*description: The clear bit for lack of enough inlink descriptors. Can be configured 1581 in CONF state.*/ 1582 #define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) 1583 #define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) 1584 #define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 1585 #define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 1586 1587 #define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x068) 1588 /* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1589 /*description: The inlink descriptor address when spi dma produce receiving error.*/ 1590 #define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF 1591 #define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) 1592 #define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF 1593 #define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 1594 1595 #define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x06C) 1596 /* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1597 /*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ 1598 #define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF 1599 #define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) 1600 #define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF 1601 #define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 1602 1603 #define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x070) 1604 /* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1605 /*description: The content of current in descriptor pointer.*/ 1606 #define SPI_DMA_INLINK_DSCR 0xFFFFFFFF 1607 #define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) 1608 #define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF 1609 #define SPI_DMA_INLINK_DSCR_S 0 1610 1611 #define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x074) 1612 /* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1613 /*description: The content of next in descriptor pointer.*/ 1614 #define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF 1615 #define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) 1616 #define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF 1617 #define SPI_DMA_INLINK_DSCR_BF0_S 0 1618 1619 #define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x078) 1620 /* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1621 /*description: The content of current in descriptor data buffer pointer.*/ 1622 #define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF 1623 #define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) 1624 #define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF 1625 #define SPI_DMA_INLINK_DSCR_BF1_S 0 1626 1627 #define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x07C) 1628 /* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1629 /*description: The address of buffer relative to the outlink descriptor that produce eof.*/ 1630 #define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF 1631 #define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) 1632 #define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF 1633 #define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 1634 1635 #define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x080) 1636 /* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1637 /*description: The last outlink descriptor address when spi dma produce to_eof.*/ 1638 #define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF 1639 #define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) 1640 #define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF 1641 #define SPI_DMA_OUT_EOF_DES_ADDR_S 0 1642 1643 #define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x084) 1644 /* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1645 /*description: The content of current out descriptor pointer.*/ 1646 #define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF 1647 #define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) 1648 #define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF 1649 #define SPI_DMA_OUTLINK_DSCR_S 0 1650 1651 #define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x088) 1652 /* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1653 /*description: The content of next out descriptor pointer.*/ 1654 #define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF 1655 #define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) 1656 #define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF 1657 #define SPI_DMA_OUTLINK_DSCR_BF0_S 0 1658 1659 #define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x08C) 1660 /* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 1661 /*description: The content of current out descriptor data buffer pointer.*/ 1662 #define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF 1663 #define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) 1664 #define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF 1665 #define SPI_DMA_OUTLINK_DSCR_BF1_S 0 1666 1667 #define SPI_DMA_OUTSTATUS_REG(i) (REG_SPI_BASE(i) + 0x090) 1668 /* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ 1669 /*description: SPI dma outfifo is empty.*/ 1670 #define SPI_DMA_OUTFIFO_EMPTY (BIT(31)) 1671 #define SPI_DMA_OUTFIFO_EMPTY_M (BIT(31)) 1672 #define SPI_DMA_OUTFIFO_EMPTY_V 0x1 1673 #define SPI_DMA_OUTFIFO_EMPTY_S 31 1674 /* SPI_DMA_OUTFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */ 1675 /*description: SPI dma outfifo is full.*/ 1676 #define SPI_DMA_OUTFIFO_FULL (BIT(30)) 1677 #define SPI_DMA_OUTFIFO_FULL_M (BIT(30)) 1678 #define SPI_DMA_OUTFIFO_FULL_V 0x1 1679 #define SPI_DMA_OUTFIFO_FULL_S 30 1680 /* SPI_DMA_OUTFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */ 1681 /*description: The remains of SPI dma outfifo data.*/ 1682 #define SPI_DMA_OUTFIFO_CNT 0x0000007F 1683 #define SPI_DMA_OUTFIFO_CNT_M ((SPI_DMA_OUTFIFO_CNT_V)<<(SPI_DMA_OUTFIFO_CNT_S)) 1684 #define SPI_DMA_OUTFIFO_CNT_V 0x7F 1685 #define SPI_DMA_OUTFIFO_CNT_S 23 1686 /* SPI_DMA_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ 1687 /*description: SPI dma out data state.*/ 1688 #define SPI_DMA_OUT_STATE 0x00000007 1689 #define SPI_DMA_OUT_STATE_M ((SPI_DMA_OUT_STATE_V)<<(SPI_DMA_OUT_STATE_S)) 1690 #define SPI_DMA_OUT_STATE_V 0x7 1691 #define SPI_DMA_OUT_STATE_S 20 1692 /* SPI_DMA_OUTDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ 1693 /*description: SPI dma out descriptor state.*/ 1694 #define SPI_DMA_OUTDSCR_STATE 0x00000003 1695 #define SPI_DMA_OUTDSCR_STATE_M ((SPI_DMA_OUTDSCR_STATE_V)<<(SPI_DMA_OUTDSCR_STATE_S)) 1696 #define SPI_DMA_OUTDSCR_STATE_V 0x3 1697 #define SPI_DMA_OUTDSCR_STATE_S 18 1698 /* SPI_DMA_OUTDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */ 1699 /*description: SPI dma out descriptor address.*/ 1700 #define SPI_DMA_OUTDSCR_ADDR 0x0003FFFF 1701 #define SPI_DMA_OUTDSCR_ADDR_M ((SPI_DMA_OUTDSCR_ADDR_V)<<(SPI_DMA_OUTDSCR_ADDR_S)) 1702 #define SPI_DMA_OUTDSCR_ADDR_V 0x3FFFF 1703 #define SPI_DMA_OUTDSCR_ADDR_S 0 1704 1705 #define SPI_DMA_INSTATUS_REG(i) (REG_SPI_BASE(i) + 0x094) 1706 /* SPI_DMA_INFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ 1707 /*description: SPI dma infifo is empty.*/ 1708 #define SPI_DMA_INFIFO_EMPTY (BIT(31)) 1709 #define SPI_DMA_INFIFO_EMPTY_M (BIT(31)) 1710 #define SPI_DMA_INFIFO_EMPTY_V 0x1 1711 #define SPI_DMA_INFIFO_EMPTY_S 31 1712 /* SPI_DMA_INFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */ 1713 /*description: SPI dma infifo is full.*/ 1714 #define SPI_DMA_INFIFO_FULL (BIT(30)) 1715 #define SPI_DMA_INFIFO_FULL_M (BIT(30)) 1716 #define SPI_DMA_INFIFO_FULL_V 0x1 1717 #define SPI_DMA_INFIFO_FULL_S 30 1718 /* SPI_DMA_INFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */ 1719 /*description: The remains of SPI dma infifo data.*/ 1720 #define SPI_DMA_INFIFO_CNT 0x0000007F 1721 #define SPI_DMA_INFIFO_CNT_M ((SPI_DMA_INFIFO_CNT_V)<<(SPI_DMA_INFIFO_CNT_S)) 1722 #define SPI_DMA_INFIFO_CNT_V 0x7F 1723 #define SPI_DMA_INFIFO_CNT_S 23 1724 /* SPI_DMA_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ 1725 /*description: SPI dma in data state.*/ 1726 #define SPI_DMA_IN_STATE 0x00000007 1727 #define SPI_DMA_IN_STATE_M ((SPI_DMA_IN_STATE_V)<<(SPI_DMA_IN_STATE_S)) 1728 #define SPI_DMA_IN_STATE_V 0x7 1729 #define SPI_DMA_IN_STATE_S 20 1730 /* SPI_DMA_INDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ 1731 /*description: SPI dma in descriptor state.*/ 1732 #define SPI_DMA_INDSCR_STATE 0x00000003 1733 #define SPI_DMA_INDSCR_STATE_M ((SPI_DMA_INDSCR_STATE_V)<<(SPI_DMA_INDSCR_STATE_S)) 1734 #define SPI_DMA_INDSCR_STATE_V 0x3 1735 #define SPI_DMA_INDSCR_STATE_S 18 1736 /* SPI_DMA_INDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */ 1737 /*description: SPI dma in descriptor address.*/ 1738 #define SPI_DMA_INDSCR_ADDR 0x0003FFFF 1739 #define SPI_DMA_INDSCR_ADDR_M ((SPI_DMA_INDSCR_ADDR_V)<<(SPI_DMA_INDSCR_ADDR_S)) 1740 #define SPI_DMA_INDSCR_ADDR_V 0x3FFFF 1741 #define SPI_DMA_INDSCR_ADDR_S 0 1742 1743 #define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x098) 1744 /* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1745 /*description: data buffer*/ 1746 #define SPI_BUF0 0xFFFFFFFF 1747 #define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) 1748 #define SPI_BUF0_V 0xFFFFFFFF 1749 #define SPI_BUF0_S 0 1750 1751 #define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x09C) 1752 /* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1753 /*description: data buffer*/ 1754 #define SPI_BUF1 0xFFFFFFFF 1755 #define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) 1756 #define SPI_BUF1_V 0xFFFFFFFF 1757 #define SPI_BUF1_S 0 1758 1759 #define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x0A0) 1760 /* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1761 /*description: data buffer*/ 1762 #define SPI_BUF2 0xFFFFFFFF 1763 #define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) 1764 #define SPI_BUF2_V 0xFFFFFFFF 1765 #define SPI_BUF2_S 0 1766 1767 #define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x0A4) 1768 /* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1769 /*description: data buffer*/ 1770 #define SPI_BUF3 0xFFFFFFFF 1771 #define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) 1772 #define SPI_BUF3_V 0xFFFFFFFF 1773 #define SPI_BUF3_S 0 1774 1775 #define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x0A8) 1776 /* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1777 /*description: data buffer*/ 1778 #define SPI_BUF4 0xFFFFFFFF 1779 #define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) 1780 #define SPI_BUF4_V 0xFFFFFFFF 1781 #define SPI_BUF4_S 0 1782 1783 #define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x0AC) 1784 /* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1785 /*description: data buffer*/ 1786 #define SPI_BUF5 0xFFFFFFFF 1787 #define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) 1788 #define SPI_BUF5_V 0xFFFFFFFF 1789 #define SPI_BUF5_S 0 1790 1791 #define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x0B0) 1792 /* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1793 /*description: data buffer*/ 1794 #define SPI_BUF6 0xFFFFFFFF 1795 #define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) 1796 #define SPI_BUF6_V 0xFFFFFFFF 1797 #define SPI_BUF6_S 0 1798 1799 #define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x0B4) 1800 /* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1801 /*description: data buffer*/ 1802 #define SPI_BUF7 0xFFFFFFFF 1803 #define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) 1804 #define SPI_BUF7_V 0xFFFFFFFF 1805 #define SPI_BUF7_S 0 1806 1807 #define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0x0B8) 1808 /* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1809 /*description: data buffer*/ 1810 #define SPI_BUF8 0xFFFFFFFF 1811 #define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) 1812 #define SPI_BUF8_V 0xFFFFFFFF 1813 #define SPI_BUF8_S 0 1814 1815 #define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0x0BC) 1816 /* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1817 /*description: data buffer*/ 1818 #define SPI_BUF9 0xFFFFFFFF 1819 #define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) 1820 #define SPI_BUF9_V 0xFFFFFFFF 1821 #define SPI_BUF9_S 0 1822 1823 #define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0x0C0) 1824 /* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1825 /*description: data buffer*/ 1826 #define SPI_BUF10 0xFFFFFFFF 1827 #define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) 1828 #define SPI_BUF10_V 0xFFFFFFFF 1829 #define SPI_BUF10_S 0 1830 1831 #define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0x0C4) 1832 /* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1833 /*description: data buffer*/ 1834 #define SPI_BUF11 0xFFFFFFFF 1835 #define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) 1836 #define SPI_BUF11_V 0xFFFFFFFF 1837 #define SPI_BUF11_S 0 1838 1839 #define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0x0C8) 1840 /* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1841 /*description: data buffer*/ 1842 #define SPI_BUF12 0xFFFFFFFF 1843 #define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) 1844 #define SPI_BUF12_V 0xFFFFFFFF 1845 #define SPI_BUF12_S 0 1846 1847 #define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0x0CC) 1848 /* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1849 /*description: data buffer*/ 1850 #define SPI_BUF13 0xFFFFFFFF 1851 #define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) 1852 #define SPI_BUF13_V 0xFFFFFFFF 1853 #define SPI_BUF13_S 0 1854 1855 #define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0x0D0) 1856 /* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1857 /*description: data buffer*/ 1858 #define SPI_BUF14 0xFFFFFFFF 1859 #define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) 1860 #define SPI_BUF14_V 0xFFFFFFFF 1861 #define SPI_BUF14_S 0 1862 1863 #define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0x0D4) 1864 /* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1865 /*description: data buffer*/ 1866 #define SPI_BUF15 0xFFFFFFFF 1867 #define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) 1868 #define SPI_BUF15_V 0xFFFFFFFF 1869 #define SPI_BUF15_S 0 1870 1871 #define SPI_W16_REG(i) (REG_SPI_BASE(i) + 0x0D8) 1872 /* SPI_BUF16 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1873 /*description: data buffer*/ 1874 #define SPI_BUF16 0xFFFFFFFF 1875 #define SPI_BUF16_M ((SPI_BUF16_V)<<(SPI_BUF16_S)) 1876 #define SPI_BUF16_V 0xFFFFFFFF 1877 #define SPI_BUF16_S 0 1878 1879 #define SPI_W17_REG(i) (REG_SPI_BASE(i) + 0x0DC) 1880 /* SPI_BUF17 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 1881 /*description: data buffer*/ 1882 #define SPI_BUF17 0xFFFFFFFF 1883 #define SPI_BUF17_M ((SPI_BUF17_V)<<(SPI_BUF17_S)) 1884 #define SPI_BUF17_V 0xFFFFFFFF 1885 #define SPI_BUF17_S 0 1886 1887 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x0E0) 1888 /* SPI_TIMING_CLK_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ 1889 /*description: 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state.*/ 1890 #define SPI_TIMING_CLK_ENA (BIT(24)) 1891 #define SPI_TIMING_CLK_ENA_M (BIT(24)) 1892 #define SPI_TIMING_CLK_ENA_V 0x1 1893 #define SPI_TIMING_CLK_ENA_S 24 1894 /* SPI_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ 1895 /*description: the input signals are delayed by system clock cycles 0: input 1896 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1897 #define SPI_DIN7_MODE 0x00000007 1898 #define SPI_DIN7_MODE_M ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S)) 1899 #define SPI_DIN7_MODE_V 0x7 1900 #define SPI_DIN7_MODE_S 21 1901 /* SPI_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ 1902 /*description: the input signals are delayed by system clock cycles 0: input 1903 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1904 #define SPI_DIN6_MODE 0x00000007 1905 #define SPI_DIN6_MODE_M ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S)) 1906 #define SPI_DIN6_MODE_V 0x7 1907 #define SPI_DIN6_MODE_S 18 1908 /* SPI_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ 1909 /*description: the input signals are delayed by system clock cycles 0: input 1910 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1911 #define SPI_DIN5_MODE 0x00000007 1912 #define SPI_DIN5_MODE_M ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S)) 1913 #define SPI_DIN5_MODE_V 0x7 1914 #define SPI_DIN5_MODE_S 15 1915 /* SPI_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ 1916 /*description: the input signals are delayed by system clock cycles 0: input 1917 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1918 #define SPI_DIN4_MODE 0x00000007 1919 #define SPI_DIN4_MODE_M ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S)) 1920 #define SPI_DIN4_MODE_V 0x7 1921 #define SPI_DIN4_MODE_S 12 1922 /* SPI_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ 1923 /*description: the input signals are delayed by system clock cycles 0: input 1924 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1925 #define SPI_DIN3_MODE 0x00000007 1926 #define SPI_DIN3_MODE_M ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S)) 1927 #define SPI_DIN3_MODE_V 0x7 1928 #define SPI_DIN3_MODE_S 9 1929 /* SPI_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ 1930 /*description: the input signals are delayed by system clock cycles 0: input 1931 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1932 #define SPI_DIN2_MODE 0x00000007 1933 #define SPI_DIN2_MODE_M ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S)) 1934 #define SPI_DIN2_MODE_V 0x7 1935 #define SPI_DIN2_MODE_S 6 1936 /* SPI_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ 1937 /*description: the input signals are delayed by system clock cycles 0: input 1938 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1939 #define SPI_DIN1_MODE 0x00000007 1940 #define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S)) 1941 #define SPI_DIN1_MODE_V 0x7 1942 #define SPI_DIN1_MODE_S 3 1943 /* SPI_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 1944 /*description: the input signals are delayed by system clock cycles 0: input 1945 without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ 1946 #define SPI_DIN0_MODE 0x00000007 1947 #define SPI_DIN0_MODE_M ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S)) 1948 #define SPI_DIN0_MODE_V 0x7 1949 #define SPI_DIN0_MODE_S 0 1950 1951 #define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x0E4) 1952 /* SPI_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ 1953 /*description: the input signals are delayed by system clock cycles 0: delayed 1954 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 1955 #define SPI_DIN7_NUM 0x00000003 1956 #define SPI_DIN7_NUM_M ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S)) 1957 #define SPI_DIN7_NUM_V 0x3 1958 #define SPI_DIN7_NUM_S 14 1959 /* SPI_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ 1960 /*description: the input signals are delayed by system clock cycles 0: delayed 1961 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 1962 #define SPI_DIN6_NUM 0x00000003 1963 #define SPI_DIN6_NUM_M ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S)) 1964 #define SPI_DIN6_NUM_V 0x3 1965 #define SPI_DIN6_NUM_S 12 1966 /* SPI_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ 1967 /*description: the input signals are delayed by system clock cycles 0: delayed 1968 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 1969 #define SPI_DIN5_NUM 0x00000003 1970 #define SPI_DIN5_NUM_M ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S)) 1971 #define SPI_DIN5_NUM_V 0x3 1972 #define SPI_DIN5_NUM_S 10 1973 /* SPI_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ 1974 /*description: the input signals are delayed by system clock cycles 0: delayed 1975 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 1976 #define SPI_DIN4_NUM 0x00000003 1977 #define SPI_DIN4_NUM_M ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S)) 1978 #define SPI_DIN4_NUM_V 0x3 1979 #define SPI_DIN4_NUM_S 8 1980 /* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ 1981 /*description: the input signals are delayed by system clock cycles 0: delayed 1982 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 1983 #define SPI_DIN3_NUM 0x00000003 1984 #define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S)) 1985 #define SPI_DIN3_NUM_V 0x3 1986 #define SPI_DIN3_NUM_S 6 1987 /* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ 1988 /*description: the input signals are delayed by system clock cycles 0: delayed 1989 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 1990 #define SPI_DIN2_NUM 0x00000003 1991 #define SPI_DIN2_NUM_M ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S)) 1992 #define SPI_DIN2_NUM_V 0x3 1993 #define SPI_DIN2_NUM_S 4 1994 /* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ 1995 /*description: the input signals are delayed by system clock cycles 0: delayed 1996 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 1997 #define SPI_DIN1_NUM 0x00000003 1998 #define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S)) 1999 #define SPI_DIN1_NUM_V 0x3 2000 #define SPI_DIN1_NUM_S 2 2001 /* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 2002 /*description: the input signals are delayed by system clock cycles 0: delayed 2003 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2004 #define SPI_DIN0_NUM 0x00000003 2005 #define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S)) 2006 #define SPI_DIN0_NUM_V 0x3 2007 #define SPI_DIN0_NUM_S 0 2008 2009 #define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x0E8) 2010 /* SPI_DOUT7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ 2011 /*description: the output signals are delayed by system clock cycles 0: output 2012 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2013 #define SPI_DOUT7_MODE 0x00000007 2014 #define SPI_DOUT7_MODE_M ((SPI_DOUT7_MODE_V)<<(SPI_DOUT7_MODE_S)) 2015 #define SPI_DOUT7_MODE_V 0x7 2016 #define SPI_DOUT7_MODE_S 21 2017 /* SPI_DOUT6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ 2018 /*description: the output signals are delayed by system clock cycles 0: output 2019 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2020 #define SPI_DOUT6_MODE 0x00000007 2021 #define SPI_DOUT6_MODE_M ((SPI_DOUT6_MODE_V)<<(SPI_DOUT6_MODE_S)) 2022 #define SPI_DOUT6_MODE_V 0x7 2023 #define SPI_DOUT6_MODE_S 18 2024 /* SPI_DOUT5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ 2025 /*description: the output signals are delayed by system clock cycles 0: output 2026 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2027 #define SPI_DOUT5_MODE 0x00000007 2028 #define SPI_DOUT5_MODE_M ((SPI_DOUT5_MODE_V)<<(SPI_DOUT5_MODE_S)) 2029 #define SPI_DOUT5_MODE_V 0x7 2030 #define SPI_DOUT5_MODE_S 15 2031 /* SPI_DOUT4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ 2032 /*description: the output signals are delayed by system clock cycles 0: output 2033 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2034 #define SPI_DOUT4_MODE 0x00000007 2035 #define SPI_DOUT4_MODE_M ((SPI_DOUT4_MODE_V)<<(SPI_DOUT4_MODE_S)) 2036 #define SPI_DOUT4_MODE_V 0x7 2037 #define SPI_DOUT4_MODE_S 12 2038 /* SPI_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ 2039 /*description: the output signals are delayed by system clock cycles 0: output 2040 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2041 #define SPI_DOUT3_MODE 0x00000007 2042 #define SPI_DOUT3_MODE_M ((SPI_DOUT3_MODE_V)<<(SPI_DOUT3_MODE_S)) 2043 #define SPI_DOUT3_MODE_V 0x7 2044 #define SPI_DOUT3_MODE_S 9 2045 /* SPI_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ 2046 /*description: the output signals are delayed by system clock cycles 0: output 2047 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2048 #define SPI_DOUT2_MODE 0x00000007 2049 #define SPI_DOUT2_MODE_M ((SPI_DOUT2_MODE_V)<<(SPI_DOUT2_MODE_S)) 2050 #define SPI_DOUT2_MODE_V 0x7 2051 #define SPI_DOUT2_MODE_S 6 2052 /* SPI_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ 2053 /*description: the output signals are delayed by system clock cycles 0: output 2054 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2055 #define SPI_DOUT1_MODE 0x00000007 2056 #define SPI_DOUT1_MODE_M ((SPI_DOUT1_MODE_V)<<(SPI_DOUT1_MODE_S)) 2057 #define SPI_DOUT1_MODE_V 0x7 2058 #define SPI_DOUT1_MODE_S 3 2059 /* SPI_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 2060 /*description: the output signals are delayed by system clock cycles 0: output 2061 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2062 #define SPI_DOUT0_MODE 0x00000007 2063 #define SPI_DOUT0_MODE_M ((SPI_DOUT0_MODE_V)<<(SPI_DOUT0_MODE_S)) 2064 #define SPI_DOUT0_MODE_V 0x7 2065 #define SPI_DOUT0_MODE_S 0 2066 2067 #define SPI_DOUT_NUM_REG(i) (REG_SPI_BASE(i) + 0x0EC) 2068 /* SPI_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ 2069 /*description: the output signals are delayed by system clock cycles 0: delayed 2070 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2071 #define SPI_DOUT7_NUM 0x00000003 2072 #define SPI_DOUT7_NUM_M ((SPI_DOUT7_NUM_V)<<(SPI_DOUT7_NUM_S)) 2073 #define SPI_DOUT7_NUM_V 0x3 2074 #define SPI_DOUT7_NUM_S 14 2075 /* SPI_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ 2076 /*description: the output signals are delayed by system clock cycles 0: delayed 2077 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2078 #define SPI_DOUT6_NUM 0x00000003 2079 #define SPI_DOUT6_NUM_M ((SPI_DOUT6_NUM_V)<<(SPI_DOUT6_NUM_S)) 2080 #define SPI_DOUT6_NUM_V 0x3 2081 #define SPI_DOUT6_NUM_S 12 2082 /* SPI_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ 2083 /*description: the output signals are delayed by system clock cycles 0: delayed 2084 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2085 #define SPI_DOUT5_NUM 0x00000003 2086 #define SPI_DOUT5_NUM_M ((SPI_DOUT5_NUM_V)<<(SPI_DOUT5_NUM_S)) 2087 #define SPI_DOUT5_NUM_V 0x3 2088 #define SPI_DOUT5_NUM_S 10 2089 /* SPI_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ 2090 /*description: the output signals are delayed by system clock cycles 0: delayed 2091 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2092 #define SPI_DOUT4_NUM 0x00000003 2093 #define SPI_DOUT4_NUM_M ((SPI_DOUT4_NUM_V)<<(SPI_DOUT4_NUM_S)) 2094 #define SPI_DOUT4_NUM_V 0x3 2095 #define SPI_DOUT4_NUM_S 8 2096 /* SPI_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ 2097 /*description: the output signals are delayed by system clock cycles 0: delayed 2098 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2099 #define SPI_DOUT3_NUM 0x00000003 2100 #define SPI_DOUT3_NUM_M ((SPI_DOUT3_NUM_V)<<(SPI_DOUT3_NUM_S)) 2101 #define SPI_DOUT3_NUM_V 0x3 2102 #define SPI_DOUT3_NUM_S 6 2103 /* SPI_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ 2104 /*description: the output signals are delayed by system clock cycles 0: delayed 2105 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2106 #define SPI_DOUT2_NUM 0x00000003 2107 #define SPI_DOUT2_NUM_M ((SPI_DOUT2_NUM_V)<<(SPI_DOUT2_NUM_S)) 2108 #define SPI_DOUT2_NUM_V 0x3 2109 #define SPI_DOUT2_NUM_S 4 2110 /* SPI_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ 2111 /*description: the output signals are delayed by system clock cycles 0: delayed 2112 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2113 #define SPI_DOUT1_NUM 0x00000003 2114 #define SPI_DOUT1_NUM_M ((SPI_DOUT1_NUM_V)<<(SPI_DOUT1_NUM_S)) 2115 #define SPI_DOUT1_NUM_V 0x3 2116 #define SPI_DOUT1_NUM_S 2 2117 /* SPI_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 2118 /*description: the output signals are delayed by system clock cycles 0: delayed 2119 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2120 #define SPI_DOUT0_NUM 0x00000003 2121 #define SPI_DOUT0_NUM_M ((SPI_DOUT0_NUM_V)<<(SPI_DOUT0_NUM_S)) 2122 #define SPI_DOUT0_NUM_V 0x3 2123 #define SPI_DOUT0_NUM_S 0 2124 2125 #define SPI_LCD_CTRL_REG(i) (REG_SPI_BASE(i) + 0x0F0) 2126 /* SPI_LCD_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2127 /*description: 1: Enable LCD mode output vsync hsync de. 0: Disable. Can be 2128 configured in CONF state.*/ 2129 #define SPI_LCD_MODE_EN (BIT(31)) 2130 #define SPI_LCD_MODE_EN_M (BIT(31)) 2131 #define SPI_LCD_MODE_EN_V 0x1 2132 #define SPI_LCD_MODE_EN_S 31 2133 /* SPI_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */ 2134 /*description: It is the vertical total height of a frame. Can be configured in CONF state.*/ 2135 #define SPI_LCD_VT_HEIGHT 0x000003FF 2136 #define SPI_LCD_VT_HEIGHT_M ((SPI_LCD_VT_HEIGHT_V)<<(SPI_LCD_VT_HEIGHT_S)) 2137 #define SPI_LCD_VT_HEIGHT_V 0x3FF 2138 #define SPI_LCD_VT_HEIGHT_S 21 2139 /* SPI_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */ 2140 /*description: It is the vertical active height of a frame. Can be configured in CONF state.*/ 2141 #define SPI_LCD_VA_HEIGHT 0x000003FF 2142 #define SPI_LCD_VA_HEIGHT_M ((SPI_LCD_VA_HEIGHT_V)<<(SPI_LCD_VA_HEIGHT_S)) 2143 #define SPI_LCD_VA_HEIGHT_V 0x3FF 2144 #define SPI_LCD_VA_HEIGHT_S 11 2145 /* SPI_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */ 2146 /*description: It is the horizontal blank front porch of a frame. Can be configured 2147 in CONF state.*/ 2148 #define SPI_LCD_HB_FRONT 0x000007FF 2149 #define SPI_LCD_HB_FRONT_M ((SPI_LCD_HB_FRONT_V)<<(SPI_LCD_HB_FRONT_S)) 2150 #define SPI_LCD_HB_FRONT_V 0x7FF 2151 #define SPI_LCD_HB_FRONT_S 0 2152 2153 #define SPI_LCD_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x0F4) 2154 /* SPI_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */ 2155 /*description: It is the horizontal total width of a frame. Can be configured in CONF state.*/ 2156 #define SPI_LCD_HT_WIDTH 0x00000FFF 2157 #define SPI_LCD_HT_WIDTH_M ((SPI_LCD_HT_WIDTH_V)<<(SPI_LCD_HT_WIDTH_S)) 2158 #define SPI_LCD_HT_WIDTH_V 0xFFF 2159 #define SPI_LCD_HT_WIDTH_S 20 2160 /* SPI_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */ 2161 /*description: It is the horizontal active width of a frame. Can be configured in CONF state.*/ 2162 #define SPI_LCD_HA_WIDTH 0x00000FFF 2163 #define SPI_LCD_HA_WIDTH_M ((SPI_LCD_HA_WIDTH_V)<<(SPI_LCD_HA_WIDTH_S)) 2164 #define SPI_LCD_HA_WIDTH_V 0xFFF 2165 #define SPI_LCD_HA_WIDTH_S 8 2166 /* SPI_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ 2167 /*description: It is the vertical blank front porch of a frame. Can be configured 2168 in CONF state.*/ 2169 #define SPI_LCD_VB_FRONT 0x000000FF 2170 #define SPI_LCD_VB_FRONT_M ((SPI_LCD_VB_FRONT_V)<<(SPI_LCD_VB_FRONT_S)) 2171 #define SPI_LCD_VB_FRONT_V 0xFF 2172 #define SPI_LCD_VB_FRONT_S 0 2173 2174 #define SPI_LCD_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x0F8) 2175 /* SPI_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ 2176 /*description: It is the position of spi_hsync active pulse in a line. Can be 2177 configured in CONF state.*/ 2178 #define SPI_LCD_HSYNC_POSITION 0x000000FF 2179 #define SPI_LCD_HSYNC_POSITION_M ((SPI_LCD_HSYNC_POSITION_V)<<(SPI_LCD_HSYNC_POSITION_S)) 2180 #define SPI_LCD_HSYNC_POSITION_V 0xFF 2181 #define SPI_LCD_HSYNC_POSITION_S 24 2182 /* SPI_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */ 2183 /*description: It is the idle value of spi_hsync. Can be configured in CONF state.*/ 2184 #define SPI_HSYNC_IDLE_POL (BIT(23)) 2185 #define SPI_HSYNC_IDLE_POL_M (BIT(23)) 2186 #define SPI_HSYNC_IDLE_POL_V 0x1 2187 #define SPI_HSYNC_IDLE_POL_S 23 2188 /* SPI_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */ 2189 /*description: It is the position of spi_hsync active pulse in a line. Can be 2190 configured in CONF state.*/ 2191 #define SPI_LCD_HSYNC_WIDTH 0x0000007F 2192 #define SPI_LCD_HSYNC_WIDTH_M ((SPI_LCD_HSYNC_WIDTH_V)<<(SPI_LCD_HSYNC_WIDTH_S)) 2193 #define SPI_LCD_HSYNC_WIDTH_V 0x7F 2194 #define SPI_LCD_HSYNC_WIDTH_S 16 2195 /* SPI_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */ 2196 /*description: It is the idle value of spi_vsync. Can be configured in CONF state.*/ 2197 #define SPI_VSYNC_IDLE_POL (BIT(7)) 2198 #define SPI_VSYNC_IDLE_POL_M (BIT(7)) 2199 #define SPI_VSYNC_IDLE_POL_V 0x1 2200 #define SPI_VSYNC_IDLE_POL_S 7 2201 /* SPI_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ 2202 /*description: It is the position of spi_vsync active pulse in a line. Can be 2203 configured in CONF state.*/ 2204 #define SPI_LCD_VSYNC_WIDTH 0x0000007F 2205 #define SPI_LCD_VSYNC_WIDTH_M ((SPI_LCD_VSYNC_WIDTH_V)<<(SPI_LCD_VSYNC_WIDTH_S)) 2206 #define SPI_LCD_VSYNC_WIDTH_V 0x7F 2207 #define SPI_LCD_VSYNC_WIDTH_S 0 2208 2209 #define SPI_LCD_D_MODE_REG(i) (REG_SPI_BASE(i) + 0x0FC) 2210 /* SPI_HS_BLANK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ 2211 /*description: 1: The pulse of spi_hsync is out in vertical blanking lines in 2212 seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans.*/ 2213 #define SPI_HS_BLANK_EN (BIT(16)) 2214 #define SPI_HS_BLANK_EN_M (BIT(16)) 2215 #define SPI_HS_BLANK_EN_V 0x1 2216 #define SPI_HS_BLANK_EN_S 16 2217 /* SPI_DE_IDLE_POL : R/W ;bitpos:[15] ;default: 1'd0 ; */ 2218 /*description: It is the idle value of spi_de.*/ 2219 #define SPI_DE_IDLE_POL (BIT(15)) 2220 #define SPI_DE_IDLE_POL_M (BIT(15)) 2221 #define SPI_DE_IDLE_POL_V 0x1 2222 #define SPI_DE_IDLE_POL_S 15 2223 /* SPI_D_VSYNC_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ 2224 /*description: the output spi_vsync is delayed by system clock cycles 0: output 2225 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2226 #define SPI_D_VSYNC_MODE 0x00000007 2227 #define SPI_D_VSYNC_MODE_M ((SPI_D_VSYNC_MODE_V)<<(SPI_D_VSYNC_MODE_S)) 2228 #define SPI_D_VSYNC_MODE_V 0x7 2229 #define SPI_D_VSYNC_MODE_S 12 2230 /* SPI_D_HSYNC_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ 2231 /*description: the output spi_hsync is delayed by system clock cycles 0: output 2232 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2233 #define SPI_D_HSYNC_MODE 0x00000007 2234 #define SPI_D_HSYNC_MODE_M ((SPI_D_HSYNC_MODE_V)<<(SPI_D_HSYNC_MODE_S)) 2235 #define SPI_D_HSYNC_MODE_V 0x7 2236 #define SPI_D_HSYNC_MODE_S 9 2237 /* SPI_D_DE_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ 2238 /*description: the output spi_de is delayed by system clock cycles 0: output 2239 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2240 #define SPI_D_DE_MODE 0x00000007 2241 #define SPI_D_DE_MODE_M ((SPI_D_DE_MODE_V)<<(SPI_D_DE_MODE_S)) 2242 #define SPI_D_DE_MODE_V 0x7 2243 #define SPI_D_DE_MODE_S 6 2244 /* SPI_D_CD_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ 2245 /*description: the output spi_cd is delayed by system clock cycles 0: output 2246 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2247 #define SPI_D_CD_MODE 0x00000007 2248 #define SPI_D_CD_MODE_M ((SPI_D_CD_MODE_V)<<(SPI_D_CD_MODE_S)) 2249 #define SPI_D_CD_MODE_V 0x7 2250 #define SPI_D_CD_MODE_S 3 2251 /* SPI_D_DQS_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 2252 /*description: the output spi_dqs is delayed by system clock cycles 0: output 2253 without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ 2254 #define SPI_D_DQS_MODE 0x00000007 2255 #define SPI_D_DQS_MODE_M ((SPI_D_DQS_MODE_V)<<(SPI_D_DQS_MODE_S)) 2256 #define SPI_D_DQS_MODE_V 0x7 2257 #define SPI_D_DQS_MODE_S 0 2258 2259 #define SPI_LCD_D_NUM_REG(i) (REG_SPI_BASE(i) + 0x100) 2260 /* SPI_D_VSYNC_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ 2261 /*description: the output spi_vsync is delayed by system clock cycles 0: delayed 2262 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2263 #define SPI_D_VSYNC_NUM 0x00000003 2264 #define SPI_D_VSYNC_NUM_M ((SPI_D_VSYNC_NUM_V)<<(SPI_D_VSYNC_NUM_S)) 2265 #define SPI_D_VSYNC_NUM_V 0x3 2266 #define SPI_D_VSYNC_NUM_S 8 2267 /* SPI_D_HSYNC_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ 2268 /*description: the output spi_hsync is delayed by system clock cycles 0: delayed 2269 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2270 #define SPI_D_HSYNC_NUM 0x00000003 2271 #define SPI_D_HSYNC_NUM_M ((SPI_D_HSYNC_NUM_V)<<(SPI_D_HSYNC_NUM_S)) 2272 #define SPI_D_HSYNC_NUM_V 0x3 2273 #define SPI_D_HSYNC_NUM_S 6 2274 /* SPI_D_DE_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ 2275 /*description: the output spi_de is delayed by system clock cycles 0: delayed 2276 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2277 #define SPI_D_DE_NUM 0x00000003 2278 #define SPI_D_DE_NUM_M ((SPI_D_DE_NUM_V)<<(SPI_D_DE_NUM_S)) 2279 #define SPI_D_DE_NUM_V 0x3 2280 #define SPI_D_DE_NUM_S 4 2281 /* SPI_D_CD_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ 2282 /*description: the output spi_cd is delayed by system clock cycles 0: delayed 2283 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2284 #define SPI_D_CD_NUM 0x00000003 2285 #define SPI_D_CD_NUM_M ((SPI_D_CD_NUM_V)<<(SPI_D_CD_NUM_S)) 2286 #define SPI_D_CD_NUM_V 0x3 2287 #define SPI_D_CD_NUM_S 2 2288 /* SPI_D_DQS_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 2289 /*description: the output spi_dqs is delayed by system clock cycles 0: delayed 2290 by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ 2291 #define SPI_D_DQS_NUM 0x00000003 2292 #define SPI_D_DQS_NUM_M ((SPI_D_DQS_NUM_V)<<(SPI_D_DQS_NUM_S)) 2293 #define SPI_D_DQS_NUM_V 0x3 2294 #define SPI_D_DQS_NUM_S 0 2295 2296 #define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) 2297 /* SPI_DATE : RW ;bitpos:[27:0] ;default: 28'h1907240 ; */ 2298 /*description: SPI register version.*/ 2299 #define SPI_DATE 0x0FFFFFFF 2300 #define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) 2301 #define SPI_DATE_V 0xFFFFFFF 2302 #define SPI_DATE_S 0 2303 2304 #ifdef __cplusplus 2305 } 2306 #endif 2307 2308 2309 2310 #endif /*_SOC_SPI_REG_H_ */ 2311
