1 // Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef _SOC_SLC_REG_H_
15 #define _SOC_SLC_REG_H_
16 
17 
18 #include "soc.h"
19 #define SLC_CONF0_REG          (DR_REG_SLC_BASE + 0x0)
20 /* SLC_SLC1_TOKEN_SEL : R/W ;bitpos:[31] ;default: 1'h1 ; */
21 /*description: */
22 #define SLC_SLC1_TOKEN_SEL  (BIT(31))
23 #define SLC_SLC1_TOKEN_SEL_M  (BIT(31))
24 #define SLC_SLC1_TOKEN_SEL_V  0x1
25 #define SLC_SLC1_TOKEN_SEL_S  31
26 /* SLC_SLC1_TOKEN_AUTO_CLR : R/W ;bitpos:[30] ;default: 1'h1 ; */
27 /*description: */
28 #define SLC_SLC1_TOKEN_AUTO_CLR  (BIT(30))
29 #define SLC_SLC1_TOKEN_AUTO_CLR_M  (BIT(30))
30 #define SLC_SLC1_TOKEN_AUTO_CLR_V  0x1
31 #define SLC_SLC1_TOKEN_AUTO_CLR_S  30
32 /* SLC_SLC1_TXDATA_BURST_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
33 /*description: */
34 #define SLC_SLC1_TXDATA_BURST_EN  (BIT(29))
35 #define SLC_SLC1_TXDATA_BURST_EN_M  (BIT(29))
36 #define SLC_SLC1_TXDATA_BURST_EN_V  0x1
37 #define SLC_SLC1_TXDATA_BURST_EN_S  29
38 /* SLC_SLC1_TXDSCR_BURST_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
39 /*description: */
40 #define SLC_SLC1_TXDSCR_BURST_EN  (BIT(28))
41 #define SLC_SLC1_TXDSCR_BURST_EN_M  (BIT(28))
42 #define SLC_SLC1_TXDSCR_BURST_EN_V  0x1
43 #define SLC_SLC1_TXDSCR_BURST_EN_S  28
44 /* SLC_SLC1_TXLINK_AUTO_RET : R/W ;bitpos:[27] ;default: 1'b1 ; */
45 /*description: */
46 #define SLC_SLC1_TXLINK_AUTO_RET  (BIT(27))
47 #define SLC_SLC1_TXLINK_AUTO_RET_M  (BIT(27))
48 #define SLC_SLC1_TXLINK_AUTO_RET_V  0x1
49 #define SLC_SLC1_TXLINK_AUTO_RET_S  27
50 /* SLC_SLC1_RXLINK_AUTO_RET : R/W ;bitpos:[26] ;default: 1'b1 ; */
51 /*description: */
52 #define SLC_SLC1_RXLINK_AUTO_RET  (BIT(26))
53 #define SLC_SLC1_RXLINK_AUTO_RET_M  (BIT(26))
54 #define SLC_SLC1_RXLINK_AUTO_RET_V  0x1
55 #define SLC_SLC1_RXLINK_AUTO_RET_S  26
56 /* SLC_SLC1_RXDATA_BURST_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
57 /*description: */
58 #define SLC_SLC1_RXDATA_BURST_EN  (BIT(25))
59 #define SLC_SLC1_RXDATA_BURST_EN_M  (BIT(25))
60 #define SLC_SLC1_RXDATA_BURST_EN_V  0x1
61 #define SLC_SLC1_RXDATA_BURST_EN_S  25
62 /* SLC_SLC1_RXDSCR_BURST_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
63 /*description: */
64 #define SLC_SLC1_RXDSCR_BURST_EN  (BIT(24))
65 #define SLC_SLC1_RXDSCR_BURST_EN_M  (BIT(24))
66 #define SLC_SLC1_RXDSCR_BURST_EN_V  0x1
67 #define SLC_SLC1_RXDSCR_BURST_EN_S  24
68 /* SLC_SLC1_RX_NO_RESTART_CLR : R/W ;bitpos:[23] ;default: 1'b0 ; */
69 /*description: */
70 #define SLC_SLC1_RX_NO_RESTART_CLR  (BIT(23))
71 #define SLC_SLC1_RX_NO_RESTART_CLR_M  (BIT(23))
72 #define SLC_SLC1_RX_NO_RESTART_CLR_V  0x1
73 #define SLC_SLC1_RX_NO_RESTART_CLR_S  23
74 /* SLC_SLC1_RX_AUTO_WRBACK : R/W ;bitpos:[22] ;default: 1'b0 ; */
75 /*description: */
76 #define SLC_SLC1_RX_AUTO_WRBACK  (BIT(22))
77 #define SLC_SLC1_RX_AUTO_WRBACK_M  (BIT(22))
78 #define SLC_SLC1_RX_AUTO_WRBACK_V  0x1
79 #define SLC_SLC1_RX_AUTO_WRBACK_S  22
80 /* SLC_SLC1_RX_LOOP_TEST : R/W ;bitpos:[21] ;default: 1'b1 ; */
81 /*description: */
82 #define SLC_SLC1_RX_LOOP_TEST  (BIT(21))
83 #define SLC_SLC1_RX_LOOP_TEST_M  (BIT(21))
84 #define SLC_SLC1_RX_LOOP_TEST_V  0x1
85 #define SLC_SLC1_RX_LOOP_TEST_S  21
86 /* SLC_SLC1_TX_LOOP_TEST : R/W ;bitpos:[20] ;default: 1'b1 ; */
87 /*description: */
88 #define SLC_SLC1_TX_LOOP_TEST  (BIT(20))
89 #define SLC_SLC1_TX_LOOP_TEST_M  (BIT(20))
90 #define SLC_SLC1_TX_LOOP_TEST_V  0x1
91 #define SLC_SLC1_TX_LOOP_TEST_S  20
92 /* SLC_SLC1_WR_RETRY_MASK_EN : R/W ;bitpos:[19] ;default: 1'b1 ; */
93 /*description: */
94 #define SLC_SLC1_WR_RETRY_MASK_EN  (BIT(19))
95 #define SLC_SLC1_WR_RETRY_MASK_EN_M  (BIT(19))
96 #define SLC_SLC1_WR_RETRY_MASK_EN_V  0x1
97 #define SLC_SLC1_WR_RETRY_MASK_EN_S  19
98 /* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
99 /*description: */
100 #define SLC_SLC0_WR_RETRY_MASK_EN  (BIT(18))
101 #define SLC_SLC0_WR_RETRY_MASK_EN_M  (BIT(18))
102 #define SLC_SLC0_WR_RETRY_MASK_EN_V  0x1
103 #define SLC_SLC0_WR_RETRY_MASK_EN_S  18
104 /* SLC_SLC1_RX_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
105 /*description: */
106 #define SLC_SLC1_RX_RST  (BIT(17))
107 #define SLC_SLC1_RX_RST_M  (BIT(17))
108 #define SLC_SLC1_RX_RST_V  0x1
109 #define SLC_SLC1_RX_RST_S  17
110 /* SLC_SLC1_TX_RST : R/W ;bitpos:[16] ;default: 1'h0 ; */
111 /*description: */
112 #define SLC_SLC1_TX_RST  (BIT(16))
113 #define SLC_SLC1_TX_RST_M  (BIT(16))
114 #define SLC_SLC1_TX_RST_V  0x1
115 #define SLC_SLC1_TX_RST_S  16
116 /* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */
117 /*description: */
118 #define SLC_SLC0_TOKEN_SEL  (BIT(15))
119 #define SLC_SLC0_TOKEN_SEL_M  (BIT(15))
120 #define SLC_SLC0_TOKEN_SEL_V  0x1
121 #define SLC_SLC0_TOKEN_SEL_S  15
122 /* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */
123 /*description: */
124 #define SLC_SLC0_TOKEN_AUTO_CLR  (BIT(14))
125 #define SLC_SLC0_TOKEN_AUTO_CLR_M  (BIT(14))
126 #define SLC_SLC0_TOKEN_AUTO_CLR_V  0x1
127 #define SLC_SLC0_TOKEN_AUTO_CLR_S  14
128 /* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
129 /*description: */
130 #define SLC_SLC0_TXDATA_BURST_EN  (BIT(13))
131 #define SLC_SLC0_TXDATA_BURST_EN_M  (BIT(13))
132 #define SLC_SLC0_TXDATA_BURST_EN_V  0x1
133 #define SLC_SLC0_TXDATA_BURST_EN_S  13
134 /* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
135 /*description: */
136 #define SLC_SLC0_TXDSCR_BURST_EN  (BIT(12))
137 #define SLC_SLC0_TXDSCR_BURST_EN_M  (BIT(12))
138 #define SLC_SLC0_TXDSCR_BURST_EN_V  0x1
139 #define SLC_SLC0_TXDSCR_BURST_EN_S  12
140 /* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */
141 /*description: */
142 #define SLC_SLC0_TXLINK_AUTO_RET  (BIT(11))
143 #define SLC_SLC0_TXLINK_AUTO_RET_M  (BIT(11))
144 #define SLC_SLC0_TXLINK_AUTO_RET_V  0x1
145 #define SLC_SLC0_TXLINK_AUTO_RET_S  11
146 /* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */
147 /*description: */
148 #define SLC_SLC0_RXLINK_AUTO_RET  (BIT(10))
149 #define SLC_SLC0_RXLINK_AUTO_RET_M  (BIT(10))
150 #define SLC_SLC0_RXLINK_AUTO_RET_V  0x1
151 #define SLC_SLC0_RXLINK_AUTO_RET_S  10
152 /* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
153 /*description: */
154 #define SLC_SLC0_RXDATA_BURST_EN  (BIT(9))
155 #define SLC_SLC0_RXDATA_BURST_EN_M  (BIT(9))
156 #define SLC_SLC0_RXDATA_BURST_EN_V  0x1
157 #define SLC_SLC0_RXDATA_BURST_EN_S  9
158 /* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
159 /*description: */
160 #define SLC_SLC0_RXDSCR_BURST_EN  (BIT(8))
161 #define SLC_SLC0_RXDSCR_BURST_EN_M  (BIT(8))
162 #define SLC_SLC0_RXDSCR_BURST_EN_V  0x1
163 #define SLC_SLC0_RXDSCR_BURST_EN_S  8
164 /* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
165 /*description: */
166 #define SLC_SLC0_RX_NO_RESTART_CLR  (BIT(7))
167 #define SLC_SLC0_RX_NO_RESTART_CLR_M  (BIT(7))
168 #define SLC_SLC0_RX_NO_RESTART_CLR_V  0x1
169 #define SLC_SLC0_RX_NO_RESTART_CLR_S  7
170 /* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
171 /*description: */
172 #define SLC_SLC0_RX_AUTO_WRBACK  (BIT(6))
173 #define SLC_SLC0_RX_AUTO_WRBACK_M  (BIT(6))
174 #define SLC_SLC0_RX_AUTO_WRBACK_V  0x1
175 #define SLC_SLC0_RX_AUTO_WRBACK_S  6
176 /* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */
177 /*description: */
178 #define SLC_SLC0_RX_LOOP_TEST  (BIT(5))
179 #define SLC_SLC0_RX_LOOP_TEST_M  (BIT(5))
180 #define SLC_SLC0_RX_LOOP_TEST_V  0x1
181 #define SLC_SLC0_RX_LOOP_TEST_S  5
182 /* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */
183 /*description: */
184 #define SLC_SLC0_TX_LOOP_TEST  (BIT(4))
185 #define SLC_SLC0_TX_LOOP_TEST_M  (BIT(4))
186 #define SLC_SLC0_TX_LOOP_TEST_V  0x1
187 #define SLC_SLC0_TX_LOOP_TEST_S  4
188 /* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
189 /*description: */
190 #define SLC_AHBM_RST  (BIT(3))
191 #define SLC_AHBM_RST_M  (BIT(3))
192 #define SLC_AHBM_RST_V  0x1
193 #define SLC_AHBM_RST_S  3
194 /* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
195 /*description: */
196 #define SLC_AHBM_FIFO_RST  (BIT(2))
197 #define SLC_AHBM_FIFO_RST_M  (BIT(2))
198 #define SLC_AHBM_FIFO_RST_V  0x1
199 #define SLC_AHBM_FIFO_RST_S  2
200 /* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
201 /*description: */
202 #define SLC_SLC0_RX_RST  (BIT(1))
203 #define SLC_SLC0_RX_RST_M  (BIT(1))
204 #define SLC_SLC0_RX_RST_V  0x1
205 #define SLC_SLC0_RX_RST_S  1
206 /* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
207 /*description: */
208 #define SLC_SLC0_TX_RST  (BIT(0))
209 #define SLC_SLC0_TX_RST_M  (BIT(0))
210 #define SLC_SLC0_TX_RST_V  0x1
211 #define SLC_SLC0_TX_RST_S  0
212 
213 #define SLC_0INT_RAW_REG          (DR_REG_SLC_BASE + 0x4)
214 /* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
215 /*description: */
216 #define SLC_SLC0_RX_QUICK_EOF_INT_RAW  (BIT(26))
217 #define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M  (BIT(26))
218 #define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V  0x1
219 #define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S  26
220 /* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
221 /*description: */
222 #define SLC_CMD_DTC_INT_RAW  (BIT(25))
223 #define SLC_CMD_DTC_INT_RAW_M  (BIT(25))
224 #define SLC_CMD_DTC_INT_RAW_V  0x1
225 #define SLC_CMD_DTC_INT_RAW_S  25
226 /* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
227 /*description: */
228 #define SLC_SLC0_TX_ERR_EOF_INT_RAW  (BIT(24))
229 #define SLC_SLC0_TX_ERR_EOF_INT_RAW_M  (BIT(24))
230 #define SLC_SLC0_TX_ERR_EOF_INT_RAW_V  0x1
231 #define SLC_SLC0_TX_ERR_EOF_INT_RAW_S  24
232 /* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
233 /*description: */
234 #define SLC_SLC0_WR_RETRY_DONE_INT_RAW  (BIT(23))
235 #define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M  (BIT(23))
236 #define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V  0x1
237 #define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S  23
238 /* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
239 /*description: */
240 #define SLC_SLC0_HOST_RD_ACK_INT_RAW  (BIT(22))
241 #define SLC_SLC0_HOST_RD_ACK_INT_RAW_M  (BIT(22))
242 #define SLC_SLC0_HOST_RD_ACK_INT_RAW_V  0x1
243 #define SLC_SLC0_HOST_RD_ACK_INT_RAW_S  22
244 /* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
245 /*description: */
246 #define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW  (BIT(21))
247 #define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (BIT(21))
248 #define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x1
249 #define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
250 /* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
251 /*description: */
252 #define SLC_SLC0_RX_DSCR_ERR_INT_RAW  (BIT(20))
253 #define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M  (BIT(20))
254 #define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V  0x1
255 #define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S  20
256 /* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
257 /*description: */
258 #define SLC_SLC0_TX_DSCR_ERR_INT_RAW  (BIT(19))
259 #define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M  (BIT(19))
260 #define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V  0x1
261 #define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S  19
262 /* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
263 /*description: */
264 #define SLC_SLC0_TOHOST_INT_RAW  (BIT(18))
265 #define SLC_SLC0_TOHOST_INT_RAW_M  (BIT(18))
266 #define SLC_SLC0_TOHOST_INT_RAW_V  0x1
267 #define SLC_SLC0_TOHOST_INT_RAW_S  18
268 /* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
269 /*description: */
270 #define SLC_SLC0_RX_EOF_INT_RAW  (BIT(17))
271 #define SLC_SLC0_RX_EOF_INT_RAW_M  (BIT(17))
272 #define SLC_SLC0_RX_EOF_INT_RAW_V  0x1
273 #define SLC_SLC0_RX_EOF_INT_RAW_S  17
274 /* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
275 /*description: */
276 #define SLC_SLC0_RX_DONE_INT_RAW  (BIT(16))
277 #define SLC_SLC0_RX_DONE_INT_RAW_M  (BIT(16))
278 #define SLC_SLC0_RX_DONE_INT_RAW_V  0x1
279 #define SLC_SLC0_RX_DONE_INT_RAW_S  16
280 /* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
281 /*description: */
282 #define SLC_SLC0_TX_SUC_EOF_INT_RAW  (BIT(15))
283 #define SLC_SLC0_TX_SUC_EOF_INT_RAW_M  (BIT(15))
284 #define SLC_SLC0_TX_SUC_EOF_INT_RAW_V  0x1
285 #define SLC_SLC0_TX_SUC_EOF_INT_RAW_S  15
286 /* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
287 /*description: */
288 #define SLC_SLC0_TX_DONE_INT_RAW  (BIT(14))
289 #define SLC_SLC0_TX_DONE_INT_RAW_M  (BIT(14))
290 #define SLC_SLC0_TX_DONE_INT_RAW_V  0x1
291 #define SLC_SLC0_TX_DONE_INT_RAW_S  14
292 /* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
293 /*description: */
294 #define SLC_SLC0_TOKEN1_1TO0_INT_RAW  (BIT(13))
295 #define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(13))
296 #define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
297 #define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S  13
298 /* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
299 /*description: */
300 #define SLC_SLC0_TOKEN0_1TO0_INT_RAW  (BIT(12))
301 #define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(12))
302 #define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
303 #define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S  12
304 /* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
305 /*description: */
306 #define SLC_SLC0_TX_OVF_INT_RAW  (BIT(11))
307 #define SLC_SLC0_TX_OVF_INT_RAW_M  (BIT(11))
308 #define SLC_SLC0_TX_OVF_INT_RAW_V  0x1
309 #define SLC_SLC0_TX_OVF_INT_RAW_S  11
310 /* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
311 /*description: */
312 #define SLC_SLC0_RX_UDF_INT_RAW  (BIT(10))
313 #define SLC_SLC0_RX_UDF_INT_RAW_M  (BIT(10))
314 #define SLC_SLC0_RX_UDF_INT_RAW_V  0x1
315 #define SLC_SLC0_RX_UDF_INT_RAW_S  10
316 /* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
317 /*description: */
318 #define SLC_SLC0_TX_START_INT_RAW  (BIT(9))
319 #define SLC_SLC0_TX_START_INT_RAW_M  (BIT(9))
320 #define SLC_SLC0_TX_START_INT_RAW_V  0x1
321 #define SLC_SLC0_TX_START_INT_RAW_S  9
322 /* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
323 /*description: */
324 #define SLC_SLC0_RX_START_INT_RAW  (BIT(8))
325 #define SLC_SLC0_RX_START_INT_RAW_M  (BIT(8))
326 #define SLC_SLC0_RX_START_INT_RAW_V  0x1
327 #define SLC_SLC0_RX_START_INT_RAW_S  8
328 /* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
329 /*description: */
330 #define SLC_FRHOST_BIT7_INT_RAW  (BIT(7))
331 #define SLC_FRHOST_BIT7_INT_RAW_M  (BIT(7))
332 #define SLC_FRHOST_BIT7_INT_RAW_V  0x1
333 #define SLC_FRHOST_BIT7_INT_RAW_S  7
334 /* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
335 /*description: */
336 #define SLC_FRHOST_BIT6_INT_RAW  (BIT(6))
337 #define SLC_FRHOST_BIT6_INT_RAW_M  (BIT(6))
338 #define SLC_FRHOST_BIT6_INT_RAW_V  0x1
339 #define SLC_FRHOST_BIT6_INT_RAW_S  6
340 /* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
341 /*description: */
342 #define SLC_FRHOST_BIT5_INT_RAW  (BIT(5))
343 #define SLC_FRHOST_BIT5_INT_RAW_M  (BIT(5))
344 #define SLC_FRHOST_BIT5_INT_RAW_V  0x1
345 #define SLC_FRHOST_BIT5_INT_RAW_S  5
346 /* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
347 /*description: */
348 #define SLC_FRHOST_BIT4_INT_RAW  (BIT(4))
349 #define SLC_FRHOST_BIT4_INT_RAW_M  (BIT(4))
350 #define SLC_FRHOST_BIT4_INT_RAW_V  0x1
351 #define SLC_FRHOST_BIT4_INT_RAW_S  4
352 /* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
353 /*description: */
354 #define SLC_FRHOST_BIT3_INT_RAW  (BIT(3))
355 #define SLC_FRHOST_BIT3_INT_RAW_M  (BIT(3))
356 #define SLC_FRHOST_BIT3_INT_RAW_V  0x1
357 #define SLC_FRHOST_BIT3_INT_RAW_S  3
358 /* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
359 /*description: */
360 #define SLC_FRHOST_BIT2_INT_RAW  (BIT(2))
361 #define SLC_FRHOST_BIT2_INT_RAW_M  (BIT(2))
362 #define SLC_FRHOST_BIT2_INT_RAW_V  0x1
363 #define SLC_FRHOST_BIT2_INT_RAW_S  2
364 /* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
365 /*description: */
366 #define SLC_FRHOST_BIT1_INT_RAW  (BIT(1))
367 #define SLC_FRHOST_BIT1_INT_RAW_M  (BIT(1))
368 #define SLC_FRHOST_BIT1_INT_RAW_V  0x1
369 #define SLC_FRHOST_BIT1_INT_RAW_S  1
370 /* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
371 /*description: */
372 #define SLC_FRHOST_BIT0_INT_RAW  (BIT(0))
373 #define SLC_FRHOST_BIT0_INT_RAW_M  (BIT(0))
374 #define SLC_FRHOST_BIT0_INT_RAW_V  0x1
375 #define SLC_FRHOST_BIT0_INT_RAW_S  0
376 
377 #define SLC_0INT_ST_REG          (DR_REG_SLC_BASE + 0x8)
378 /* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
379 /*description: */
380 #define SLC_SLC0_RX_QUICK_EOF_INT_ST  (BIT(26))
381 #define SLC_SLC0_RX_QUICK_EOF_INT_ST_M  (BIT(26))
382 #define SLC_SLC0_RX_QUICK_EOF_INT_ST_V  0x1
383 #define SLC_SLC0_RX_QUICK_EOF_INT_ST_S  26
384 /* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
385 /*description: */
386 #define SLC_CMD_DTC_INT_ST  (BIT(25))
387 #define SLC_CMD_DTC_INT_ST_M  (BIT(25))
388 #define SLC_CMD_DTC_INT_ST_V  0x1
389 #define SLC_CMD_DTC_INT_ST_S  25
390 /* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
391 /*description: */
392 #define SLC_SLC0_TX_ERR_EOF_INT_ST  (BIT(24))
393 #define SLC_SLC0_TX_ERR_EOF_INT_ST_M  (BIT(24))
394 #define SLC_SLC0_TX_ERR_EOF_INT_ST_V  0x1
395 #define SLC_SLC0_TX_ERR_EOF_INT_ST_S  24
396 /* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
397 /*description: */
398 #define SLC_SLC0_WR_RETRY_DONE_INT_ST  (BIT(23))
399 #define SLC_SLC0_WR_RETRY_DONE_INT_ST_M  (BIT(23))
400 #define SLC_SLC0_WR_RETRY_DONE_INT_ST_V  0x1
401 #define SLC_SLC0_WR_RETRY_DONE_INT_ST_S  23
402 /* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
403 /*description: */
404 #define SLC_SLC0_HOST_RD_ACK_INT_ST  (BIT(22))
405 #define SLC_SLC0_HOST_RD_ACK_INT_ST_M  (BIT(22))
406 #define SLC_SLC0_HOST_RD_ACK_INT_ST_V  0x1
407 #define SLC_SLC0_HOST_RD_ACK_INT_ST_S  22
408 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
409 /*description: */
410 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST  (BIT(21))
411 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M  (BIT(21))
412 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x1
413 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
414 /* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
415 /*description: */
416 #define SLC_SLC0_RX_DSCR_ERR_INT_ST  (BIT(20))
417 #define SLC_SLC0_RX_DSCR_ERR_INT_ST_M  (BIT(20))
418 #define SLC_SLC0_RX_DSCR_ERR_INT_ST_V  0x1
419 #define SLC_SLC0_RX_DSCR_ERR_INT_ST_S  20
420 /* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
421 /*description: */
422 #define SLC_SLC0_TX_DSCR_ERR_INT_ST  (BIT(19))
423 #define SLC_SLC0_TX_DSCR_ERR_INT_ST_M  (BIT(19))
424 #define SLC_SLC0_TX_DSCR_ERR_INT_ST_V  0x1
425 #define SLC_SLC0_TX_DSCR_ERR_INT_ST_S  19
426 /* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
427 /*description: */
428 #define SLC_SLC0_TOHOST_INT_ST  (BIT(18))
429 #define SLC_SLC0_TOHOST_INT_ST_M  (BIT(18))
430 #define SLC_SLC0_TOHOST_INT_ST_V  0x1
431 #define SLC_SLC0_TOHOST_INT_ST_S  18
432 /* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
433 /*description: */
434 #define SLC_SLC0_RX_EOF_INT_ST  (BIT(17))
435 #define SLC_SLC0_RX_EOF_INT_ST_M  (BIT(17))
436 #define SLC_SLC0_RX_EOF_INT_ST_V  0x1
437 #define SLC_SLC0_RX_EOF_INT_ST_S  17
438 /* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
439 /*description: */
440 #define SLC_SLC0_RX_DONE_INT_ST  (BIT(16))
441 #define SLC_SLC0_RX_DONE_INT_ST_M  (BIT(16))
442 #define SLC_SLC0_RX_DONE_INT_ST_V  0x1
443 #define SLC_SLC0_RX_DONE_INT_ST_S  16
444 /* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
445 /*description: */
446 #define SLC_SLC0_TX_SUC_EOF_INT_ST  (BIT(15))
447 #define SLC_SLC0_TX_SUC_EOF_INT_ST_M  (BIT(15))
448 #define SLC_SLC0_TX_SUC_EOF_INT_ST_V  0x1
449 #define SLC_SLC0_TX_SUC_EOF_INT_ST_S  15
450 /* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
451 /*description: */
452 #define SLC_SLC0_TX_DONE_INT_ST  (BIT(14))
453 #define SLC_SLC0_TX_DONE_INT_ST_M  (BIT(14))
454 #define SLC_SLC0_TX_DONE_INT_ST_V  0x1
455 #define SLC_SLC0_TX_DONE_INT_ST_S  14
456 /* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
457 /*description: */
458 #define SLC_SLC0_TOKEN1_1TO0_INT_ST  (BIT(13))
459 #define SLC_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(13))
460 #define SLC_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
461 #define SLC_SLC0_TOKEN1_1TO0_INT_ST_S  13
462 /* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
463 /*description: */
464 #define SLC_SLC0_TOKEN0_1TO0_INT_ST  (BIT(12))
465 #define SLC_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(12))
466 #define SLC_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
467 #define SLC_SLC0_TOKEN0_1TO0_INT_ST_S  12
468 /* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
469 /*description: */
470 #define SLC_SLC0_TX_OVF_INT_ST  (BIT(11))
471 #define SLC_SLC0_TX_OVF_INT_ST_M  (BIT(11))
472 #define SLC_SLC0_TX_OVF_INT_ST_V  0x1
473 #define SLC_SLC0_TX_OVF_INT_ST_S  11
474 /* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
475 /*description: */
476 #define SLC_SLC0_RX_UDF_INT_ST  (BIT(10))
477 #define SLC_SLC0_RX_UDF_INT_ST_M  (BIT(10))
478 #define SLC_SLC0_RX_UDF_INT_ST_V  0x1
479 #define SLC_SLC0_RX_UDF_INT_ST_S  10
480 /* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
481 /*description: */
482 #define SLC_SLC0_TX_START_INT_ST  (BIT(9))
483 #define SLC_SLC0_TX_START_INT_ST_M  (BIT(9))
484 #define SLC_SLC0_TX_START_INT_ST_V  0x1
485 #define SLC_SLC0_TX_START_INT_ST_S  9
486 /* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
487 /*description: */
488 #define SLC_SLC0_RX_START_INT_ST  (BIT(8))
489 #define SLC_SLC0_RX_START_INT_ST_M  (BIT(8))
490 #define SLC_SLC0_RX_START_INT_ST_V  0x1
491 #define SLC_SLC0_RX_START_INT_ST_S  8
492 /* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
493 /*description: */
494 #define SLC_FRHOST_BIT7_INT_ST  (BIT(7))
495 #define SLC_FRHOST_BIT7_INT_ST_M  (BIT(7))
496 #define SLC_FRHOST_BIT7_INT_ST_V  0x1
497 #define SLC_FRHOST_BIT7_INT_ST_S  7
498 /* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
499 /*description: */
500 #define SLC_FRHOST_BIT6_INT_ST  (BIT(6))
501 #define SLC_FRHOST_BIT6_INT_ST_M  (BIT(6))
502 #define SLC_FRHOST_BIT6_INT_ST_V  0x1
503 #define SLC_FRHOST_BIT6_INT_ST_S  6
504 /* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
505 /*description: */
506 #define SLC_FRHOST_BIT5_INT_ST  (BIT(5))
507 #define SLC_FRHOST_BIT5_INT_ST_M  (BIT(5))
508 #define SLC_FRHOST_BIT5_INT_ST_V  0x1
509 #define SLC_FRHOST_BIT5_INT_ST_S  5
510 /* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
511 /*description: */
512 #define SLC_FRHOST_BIT4_INT_ST  (BIT(4))
513 #define SLC_FRHOST_BIT4_INT_ST_M  (BIT(4))
514 #define SLC_FRHOST_BIT4_INT_ST_V  0x1
515 #define SLC_FRHOST_BIT4_INT_ST_S  4
516 /* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
517 /*description: */
518 #define SLC_FRHOST_BIT3_INT_ST  (BIT(3))
519 #define SLC_FRHOST_BIT3_INT_ST_M  (BIT(3))
520 #define SLC_FRHOST_BIT3_INT_ST_V  0x1
521 #define SLC_FRHOST_BIT3_INT_ST_S  3
522 /* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
523 /*description: */
524 #define SLC_FRHOST_BIT2_INT_ST  (BIT(2))
525 #define SLC_FRHOST_BIT2_INT_ST_M  (BIT(2))
526 #define SLC_FRHOST_BIT2_INT_ST_V  0x1
527 #define SLC_FRHOST_BIT2_INT_ST_S  2
528 /* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
529 /*description: */
530 #define SLC_FRHOST_BIT1_INT_ST  (BIT(1))
531 #define SLC_FRHOST_BIT1_INT_ST_M  (BIT(1))
532 #define SLC_FRHOST_BIT1_INT_ST_V  0x1
533 #define SLC_FRHOST_BIT1_INT_ST_S  1
534 /* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
535 /*description: */
536 #define SLC_FRHOST_BIT0_INT_ST  (BIT(0))
537 #define SLC_FRHOST_BIT0_INT_ST_M  (BIT(0))
538 #define SLC_FRHOST_BIT0_INT_ST_V  0x1
539 #define SLC_FRHOST_BIT0_INT_ST_S  0
540 
541 #define SLC_0INT_ENA_REG          (DR_REG_SLC_BASE + 0xC)
542 /* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
543 /*description: */
544 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA  (BIT(26))
545 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M  (BIT(26))
546 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V  0x1
547 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S  26
548 /* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
549 /*description: */
550 #define SLC_CMD_DTC_INT_ENA  (BIT(25))
551 #define SLC_CMD_DTC_INT_ENA_M  (BIT(25))
552 #define SLC_CMD_DTC_INT_ENA_V  0x1
553 #define SLC_CMD_DTC_INT_ENA_S  25
554 /* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
555 /*description: */
556 #define SLC_SLC0_TX_ERR_EOF_INT_ENA  (BIT(24))
557 #define SLC_SLC0_TX_ERR_EOF_INT_ENA_M  (BIT(24))
558 #define SLC_SLC0_TX_ERR_EOF_INT_ENA_V  0x1
559 #define SLC_SLC0_TX_ERR_EOF_INT_ENA_S  24
560 /* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
561 /*description: */
562 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA  (BIT(23))
563 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M  (BIT(23))
564 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V  0x1
565 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S  23
566 /* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
567 /*description: */
568 #define SLC_SLC0_HOST_RD_ACK_INT_ENA  (BIT(22))
569 #define SLC_SLC0_HOST_RD_ACK_INT_ENA_M  (BIT(22))
570 #define SLC_SLC0_HOST_RD_ACK_INT_ENA_V  0x1
571 #define SLC_SLC0_HOST_RD_ACK_INT_ENA_S  22
572 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
573 /*description: */
574 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA  (BIT(21))
575 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (BIT(21))
576 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x1
577 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
578 /* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
579 /*description: */
580 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA  (BIT(20))
581 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M  (BIT(20))
582 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V  0x1
583 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S  20
584 /* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
585 /*description: */
586 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA  (BIT(19))
587 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M  (BIT(19))
588 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V  0x1
589 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S  19
590 /* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
591 /*description: */
592 #define SLC_SLC0_TOHOST_INT_ENA  (BIT(18))
593 #define SLC_SLC0_TOHOST_INT_ENA_M  (BIT(18))
594 #define SLC_SLC0_TOHOST_INT_ENA_V  0x1
595 #define SLC_SLC0_TOHOST_INT_ENA_S  18
596 /* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
597 /*description: */
598 #define SLC_SLC0_RX_EOF_INT_ENA  (BIT(17))
599 #define SLC_SLC0_RX_EOF_INT_ENA_M  (BIT(17))
600 #define SLC_SLC0_RX_EOF_INT_ENA_V  0x1
601 #define SLC_SLC0_RX_EOF_INT_ENA_S  17
602 /* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
603 /*description: */
604 #define SLC_SLC0_RX_DONE_INT_ENA  (BIT(16))
605 #define SLC_SLC0_RX_DONE_INT_ENA_M  (BIT(16))
606 #define SLC_SLC0_RX_DONE_INT_ENA_V  0x1
607 #define SLC_SLC0_RX_DONE_INT_ENA_S  16
608 /* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
609 /*description: */
610 #define SLC_SLC0_TX_SUC_EOF_INT_ENA  (BIT(15))
611 #define SLC_SLC0_TX_SUC_EOF_INT_ENA_M  (BIT(15))
612 #define SLC_SLC0_TX_SUC_EOF_INT_ENA_V  0x1
613 #define SLC_SLC0_TX_SUC_EOF_INT_ENA_S  15
614 /* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
615 /*description: */
616 #define SLC_SLC0_TX_DONE_INT_ENA  (BIT(14))
617 #define SLC_SLC0_TX_DONE_INT_ENA_M  (BIT(14))
618 #define SLC_SLC0_TX_DONE_INT_ENA_V  0x1
619 #define SLC_SLC0_TX_DONE_INT_ENA_S  14
620 /* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
621 /*description: */
622 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(13))
623 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(13))
624 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
625 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S  13
626 /* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
627 /*description: */
628 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(12))
629 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(12))
630 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
631 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S  12
632 /* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
633 /*description: */
634 #define SLC_SLC0_TX_OVF_INT_ENA  (BIT(11))
635 #define SLC_SLC0_TX_OVF_INT_ENA_M  (BIT(11))
636 #define SLC_SLC0_TX_OVF_INT_ENA_V  0x1
637 #define SLC_SLC0_TX_OVF_INT_ENA_S  11
638 /* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
639 /*description: */
640 #define SLC_SLC0_RX_UDF_INT_ENA  (BIT(10))
641 #define SLC_SLC0_RX_UDF_INT_ENA_M  (BIT(10))
642 #define SLC_SLC0_RX_UDF_INT_ENA_V  0x1
643 #define SLC_SLC0_RX_UDF_INT_ENA_S  10
644 /* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
645 /*description: */
646 #define SLC_SLC0_TX_START_INT_ENA  (BIT(9))
647 #define SLC_SLC0_TX_START_INT_ENA_M  (BIT(9))
648 #define SLC_SLC0_TX_START_INT_ENA_V  0x1
649 #define SLC_SLC0_TX_START_INT_ENA_S  9
650 /* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
651 /*description: */
652 #define SLC_SLC0_RX_START_INT_ENA  (BIT(8))
653 #define SLC_SLC0_RX_START_INT_ENA_M  (BIT(8))
654 #define SLC_SLC0_RX_START_INT_ENA_V  0x1
655 #define SLC_SLC0_RX_START_INT_ENA_S  8
656 /* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
657 /*description: */
658 #define SLC_FRHOST_BIT7_INT_ENA  (BIT(7))
659 #define SLC_FRHOST_BIT7_INT_ENA_M  (BIT(7))
660 #define SLC_FRHOST_BIT7_INT_ENA_V  0x1
661 #define SLC_FRHOST_BIT7_INT_ENA_S  7
662 /* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
663 /*description: */
664 #define SLC_FRHOST_BIT6_INT_ENA  (BIT(6))
665 #define SLC_FRHOST_BIT6_INT_ENA_M  (BIT(6))
666 #define SLC_FRHOST_BIT6_INT_ENA_V  0x1
667 #define SLC_FRHOST_BIT6_INT_ENA_S  6
668 /* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
669 /*description: */
670 #define SLC_FRHOST_BIT5_INT_ENA  (BIT(5))
671 #define SLC_FRHOST_BIT5_INT_ENA_M  (BIT(5))
672 #define SLC_FRHOST_BIT5_INT_ENA_V  0x1
673 #define SLC_FRHOST_BIT5_INT_ENA_S  5
674 /* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
675 /*description: */
676 #define SLC_FRHOST_BIT4_INT_ENA  (BIT(4))
677 #define SLC_FRHOST_BIT4_INT_ENA_M  (BIT(4))
678 #define SLC_FRHOST_BIT4_INT_ENA_V  0x1
679 #define SLC_FRHOST_BIT4_INT_ENA_S  4
680 /* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
681 /*description: */
682 #define SLC_FRHOST_BIT3_INT_ENA  (BIT(3))
683 #define SLC_FRHOST_BIT3_INT_ENA_M  (BIT(3))
684 #define SLC_FRHOST_BIT3_INT_ENA_V  0x1
685 #define SLC_FRHOST_BIT3_INT_ENA_S  3
686 /* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
687 /*description: */
688 #define SLC_FRHOST_BIT2_INT_ENA  (BIT(2))
689 #define SLC_FRHOST_BIT2_INT_ENA_M  (BIT(2))
690 #define SLC_FRHOST_BIT2_INT_ENA_V  0x1
691 #define SLC_FRHOST_BIT2_INT_ENA_S  2
692 /* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
693 /*description: */
694 #define SLC_FRHOST_BIT1_INT_ENA  (BIT(1))
695 #define SLC_FRHOST_BIT1_INT_ENA_M  (BIT(1))
696 #define SLC_FRHOST_BIT1_INT_ENA_V  0x1
697 #define SLC_FRHOST_BIT1_INT_ENA_S  1
698 /* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
699 /*description: */
700 #define SLC_FRHOST_BIT0_INT_ENA  (BIT(0))
701 #define SLC_FRHOST_BIT0_INT_ENA_M  (BIT(0))
702 #define SLC_FRHOST_BIT0_INT_ENA_V  0x1
703 #define SLC_FRHOST_BIT0_INT_ENA_S  0
704 
705 #define SLC_0INT_CLR_REG          (DR_REG_SLC_BASE + 0x10)
706 /* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
707 /*description: */
708 #define SLC_SLC0_RX_QUICK_EOF_INT_CLR  (BIT(26))
709 #define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M  (BIT(26))
710 #define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V  0x1
711 #define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S  26
712 /* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
713 /*description: */
714 #define SLC_CMD_DTC_INT_CLR  (BIT(25))
715 #define SLC_CMD_DTC_INT_CLR_M  (BIT(25))
716 #define SLC_CMD_DTC_INT_CLR_V  0x1
717 #define SLC_CMD_DTC_INT_CLR_S  25
718 /* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
719 /*description: */
720 #define SLC_SLC0_TX_ERR_EOF_INT_CLR  (BIT(24))
721 #define SLC_SLC0_TX_ERR_EOF_INT_CLR_M  (BIT(24))
722 #define SLC_SLC0_TX_ERR_EOF_INT_CLR_V  0x1
723 #define SLC_SLC0_TX_ERR_EOF_INT_CLR_S  24
724 /* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
725 /*description: */
726 #define SLC_SLC0_WR_RETRY_DONE_INT_CLR  (BIT(23))
727 #define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M  (BIT(23))
728 #define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V  0x1
729 #define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S  23
730 /* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
731 /*description: */
732 #define SLC_SLC0_HOST_RD_ACK_INT_CLR  (BIT(22))
733 #define SLC_SLC0_HOST_RD_ACK_INT_CLR_M  (BIT(22))
734 #define SLC_SLC0_HOST_RD_ACK_INT_CLR_V  0x1
735 #define SLC_SLC0_HOST_RD_ACK_INT_CLR_S  22
736 /* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
737 /*description: */
738 #define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR  (BIT(21))
739 #define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (BIT(21))
740 #define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x1
741 #define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
742 /* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
743 /*description: */
744 #define SLC_SLC0_RX_DSCR_ERR_INT_CLR  (BIT(20))
745 #define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M  (BIT(20))
746 #define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V  0x1
747 #define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S  20
748 /* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
749 /*description: */
750 #define SLC_SLC0_TX_DSCR_ERR_INT_CLR  (BIT(19))
751 #define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M  (BIT(19))
752 #define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V  0x1
753 #define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S  19
754 /* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
755 /*description: */
756 #define SLC_SLC0_TOHOST_INT_CLR  (BIT(18))
757 #define SLC_SLC0_TOHOST_INT_CLR_M  (BIT(18))
758 #define SLC_SLC0_TOHOST_INT_CLR_V  0x1
759 #define SLC_SLC0_TOHOST_INT_CLR_S  18
760 /* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
761 /*description: */
762 #define SLC_SLC0_RX_EOF_INT_CLR  (BIT(17))
763 #define SLC_SLC0_RX_EOF_INT_CLR_M  (BIT(17))
764 #define SLC_SLC0_RX_EOF_INT_CLR_V  0x1
765 #define SLC_SLC0_RX_EOF_INT_CLR_S  17
766 /* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
767 /*description: */
768 #define SLC_SLC0_RX_DONE_INT_CLR  (BIT(16))
769 #define SLC_SLC0_RX_DONE_INT_CLR_M  (BIT(16))
770 #define SLC_SLC0_RX_DONE_INT_CLR_V  0x1
771 #define SLC_SLC0_RX_DONE_INT_CLR_S  16
772 /* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
773 /*description: */
774 #define SLC_SLC0_TX_SUC_EOF_INT_CLR  (BIT(15))
775 #define SLC_SLC0_TX_SUC_EOF_INT_CLR_M  (BIT(15))
776 #define SLC_SLC0_TX_SUC_EOF_INT_CLR_V  0x1
777 #define SLC_SLC0_TX_SUC_EOF_INT_CLR_S  15
778 /* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
779 /*description: */
780 #define SLC_SLC0_TX_DONE_INT_CLR  (BIT(14))
781 #define SLC_SLC0_TX_DONE_INT_CLR_M  (BIT(14))
782 #define SLC_SLC0_TX_DONE_INT_CLR_V  0x1
783 #define SLC_SLC0_TX_DONE_INT_CLR_S  14
784 /* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
785 /*description: */
786 #define SLC_SLC0_TOKEN1_1TO0_INT_CLR  (BIT(13))
787 #define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(13))
788 #define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
789 #define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S  13
790 /* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
791 /*description: */
792 #define SLC_SLC0_TOKEN0_1TO0_INT_CLR  (BIT(12))
793 #define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(12))
794 #define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
795 #define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S  12
796 /* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
797 /*description: */
798 #define SLC_SLC0_TX_OVF_INT_CLR  (BIT(11))
799 #define SLC_SLC0_TX_OVF_INT_CLR_M  (BIT(11))
800 #define SLC_SLC0_TX_OVF_INT_CLR_V  0x1
801 #define SLC_SLC0_TX_OVF_INT_CLR_S  11
802 /* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
803 /*description: */
804 #define SLC_SLC0_RX_UDF_INT_CLR  (BIT(10))
805 #define SLC_SLC0_RX_UDF_INT_CLR_M  (BIT(10))
806 #define SLC_SLC0_RX_UDF_INT_CLR_V  0x1
807 #define SLC_SLC0_RX_UDF_INT_CLR_S  10
808 /* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
809 /*description: */
810 #define SLC_SLC0_TX_START_INT_CLR  (BIT(9))
811 #define SLC_SLC0_TX_START_INT_CLR_M  (BIT(9))
812 #define SLC_SLC0_TX_START_INT_CLR_V  0x1
813 #define SLC_SLC0_TX_START_INT_CLR_S  9
814 /* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
815 /*description: */
816 #define SLC_SLC0_RX_START_INT_CLR  (BIT(8))
817 #define SLC_SLC0_RX_START_INT_CLR_M  (BIT(8))
818 #define SLC_SLC0_RX_START_INT_CLR_V  0x1
819 #define SLC_SLC0_RX_START_INT_CLR_S  8
820 /* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
821 /*description: */
822 #define SLC_FRHOST_BIT7_INT_CLR  (BIT(7))
823 #define SLC_FRHOST_BIT7_INT_CLR_M  (BIT(7))
824 #define SLC_FRHOST_BIT7_INT_CLR_V  0x1
825 #define SLC_FRHOST_BIT7_INT_CLR_S  7
826 /* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
827 /*description: */
828 #define SLC_FRHOST_BIT6_INT_CLR  (BIT(6))
829 #define SLC_FRHOST_BIT6_INT_CLR_M  (BIT(6))
830 #define SLC_FRHOST_BIT6_INT_CLR_V  0x1
831 #define SLC_FRHOST_BIT6_INT_CLR_S  6
832 /* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
833 /*description: */
834 #define SLC_FRHOST_BIT5_INT_CLR  (BIT(5))
835 #define SLC_FRHOST_BIT5_INT_CLR_M  (BIT(5))
836 #define SLC_FRHOST_BIT5_INT_CLR_V  0x1
837 #define SLC_FRHOST_BIT5_INT_CLR_S  5
838 /* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
839 /*description: */
840 #define SLC_FRHOST_BIT4_INT_CLR  (BIT(4))
841 #define SLC_FRHOST_BIT4_INT_CLR_M  (BIT(4))
842 #define SLC_FRHOST_BIT4_INT_CLR_V  0x1
843 #define SLC_FRHOST_BIT4_INT_CLR_S  4
844 /* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
845 /*description: */
846 #define SLC_FRHOST_BIT3_INT_CLR  (BIT(3))
847 #define SLC_FRHOST_BIT3_INT_CLR_M  (BIT(3))
848 #define SLC_FRHOST_BIT3_INT_CLR_V  0x1
849 #define SLC_FRHOST_BIT3_INT_CLR_S  3
850 /* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
851 /*description: */
852 #define SLC_FRHOST_BIT2_INT_CLR  (BIT(2))
853 #define SLC_FRHOST_BIT2_INT_CLR_M  (BIT(2))
854 #define SLC_FRHOST_BIT2_INT_CLR_V  0x1
855 #define SLC_FRHOST_BIT2_INT_CLR_S  2
856 /* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
857 /*description: */
858 #define SLC_FRHOST_BIT1_INT_CLR  (BIT(1))
859 #define SLC_FRHOST_BIT1_INT_CLR_M  (BIT(1))
860 #define SLC_FRHOST_BIT1_INT_CLR_V  0x1
861 #define SLC_FRHOST_BIT1_INT_CLR_S  1
862 /* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
863 /*description: */
864 #define SLC_FRHOST_BIT0_INT_CLR  (BIT(0))
865 #define SLC_FRHOST_BIT0_INT_CLR_M  (BIT(0))
866 #define SLC_FRHOST_BIT0_INT_CLR_V  0x1
867 #define SLC_FRHOST_BIT0_INT_CLR_S  0
868 
869 #define SLC_1INT_RAW_REG          (DR_REG_SLC_BASE + 0x14)
870 /* SLC_SLC1_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
871 /*description: */
872 #define SLC_SLC1_TX_ERR_EOF_INT_RAW  (BIT(24))
873 #define SLC_SLC1_TX_ERR_EOF_INT_RAW_M  (BIT(24))
874 #define SLC_SLC1_TX_ERR_EOF_INT_RAW_V  0x1
875 #define SLC_SLC1_TX_ERR_EOF_INT_RAW_S  24
876 /* SLC_SLC1_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
877 /*description: */
878 #define SLC_SLC1_WR_RETRY_DONE_INT_RAW  (BIT(23))
879 #define SLC_SLC1_WR_RETRY_DONE_INT_RAW_M  (BIT(23))
880 #define SLC_SLC1_WR_RETRY_DONE_INT_RAW_V  0x1
881 #define SLC_SLC1_WR_RETRY_DONE_INT_RAW_S  23
882 /* SLC_SLC1_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
883 /*description: */
884 #define SLC_SLC1_HOST_RD_ACK_INT_RAW  (BIT(22))
885 #define SLC_SLC1_HOST_RD_ACK_INT_RAW_M  (BIT(22))
886 #define SLC_SLC1_HOST_RD_ACK_INT_RAW_V  0x1
887 #define SLC_SLC1_HOST_RD_ACK_INT_RAW_S  22
888 /* SLC_SLC1_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
889 /*description: */
890 #define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW  (BIT(21))
891 #define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_M  (BIT(21))
892 #define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_V  0x1
893 #define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_S  21
894 /* SLC_SLC1_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
895 /*description: */
896 #define SLC_SLC1_RX_DSCR_ERR_INT_RAW  (BIT(20))
897 #define SLC_SLC1_RX_DSCR_ERR_INT_RAW_M  (BIT(20))
898 #define SLC_SLC1_RX_DSCR_ERR_INT_RAW_V  0x1
899 #define SLC_SLC1_RX_DSCR_ERR_INT_RAW_S  20
900 /* SLC_SLC1_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
901 /*description: */
902 #define SLC_SLC1_TX_DSCR_ERR_INT_RAW  (BIT(19))
903 #define SLC_SLC1_TX_DSCR_ERR_INT_RAW_M  (BIT(19))
904 #define SLC_SLC1_TX_DSCR_ERR_INT_RAW_V  0x1
905 #define SLC_SLC1_TX_DSCR_ERR_INT_RAW_S  19
906 /* SLC_SLC1_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
907 /*description: */
908 #define SLC_SLC1_TOHOST_INT_RAW  (BIT(18))
909 #define SLC_SLC1_TOHOST_INT_RAW_M  (BIT(18))
910 #define SLC_SLC1_TOHOST_INT_RAW_V  0x1
911 #define SLC_SLC1_TOHOST_INT_RAW_S  18
912 /* SLC_SLC1_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
913 /*description: */
914 #define SLC_SLC1_RX_EOF_INT_RAW  (BIT(17))
915 #define SLC_SLC1_RX_EOF_INT_RAW_M  (BIT(17))
916 #define SLC_SLC1_RX_EOF_INT_RAW_V  0x1
917 #define SLC_SLC1_RX_EOF_INT_RAW_S  17
918 /* SLC_SLC1_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
919 /*description: */
920 #define SLC_SLC1_RX_DONE_INT_RAW  (BIT(16))
921 #define SLC_SLC1_RX_DONE_INT_RAW_M  (BIT(16))
922 #define SLC_SLC1_RX_DONE_INT_RAW_V  0x1
923 #define SLC_SLC1_RX_DONE_INT_RAW_S  16
924 /* SLC_SLC1_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
925 /*description: */
926 #define SLC_SLC1_TX_SUC_EOF_INT_RAW  (BIT(15))
927 #define SLC_SLC1_TX_SUC_EOF_INT_RAW_M  (BIT(15))
928 #define SLC_SLC1_TX_SUC_EOF_INT_RAW_V  0x1
929 #define SLC_SLC1_TX_SUC_EOF_INT_RAW_S  15
930 /* SLC_SLC1_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
931 /*description: */
932 #define SLC_SLC1_TX_DONE_INT_RAW  (BIT(14))
933 #define SLC_SLC1_TX_DONE_INT_RAW_M  (BIT(14))
934 #define SLC_SLC1_TX_DONE_INT_RAW_V  0x1
935 #define SLC_SLC1_TX_DONE_INT_RAW_S  14
936 /* SLC_SLC1_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
937 /*description: */
938 #define SLC_SLC1_TOKEN1_1TO0_INT_RAW  (BIT(13))
939 #define SLC_SLC1_TOKEN1_1TO0_INT_RAW_M  (BIT(13))
940 #define SLC_SLC1_TOKEN1_1TO0_INT_RAW_V  0x1
941 #define SLC_SLC1_TOKEN1_1TO0_INT_RAW_S  13
942 /* SLC_SLC1_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
943 /*description: */
944 #define SLC_SLC1_TOKEN0_1TO0_INT_RAW  (BIT(12))
945 #define SLC_SLC1_TOKEN0_1TO0_INT_RAW_M  (BIT(12))
946 #define SLC_SLC1_TOKEN0_1TO0_INT_RAW_V  0x1
947 #define SLC_SLC1_TOKEN0_1TO0_INT_RAW_S  12
948 /* SLC_SLC1_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
949 /*description: */
950 #define SLC_SLC1_TX_OVF_INT_RAW  (BIT(11))
951 #define SLC_SLC1_TX_OVF_INT_RAW_M  (BIT(11))
952 #define SLC_SLC1_TX_OVF_INT_RAW_V  0x1
953 #define SLC_SLC1_TX_OVF_INT_RAW_S  11
954 /* SLC_SLC1_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
955 /*description: */
956 #define SLC_SLC1_RX_UDF_INT_RAW  (BIT(10))
957 #define SLC_SLC1_RX_UDF_INT_RAW_M  (BIT(10))
958 #define SLC_SLC1_RX_UDF_INT_RAW_V  0x1
959 #define SLC_SLC1_RX_UDF_INT_RAW_S  10
960 /* SLC_SLC1_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
961 /*description: */
962 #define SLC_SLC1_TX_START_INT_RAW  (BIT(9))
963 #define SLC_SLC1_TX_START_INT_RAW_M  (BIT(9))
964 #define SLC_SLC1_TX_START_INT_RAW_V  0x1
965 #define SLC_SLC1_TX_START_INT_RAW_S  9
966 /* SLC_SLC1_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
967 /*description: */
968 #define SLC_SLC1_RX_START_INT_RAW  (BIT(8))
969 #define SLC_SLC1_RX_START_INT_RAW_M  (BIT(8))
970 #define SLC_SLC1_RX_START_INT_RAW_V  0x1
971 #define SLC_SLC1_RX_START_INT_RAW_S  8
972 /* SLC_FRHOST_BIT15_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
973 /*description: */
974 #define SLC_FRHOST_BIT15_INT_RAW  (BIT(7))
975 #define SLC_FRHOST_BIT15_INT_RAW_M  (BIT(7))
976 #define SLC_FRHOST_BIT15_INT_RAW_V  0x1
977 #define SLC_FRHOST_BIT15_INT_RAW_S  7
978 /* SLC_FRHOST_BIT14_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
979 /*description: */
980 #define SLC_FRHOST_BIT14_INT_RAW  (BIT(6))
981 #define SLC_FRHOST_BIT14_INT_RAW_M  (BIT(6))
982 #define SLC_FRHOST_BIT14_INT_RAW_V  0x1
983 #define SLC_FRHOST_BIT14_INT_RAW_S  6
984 /* SLC_FRHOST_BIT13_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
985 /*description: */
986 #define SLC_FRHOST_BIT13_INT_RAW  (BIT(5))
987 #define SLC_FRHOST_BIT13_INT_RAW_M  (BIT(5))
988 #define SLC_FRHOST_BIT13_INT_RAW_V  0x1
989 #define SLC_FRHOST_BIT13_INT_RAW_S  5
990 /* SLC_FRHOST_BIT12_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
991 /*description: */
992 #define SLC_FRHOST_BIT12_INT_RAW  (BIT(4))
993 #define SLC_FRHOST_BIT12_INT_RAW_M  (BIT(4))
994 #define SLC_FRHOST_BIT12_INT_RAW_V  0x1
995 #define SLC_FRHOST_BIT12_INT_RAW_S  4
996 /* SLC_FRHOST_BIT11_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
997 /*description: */
998 #define SLC_FRHOST_BIT11_INT_RAW  (BIT(3))
999 #define SLC_FRHOST_BIT11_INT_RAW_M  (BIT(3))
1000 #define SLC_FRHOST_BIT11_INT_RAW_V  0x1
1001 #define SLC_FRHOST_BIT11_INT_RAW_S  3
1002 /* SLC_FRHOST_BIT10_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
1003 /*description: */
1004 #define SLC_FRHOST_BIT10_INT_RAW  (BIT(2))
1005 #define SLC_FRHOST_BIT10_INT_RAW_M  (BIT(2))
1006 #define SLC_FRHOST_BIT10_INT_RAW_V  0x1
1007 #define SLC_FRHOST_BIT10_INT_RAW_S  2
1008 /* SLC_FRHOST_BIT9_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
1009 /*description: */
1010 #define SLC_FRHOST_BIT9_INT_RAW  (BIT(1))
1011 #define SLC_FRHOST_BIT9_INT_RAW_M  (BIT(1))
1012 #define SLC_FRHOST_BIT9_INT_RAW_V  0x1
1013 #define SLC_FRHOST_BIT9_INT_RAW_S  1
1014 /* SLC_FRHOST_BIT8_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
1015 /*description: */
1016 #define SLC_FRHOST_BIT8_INT_RAW  (BIT(0))
1017 #define SLC_FRHOST_BIT8_INT_RAW_M  (BIT(0))
1018 #define SLC_FRHOST_BIT8_INT_RAW_V  0x1
1019 #define SLC_FRHOST_BIT8_INT_RAW_S  0
1020 
1021 #define SLC_1INT_ST_REG          (DR_REG_SLC_BASE + 0x18)
1022 /* SLC_SLC1_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
1023 /*description: */
1024 #define SLC_SLC1_TX_ERR_EOF_INT_ST  (BIT(24))
1025 #define SLC_SLC1_TX_ERR_EOF_INT_ST_M  (BIT(24))
1026 #define SLC_SLC1_TX_ERR_EOF_INT_ST_V  0x1
1027 #define SLC_SLC1_TX_ERR_EOF_INT_ST_S  24
1028 /* SLC_SLC1_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
1029 /*description: */
1030 #define SLC_SLC1_WR_RETRY_DONE_INT_ST  (BIT(23))
1031 #define SLC_SLC1_WR_RETRY_DONE_INT_ST_M  (BIT(23))
1032 #define SLC_SLC1_WR_RETRY_DONE_INT_ST_V  0x1
1033 #define SLC_SLC1_WR_RETRY_DONE_INT_ST_S  23
1034 /* SLC_SLC1_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
1035 /*description: */
1036 #define SLC_SLC1_HOST_RD_ACK_INT_ST  (BIT(22))
1037 #define SLC_SLC1_HOST_RD_ACK_INT_ST_M  (BIT(22))
1038 #define SLC_SLC1_HOST_RD_ACK_INT_ST_V  0x1
1039 #define SLC_SLC1_HOST_RD_ACK_INT_ST_S  22
1040 /* SLC_SLC1_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
1041 /*description: */
1042 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST  (BIT(21))
1043 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_M  (BIT(21))
1044 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_V  0x1
1045 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_S  21
1046 /* SLC_SLC1_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
1047 /*description: */
1048 #define SLC_SLC1_RX_DSCR_ERR_INT_ST  (BIT(20))
1049 #define SLC_SLC1_RX_DSCR_ERR_INT_ST_M  (BIT(20))
1050 #define SLC_SLC1_RX_DSCR_ERR_INT_ST_V  0x1
1051 #define SLC_SLC1_RX_DSCR_ERR_INT_ST_S  20
1052 /* SLC_SLC1_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
1053 /*description: */
1054 #define SLC_SLC1_TX_DSCR_ERR_INT_ST  (BIT(19))
1055 #define SLC_SLC1_TX_DSCR_ERR_INT_ST_M  (BIT(19))
1056 #define SLC_SLC1_TX_DSCR_ERR_INT_ST_V  0x1
1057 #define SLC_SLC1_TX_DSCR_ERR_INT_ST_S  19
1058 /* SLC_SLC1_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
1059 /*description: */
1060 #define SLC_SLC1_TOHOST_INT_ST  (BIT(18))
1061 #define SLC_SLC1_TOHOST_INT_ST_M  (BIT(18))
1062 #define SLC_SLC1_TOHOST_INT_ST_V  0x1
1063 #define SLC_SLC1_TOHOST_INT_ST_S  18
1064 /* SLC_SLC1_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
1065 /*description: */
1066 #define SLC_SLC1_RX_EOF_INT_ST  (BIT(17))
1067 #define SLC_SLC1_RX_EOF_INT_ST_M  (BIT(17))
1068 #define SLC_SLC1_RX_EOF_INT_ST_V  0x1
1069 #define SLC_SLC1_RX_EOF_INT_ST_S  17
1070 /* SLC_SLC1_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
1071 /*description: */
1072 #define SLC_SLC1_RX_DONE_INT_ST  (BIT(16))
1073 #define SLC_SLC1_RX_DONE_INT_ST_M  (BIT(16))
1074 #define SLC_SLC1_RX_DONE_INT_ST_V  0x1
1075 #define SLC_SLC1_RX_DONE_INT_ST_S  16
1076 /* SLC_SLC1_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
1077 /*description: */
1078 #define SLC_SLC1_TX_SUC_EOF_INT_ST  (BIT(15))
1079 #define SLC_SLC1_TX_SUC_EOF_INT_ST_M  (BIT(15))
1080 #define SLC_SLC1_TX_SUC_EOF_INT_ST_V  0x1
1081 #define SLC_SLC1_TX_SUC_EOF_INT_ST_S  15
1082 /* SLC_SLC1_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
1083 /*description: */
1084 #define SLC_SLC1_TX_DONE_INT_ST  (BIT(14))
1085 #define SLC_SLC1_TX_DONE_INT_ST_M  (BIT(14))
1086 #define SLC_SLC1_TX_DONE_INT_ST_V  0x1
1087 #define SLC_SLC1_TX_DONE_INT_ST_S  14
1088 /* SLC_SLC1_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
1089 /*description: */
1090 #define SLC_SLC1_TOKEN1_1TO0_INT_ST  (BIT(13))
1091 #define SLC_SLC1_TOKEN1_1TO0_INT_ST_M  (BIT(13))
1092 #define SLC_SLC1_TOKEN1_1TO0_INT_ST_V  0x1
1093 #define SLC_SLC1_TOKEN1_1TO0_INT_ST_S  13
1094 /* SLC_SLC1_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
1095 /*description: */
1096 #define SLC_SLC1_TOKEN0_1TO0_INT_ST  (BIT(12))
1097 #define SLC_SLC1_TOKEN0_1TO0_INT_ST_M  (BIT(12))
1098 #define SLC_SLC1_TOKEN0_1TO0_INT_ST_V  0x1
1099 #define SLC_SLC1_TOKEN0_1TO0_INT_ST_S  12
1100 /* SLC_SLC1_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
1101 /*description: */
1102 #define SLC_SLC1_TX_OVF_INT_ST  (BIT(11))
1103 #define SLC_SLC1_TX_OVF_INT_ST_M  (BIT(11))
1104 #define SLC_SLC1_TX_OVF_INT_ST_V  0x1
1105 #define SLC_SLC1_TX_OVF_INT_ST_S  11
1106 /* SLC_SLC1_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
1107 /*description: */
1108 #define SLC_SLC1_RX_UDF_INT_ST  (BIT(10))
1109 #define SLC_SLC1_RX_UDF_INT_ST_M  (BIT(10))
1110 #define SLC_SLC1_RX_UDF_INT_ST_V  0x1
1111 #define SLC_SLC1_RX_UDF_INT_ST_S  10
1112 /* SLC_SLC1_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
1113 /*description: */
1114 #define SLC_SLC1_TX_START_INT_ST  (BIT(9))
1115 #define SLC_SLC1_TX_START_INT_ST_M  (BIT(9))
1116 #define SLC_SLC1_TX_START_INT_ST_V  0x1
1117 #define SLC_SLC1_TX_START_INT_ST_S  9
1118 /* SLC_SLC1_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
1119 /*description: */
1120 #define SLC_SLC1_RX_START_INT_ST  (BIT(8))
1121 #define SLC_SLC1_RX_START_INT_ST_M  (BIT(8))
1122 #define SLC_SLC1_RX_START_INT_ST_V  0x1
1123 #define SLC_SLC1_RX_START_INT_ST_S  8
1124 /* SLC_FRHOST_BIT15_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
1125 /*description: */
1126 #define SLC_FRHOST_BIT15_INT_ST  (BIT(7))
1127 #define SLC_FRHOST_BIT15_INT_ST_M  (BIT(7))
1128 #define SLC_FRHOST_BIT15_INT_ST_V  0x1
1129 #define SLC_FRHOST_BIT15_INT_ST_S  7
1130 /* SLC_FRHOST_BIT14_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
1131 /*description: */
1132 #define SLC_FRHOST_BIT14_INT_ST  (BIT(6))
1133 #define SLC_FRHOST_BIT14_INT_ST_M  (BIT(6))
1134 #define SLC_FRHOST_BIT14_INT_ST_V  0x1
1135 #define SLC_FRHOST_BIT14_INT_ST_S  6
1136 /* SLC_FRHOST_BIT13_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
1137 /*description: */
1138 #define SLC_FRHOST_BIT13_INT_ST  (BIT(5))
1139 #define SLC_FRHOST_BIT13_INT_ST_M  (BIT(5))
1140 #define SLC_FRHOST_BIT13_INT_ST_V  0x1
1141 #define SLC_FRHOST_BIT13_INT_ST_S  5
1142 /* SLC_FRHOST_BIT12_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
1143 /*description: */
1144 #define SLC_FRHOST_BIT12_INT_ST  (BIT(4))
1145 #define SLC_FRHOST_BIT12_INT_ST_M  (BIT(4))
1146 #define SLC_FRHOST_BIT12_INT_ST_V  0x1
1147 #define SLC_FRHOST_BIT12_INT_ST_S  4
1148 /* SLC_FRHOST_BIT11_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
1149 /*description: */
1150 #define SLC_FRHOST_BIT11_INT_ST  (BIT(3))
1151 #define SLC_FRHOST_BIT11_INT_ST_M  (BIT(3))
1152 #define SLC_FRHOST_BIT11_INT_ST_V  0x1
1153 #define SLC_FRHOST_BIT11_INT_ST_S  3
1154 /* SLC_FRHOST_BIT10_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
1155 /*description: */
1156 #define SLC_FRHOST_BIT10_INT_ST  (BIT(2))
1157 #define SLC_FRHOST_BIT10_INT_ST_M  (BIT(2))
1158 #define SLC_FRHOST_BIT10_INT_ST_V  0x1
1159 #define SLC_FRHOST_BIT10_INT_ST_S  2
1160 /* SLC_FRHOST_BIT9_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
1161 /*description: */
1162 #define SLC_FRHOST_BIT9_INT_ST  (BIT(1))
1163 #define SLC_FRHOST_BIT9_INT_ST_M  (BIT(1))
1164 #define SLC_FRHOST_BIT9_INT_ST_V  0x1
1165 #define SLC_FRHOST_BIT9_INT_ST_S  1
1166 /* SLC_FRHOST_BIT8_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
1167 /*description: */
1168 #define SLC_FRHOST_BIT8_INT_ST  (BIT(0))
1169 #define SLC_FRHOST_BIT8_INT_ST_M  (BIT(0))
1170 #define SLC_FRHOST_BIT8_INT_ST_V  0x1
1171 #define SLC_FRHOST_BIT8_INT_ST_S  0
1172 
1173 #define SLC_1INT_ENA_REG          (DR_REG_SLC_BASE + 0x1C)
1174 /* SLC_SLC1_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
1175 /*description: */
1176 #define SLC_SLC1_TX_ERR_EOF_INT_ENA  (BIT(24))
1177 #define SLC_SLC1_TX_ERR_EOF_INT_ENA_M  (BIT(24))
1178 #define SLC_SLC1_TX_ERR_EOF_INT_ENA_V  0x1
1179 #define SLC_SLC1_TX_ERR_EOF_INT_ENA_S  24
1180 /* SLC_SLC1_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
1181 /*description: */
1182 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA  (BIT(23))
1183 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA_M  (BIT(23))
1184 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA_V  0x1
1185 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA_S  23
1186 /* SLC_SLC1_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
1187 /*description: */
1188 #define SLC_SLC1_HOST_RD_ACK_INT_ENA  (BIT(22))
1189 #define SLC_SLC1_HOST_RD_ACK_INT_ENA_M  (BIT(22))
1190 #define SLC_SLC1_HOST_RD_ACK_INT_ENA_V  0x1
1191 #define SLC_SLC1_HOST_RD_ACK_INT_ENA_S  22
1192 /* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
1193 /*description: */
1194 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA  (BIT(21))
1195 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_M  (BIT(21))
1196 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_V  0x1
1197 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_S  21
1198 /* SLC_SLC1_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
1199 /*description: */
1200 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA  (BIT(20))
1201 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA_M  (BIT(20))
1202 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA_V  0x1
1203 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA_S  20
1204 /* SLC_SLC1_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
1205 /*description: */
1206 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA  (BIT(19))
1207 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA_M  (BIT(19))
1208 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA_V  0x1
1209 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA_S  19
1210 /* SLC_SLC1_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
1211 /*description: */
1212 #define SLC_SLC1_TOHOST_INT_ENA  (BIT(18))
1213 #define SLC_SLC1_TOHOST_INT_ENA_M  (BIT(18))
1214 #define SLC_SLC1_TOHOST_INT_ENA_V  0x1
1215 #define SLC_SLC1_TOHOST_INT_ENA_S  18
1216 /* SLC_SLC1_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
1217 /*description: */
1218 #define SLC_SLC1_RX_EOF_INT_ENA  (BIT(17))
1219 #define SLC_SLC1_RX_EOF_INT_ENA_M  (BIT(17))
1220 #define SLC_SLC1_RX_EOF_INT_ENA_V  0x1
1221 #define SLC_SLC1_RX_EOF_INT_ENA_S  17
1222 /* SLC_SLC1_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
1223 /*description: */
1224 #define SLC_SLC1_RX_DONE_INT_ENA  (BIT(16))
1225 #define SLC_SLC1_RX_DONE_INT_ENA_M  (BIT(16))
1226 #define SLC_SLC1_RX_DONE_INT_ENA_V  0x1
1227 #define SLC_SLC1_RX_DONE_INT_ENA_S  16
1228 /* SLC_SLC1_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
1229 /*description: */
1230 #define SLC_SLC1_TX_SUC_EOF_INT_ENA  (BIT(15))
1231 #define SLC_SLC1_TX_SUC_EOF_INT_ENA_M  (BIT(15))
1232 #define SLC_SLC1_TX_SUC_EOF_INT_ENA_V  0x1
1233 #define SLC_SLC1_TX_SUC_EOF_INT_ENA_S  15
1234 /* SLC_SLC1_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
1235 /*description: */
1236 #define SLC_SLC1_TX_DONE_INT_ENA  (BIT(14))
1237 #define SLC_SLC1_TX_DONE_INT_ENA_M  (BIT(14))
1238 #define SLC_SLC1_TX_DONE_INT_ENA_V  0x1
1239 #define SLC_SLC1_TX_DONE_INT_ENA_S  14
1240 /* SLC_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
1241 /*description: */
1242 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA  (BIT(13))
1243 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA_M  (BIT(13))
1244 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA_V  0x1
1245 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA_S  13
1246 /* SLC_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
1247 /*description: */
1248 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA  (BIT(12))
1249 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA_M  (BIT(12))
1250 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA_V  0x1
1251 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA_S  12
1252 /* SLC_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
1253 /*description: */
1254 #define SLC_SLC1_TX_OVF_INT_ENA  (BIT(11))
1255 #define SLC_SLC1_TX_OVF_INT_ENA_M  (BIT(11))
1256 #define SLC_SLC1_TX_OVF_INT_ENA_V  0x1
1257 #define SLC_SLC1_TX_OVF_INT_ENA_S  11
1258 /* SLC_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
1259 /*description: */
1260 #define SLC_SLC1_RX_UDF_INT_ENA  (BIT(10))
1261 #define SLC_SLC1_RX_UDF_INT_ENA_M  (BIT(10))
1262 #define SLC_SLC1_RX_UDF_INT_ENA_V  0x1
1263 #define SLC_SLC1_RX_UDF_INT_ENA_S  10
1264 /* SLC_SLC1_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
1265 /*description: */
1266 #define SLC_SLC1_TX_START_INT_ENA  (BIT(9))
1267 #define SLC_SLC1_TX_START_INT_ENA_M  (BIT(9))
1268 #define SLC_SLC1_TX_START_INT_ENA_V  0x1
1269 #define SLC_SLC1_TX_START_INT_ENA_S  9
1270 /* SLC_SLC1_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
1271 /*description: */
1272 #define SLC_SLC1_RX_START_INT_ENA  (BIT(8))
1273 #define SLC_SLC1_RX_START_INT_ENA_M  (BIT(8))
1274 #define SLC_SLC1_RX_START_INT_ENA_V  0x1
1275 #define SLC_SLC1_RX_START_INT_ENA_S  8
1276 /* SLC_FRHOST_BIT15_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
1277 /*description: */
1278 #define SLC_FRHOST_BIT15_INT_ENA  (BIT(7))
1279 #define SLC_FRHOST_BIT15_INT_ENA_M  (BIT(7))
1280 #define SLC_FRHOST_BIT15_INT_ENA_V  0x1
1281 #define SLC_FRHOST_BIT15_INT_ENA_S  7
1282 /* SLC_FRHOST_BIT14_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
1283 /*description: */
1284 #define SLC_FRHOST_BIT14_INT_ENA  (BIT(6))
1285 #define SLC_FRHOST_BIT14_INT_ENA_M  (BIT(6))
1286 #define SLC_FRHOST_BIT14_INT_ENA_V  0x1
1287 #define SLC_FRHOST_BIT14_INT_ENA_S  6
1288 /* SLC_FRHOST_BIT13_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
1289 /*description: */
1290 #define SLC_FRHOST_BIT13_INT_ENA  (BIT(5))
1291 #define SLC_FRHOST_BIT13_INT_ENA_M  (BIT(5))
1292 #define SLC_FRHOST_BIT13_INT_ENA_V  0x1
1293 #define SLC_FRHOST_BIT13_INT_ENA_S  5
1294 /* SLC_FRHOST_BIT12_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
1295 /*description: */
1296 #define SLC_FRHOST_BIT12_INT_ENA  (BIT(4))
1297 #define SLC_FRHOST_BIT12_INT_ENA_M  (BIT(4))
1298 #define SLC_FRHOST_BIT12_INT_ENA_V  0x1
1299 #define SLC_FRHOST_BIT12_INT_ENA_S  4
1300 /* SLC_FRHOST_BIT11_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
1301 /*description: */
1302 #define SLC_FRHOST_BIT11_INT_ENA  (BIT(3))
1303 #define SLC_FRHOST_BIT11_INT_ENA_M  (BIT(3))
1304 #define SLC_FRHOST_BIT11_INT_ENA_V  0x1
1305 #define SLC_FRHOST_BIT11_INT_ENA_S  3
1306 /* SLC_FRHOST_BIT10_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
1307 /*description: */
1308 #define SLC_FRHOST_BIT10_INT_ENA  (BIT(2))
1309 #define SLC_FRHOST_BIT10_INT_ENA_M  (BIT(2))
1310 #define SLC_FRHOST_BIT10_INT_ENA_V  0x1
1311 #define SLC_FRHOST_BIT10_INT_ENA_S  2
1312 /* SLC_FRHOST_BIT9_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
1313 /*description: */
1314 #define SLC_FRHOST_BIT9_INT_ENA  (BIT(1))
1315 #define SLC_FRHOST_BIT9_INT_ENA_M  (BIT(1))
1316 #define SLC_FRHOST_BIT9_INT_ENA_V  0x1
1317 #define SLC_FRHOST_BIT9_INT_ENA_S  1
1318 /* SLC_FRHOST_BIT8_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
1319 /*description: */
1320 #define SLC_FRHOST_BIT8_INT_ENA  (BIT(0))
1321 #define SLC_FRHOST_BIT8_INT_ENA_M  (BIT(0))
1322 #define SLC_FRHOST_BIT8_INT_ENA_V  0x1
1323 #define SLC_FRHOST_BIT8_INT_ENA_S  0
1324 
1325 #define SLC_1INT_CLR_REG          (DR_REG_SLC_BASE + 0x20)
1326 /* SLC_SLC1_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
1327 /*description: */
1328 #define SLC_SLC1_TX_ERR_EOF_INT_CLR  (BIT(24))
1329 #define SLC_SLC1_TX_ERR_EOF_INT_CLR_M  (BIT(24))
1330 #define SLC_SLC1_TX_ERR_EOF_INT_CLR_V  0x1
1331 #define SLC_SLC1_TX_ERR_EOF_INT_CLR_S  24
1332 /* SLC_SLC1_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
1333 /*description: */
1334 #define SLC_SLC1_WR_RETRY_DONE_INT_CLR  (BIT(23))
1335 #define SLC_SLC1_WR_RETRY_DONE_INT_CLR_M  (BIT(23))
1336 #define SLC_SLC1_WR_RETRY_DONE_INT_CLR_V  0x1
1337 #define SLC_SLC1_WR_RETRY_DONE_INT_CLR_S  23
1338 /* SLC_SLC1_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
1339 /*description: */
1340 #define SLC_SLC1_HOST_RD_ACK_INT_CLR  (BIT(22))
1341 #define SLC_SLC1_HOST_RD_ACK_INT_CLR_M  (BIT(22))
1342 #define SLC_SLC1_HOST_RD_ACK_INT_CLR_V  0x1
1343 #define SLC_SLC1_HOST_RD_ACK_INT_CLR_S  22
1344 /* SLC_SLC1_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
1345 /*description: */
1346 #define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR  (BIT(21))
1347 #define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_M  (BIT(21))
1348 #define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_V  0x1
1349 #define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_S  21
1350 /* SLC_SLC1_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
1351 /*description: */
1352 #define SLC_SLC1_RX_DSCR_ERR_INT_CLR  (BIT(20))
1353 #define SLC_SLC1_RX_DSCR_ERR_INT_CLR_M  (BIT(20))
1354 #define SLC_SLC1_RX_DSCR_ERR_INT_CLR_V  0x1
1355 #define SLC_SLC1_RX_DSCR_ERR_INT_CLR_S  20
1356 /* SLC_SLC1_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
1357 /*description: */
1358 #define SLC_SLC1_TX_DSCR_ERR_INT_CLR  (BIT(19))
1359 #define SLC_SLC1_TX_DSCR_ERR_INT_CLR_M  (BIT(19))
1360 #define SLC_SLC1_TX_DSCR_ERR_INT_CLR_V  0x1
1361 #define SLC_SLC1_TX_DSCR_ERR_INT_CLR_S  19
1362 /* SLC_SLC1_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
1363 /*description: */
1364 #define SLC_SLC1_TOHOST_INT_CLR  (BIT(18))
1365 #define SLC_SLC1_TOHOST_INT_CLR_M  (BIT(18))
1366 #define SLC_SLC1_TOHOST_INT_CLR_V  0x1
1367 #define SLC_SLC1_TOHOST_INT_CLR_S  18
1368 /* SLC_SLC1_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
1369 /*description: */
1370 #define SLC_SLC1_RX_EOF_INT_CLR  (BIT(17))
1371 #define SLC_SLC1_RX_EOF_INT_CLR_M  (BIT(17))
1372 #define SLC_SLC1_RX_EOF_INT_CLR_V  0x1
1373 #define SLC_SLC1_RX_EOF_INT_CLR_S  17
1374 /* SLC_SLC1_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
1375 /*description: */
1376 #define SLC_SLC1_RX_DONE_INT_CLR  (BIT(16))
1377 #define SLC_SLC1_RX_DONE_INT_CLR_M  (BIT(16))
1378 #define SLC_SLC1_RX_DONE_INT_CLR_V  0x1
1379 #define SLC_SLC1_RX_DONE_INT_CLR_S  16
1380 /* SLC_SLC1_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
1381 /*description: */
1382 #define SLC_SLC1_TX_SUC_EOF_INT_CLR  (BIT(15))
1383 #define SLC_SLC1_TX_SUC_EOF_INT_CLR_M  (BIT(15))
1384 #define SLC_SLC1_TX_SUC_EOF_INT_CLR_V  0x1
1385 #define SLC_SLC1_TX_SUC_EOF_INT_CLR_S  15
1386 /* SLC_SLC1_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
1387 /*description: */
1388 #define SLC_SLC1_TX_DONE_INT_CLR  (BIT(14))
1389 #define SLC_SLC1_TX_DONE_INT_CLR_M  (BIT(14))
1390 #define SLC_SLC1_TX_DONE_INT_CLR_V  0x1
1391 #define SLC_SLC1_TX_DONE_INT_CLR_S  14
1392 /* SLC_SLC1_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
1393 /*description: */
1394 #define SLC_SLC1_TOKEN1_1TO0_INT_CLR  (BIT(13))
1395 #define SLC_SLC1_TOKEN1_1TO0_INT_CLR_M  (BIT(13))
1396 #define SLC_SLC1_TOKEN1_1TO0_INT_CLR_V  0x1
1397 #define SLC_SLC1_TOKEN1_1TO0_INT_CLR_S  13
1398 /* SLC_SLC1_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
1399 /*description: */
1400 #define SLC_SLC1_TOKEN0_1TO0_INT_CLR  (BIT(12))
1401 #define SLC_SLC1_TOKEN0_1TO0_INT_CLR_M  (BIT(12))
1402 #define SLC_SLC1_TOKEN0_1TO0_INT_CLR_V  0x1
1403 #define SLC_SLC1_TOKEN0_1TO0_INT_CLR_S  12
1404 /* SLC_SLC1_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
1405 /*description: */
1406 #define SLC_SLC1_TX_OVF_INT_CLR  (BIT(11))
1407 #define SLC_SLC1_TX_OVF_INT_CLR_M  (BIT(11))
1408 #define SLC_SLC1_TX_OVF_INT_CLR_V  0x1
1409 #define SLC_SLC1_TX_OVF_INT_CLR_S  11
1410 /* SLC_SLC1_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
1411 /*description: */
1412 #define SLC_SLC1_RX_UDF_INT_CLR  (BIT(10))
1413 #define SLC_SLC1_RX_UDF_INT_CLR_M  (BIT(10))
1414 #define SLC_SLC1_RX_UDF_INT_CLR_V  0x1
1415 #define SLC_SLC1_RX_UDF_INT_CLR_S  10
1416 /* SLC_SLC1_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
1417 /*description: */
1418 #define SLC_SLC1_TX_START_INT_CLR  (BIT(9))
1419 #define SLC_SLC1_TX_START_INT_CLR_M  (BIT(9))
1420 #define SLC_SLC1_TX_START_INT_CLR_V  0x1
1421 #define SLC_SLC1_TX_START_INT_CLR_S  9
1422 /* SLC_SLC1_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
1423 /*description: */
1424 #define SLC_SLC1_RX_START_INT_CLR  (BIT(8))
1425 #define SLC_SLC1_RX_START_INT_CLR_M  (BIT(8))
1426 #define SLC_SLC1_RX_START_INT_CLR_V  0x1
1427 #define SLC_SLC1_RX_START_INT_CLR_S  8
1428 /* SLC_FRHOST_BIT15_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
1429 /*description: */
1430 #define SLC_FRHOST_BIT15_INT_CLR  (BIT(7))
1431 #define SLC_FRHOST_BIT15_INT_CLR_M  (BIT(7))
1432 #define SLC_FRHOST_BIT15_INT_CLR_V  0x1
1433 #define SLC_FRHOST_BIT15_INT_CLR_S  7
1434 /* SLC_FRHOST_BIT14_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
1435 /*description: */
1436 #define SLC_FRHOST_BIT14_INT_CLR  (BIT(6))
1437 #define SLC_FRHOST_BIT14_INT_CLR_M  (BIT(6))
1438 #define SLC_FRHOST_BIT14_INT_CLR_V  0x1
1439 #define SLC_FRHOST_BIT14_INT_CLR_S  6
1440 /* SLC_FRHOST_BIT13_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
1441 /*description: */
1442 #define SLC_FRHOST_BIT13_INT_CLR  (BIT(5))
1443 #define SLC_FRHOST_BIT13_INT_CLR_M  (BIT(5))
1444 #define SLC_FRHOST_BIT13_INT_CLR_V  0x1
1445 #define SLC_FRHOST_BIT13_INT_CLR_S  5
1446 /* SLC_FRHOST_BIT12_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
1447 /*description: */
1448 #define SLC_FRHOST_BIT12_INT_CLR  (BIT(4))
1449 #define SLC_FRHOST_BIT12_INT_CLR_M  (BIT(4))
1450 #define SLC_FRHOST_BIT12_INT_CLR_V  0x1
1451 #define SLC_FRHOST_BIT12_INT_CLR_S  4
1452 /* SLC_FRHOST_BIT11_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
1453 /*description: */
1454 #define SLC_FRHOST_BIT11_INT_CLR  (BIT(3))
1455 #define SLC_FRHOST_BIT11_INT_CLR_M  (BIT(3))
1456 #define SLC_FRHOST_BIT11_INT_CLR_V  0x1
1457 #define SLC_FRHOST_BIT11_INT_CLR_S  3
1458 /* SLC_FRHOST_BIT10_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
1459 /*description: */
1460 #define SLC_FRHOST_BIT10_INT_CLR  (BIT(2))
1461 #define SLC_FRHOST_BIT10_INT_CLR_M  (BIT(2))
1462 #define SLC_FRHOST_BIT10_INT_CLR_V  0x1
1463 #define SLC_FRHOST_BIT10_INT_CLR_S  2
1464 /* SLC_FRHOST_BIT9_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
1465 /*description: */
1466 #define SLC_FRHOST_BIT9_INT_CLR  (BIT(1))
1467 #define SLC_FRHOST_BIT9_INT_CLR_M  (BIT(1))
1468 #define SLC_FRHOST_BIT9_INT_CLR_V  0x1
1469 #define SLC_FRHOST_BIT9_INT_CLR_S  1
1470 /* SLC_FRHOST_BIT8_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
1471 /*description: */
1472 #define SLC_FRHOST_BIT8_INT_CLR  (BIT(0))
1473 #define SLC_FRHOST_BIT8_INT_CLR_M  (BIT(0))
1474 #define SLC_FRHOST_BIT8_INT_CLR_V  0x1
1475 #define SLC_FRHOST_BIT8_INT_CLR_S  0
1476 
1477 #define SLC_RX_STATUS_REG          (DR_REG_SLC_BASE + 0x24)
1478 /* SLC_SLC1_RX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */
1479 /*description: */
1480 #define SLC_SLC1_RX_EMPTY  (BIT(17))
1481 #define SLC_SLC1_RX_EMPTY_M  (BIT(17))
1482 #define SLC_SLC1_RX_EMPTY_V  0x1
1483 #define SLC_SLC1_RX_EMPTY_S  17
1484 /* SLC_SLC1_RX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */
1485 /*description: */
1486 #define SLC_SLC1_RX_FULL  (BIT(16))
1487 #define SLC_SLC1_RX_FULL_M  (BIT(16))
1488 #define SLC_SLC1_RX_FULL_V  0x1
1489 #define SLC_SLC1_RX_FULL_S  16
1490 /* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
1491 /*description: */
1492 #define SLC_SLC0_RX_EMPTY  (BIT(1))
1493 #define SLC_SLC0_RX_EMPTY_M  (BIT(1))
1494 #define SLC_SLC0_RX_EMPTY_V  0x1
1495 #define SLC_SLC0_RX_EMPTY_S  1
1496 /* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
1497 /*description: */
1498 #define SLC_SLC0_RX_FULL  (BIT(0))
1499 #define SLC_SLC0_RX_FULL_M  (BIT(0))
1500 #define SLC_SLC0_RX_FULL_V  0x1
1501 #define SLC_SLC0_RX_FULL_S  0
1502 
1503 #define SLC_0RXFIFO_PUSH_REG          (DR_REG_SLC_BASE + 0x28)
1504 /* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
1505 /*description: */
1506 #define SLC_SLC0_RXFIFO_PUSH  (BIT(16))
1507 #define SLC_SLC0_RXFIFO_PUSH_M  (BIT(16))
1508 #define SLC_SLC0_RXFIFO_PUSH_V  0x1
1509 #define SLC_SLC0_RXFIFO_PUSH_S  16
1510 /* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
1511 /*description: */
1512 #define SLC_SLC0_RXFIFO_WDATA  0x000001FF
1513 #define SLC_SLC0_RXFIFO_WDATA_M  ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S))
1514 #define SLC_SLC0_RXFIFO_WDATA_V  0x1FF
1515 #define SLC_SLC0_RXFIFO_WDATA_S  0
1516 
1517 #define SLC_1RXFIFO_PUSH_REG          (DR_REG_SLC_BASE + 0x2C)
1518 /* SLC_SLC1_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
1519 /*description: */
1520 #define SLC_SLC1_RXFIFO_PUSH  (BIT(16))
1521 #define SLC_SLC1_RXFIFO_PUSH_M  (BIT(16))
1522 #define SLC_SLC1_RXFIFO_PUSH_V  0x1
1523 #define SLC_SLC1_RXFIFO_PUSH_S  16
1524 /* SLC_SLC1_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
1525 /*description: */
1526 #define SLC_SLC1_RXFIFO_WDATA  0x000001FF
1527 #define SLC_SLC1_RXFIFO_WDATA_M  ((SLC_SLC1_RXFIFO_WDATA_V)<<(SLC_SLC1_RXFIFO_WDATA_S))
1528 #define SLC_SLC1_RXFIFO_WDATA_V  0x1FF
1529 #define SLC_SLC1_RXFIFO_WDATA_S  0
1530 
1531 #define SLC_TX_STATUS_REG          (DR_REG_SLC_BASE + 0x30)
1532 /* SLC_SLC1_TX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */
1533 /*description: */
1534 #define SLC_SLC1_TX_EMPTY  (BIT(17))
1535 #define SLC_SLC1_TX_EMPTY_M  (BIT(17))
1536 #define SLC_SLC1_TX_EMPTY_V  0x1
1537 #define SLC_SLC1_TX_EMPTY_S  17
1538 /* SLC_SLC1_TX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */
1539 /*description: */
1540 #define SLC_SLC1_TX_FULL  (BIT(16))
1541 #define SLC_SLC1_TX_FULL_M  (BIT(16))
1542 #define SLC_SLC1_TX_FULL_V  0x1
1543 #define SLC_SLC1_TX_FULL_S  16
1544 /* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
1545 /*description: */
1546 #define SLC_SLC0_TX_EMPTY  (BIT(1))
1547 #define SLC_SLC0_TX_EMPTY_M  (BIT(1))
1548 #define SLC_SLC0_TX_EMPTY_V  0x1
1549 #define SLC_SLC0_TX_EMPTY_S  1
1550 /* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
1551 /*description: */
1552 #define SLC_SLC0_TX_FULL  (BIT(0))
1553 #define SLC_SLC0_TX_FULL_M  (BIT(0))
1554 #define SLC_SLC0_TX_FULL_V  0x1
1555 #define SLC_SLC0_TX_FULL_S  0
1556 
1557 #define SLC_0TXFIFO_POP_REG          (DR_REG_SLC_BASE + 0x34)
1558 /* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
1559 /*description: */
1560 #define SLC_SLC0_TXFIFO_POP  (BIT(16))
1561 #define SLC_SLC0_TXFIFO_POP_M  (BIT(16))
1562 #define SLC_SLC0_TXFIFO_POP_V  0x1
1563 #define SLC_SLC0_TXFIFO_POP_S  16
1564 /* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
1565 /*description: */
1566 #define SLC_SLC0_TXFIFO_RDATA  0x000007FF
1567 #define SLC_SLC0_TXFIFO_RDATA_M  ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S))
1568 #define SLC_SLC0_TXFIFO_RDATA_V  0x7FF
1569 #define SLC_SLC0_TXFIFO_RDATA_S  0
1570 
1571 #define SLC_1TXFIFO_POP_REG          (DR_REG_SLC_BASE + 0x38)
1572 /* SLC_SLC1_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
1573 /*description: */
1574 #define SLC_SLC1_TXFIFO_POP  (BIT(16))
1575 #define SLC_SLC1_TXFIFO_POP_M  (BIT(16))
1576 #define SLC_SLC1_TXFIFO_POP_V  0x1
1577 #define SLC_SLC1_TXFIFO_POP_S  16
1578 /* SLC_SLC1_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
1579 /*description: */
1580 #define SLC_SLC1_TXFIFO_RDATA  0x000007FF
1581 #define SLC_SLC1_TXFIFO_RDATA_M  ((SLC_SLC1_TXFIFO_RDATA_V)<<(SLC_SLC1_TXFIFO_RDATA_S))
1582 #define SLC_SLC1_TXFIFO_RDATA_V  0x7FF
1583 #define SLC_SLC1_TXFIFO_RDATA_S  0
1584 
1585 #define SLC_0RX_LINK_REG          (DR_REG_SLC_BASE + 0x3C)
1586 /* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
1587 /*description: */
1588 #define SLC_SLC0_RXLINK_PARK  (BIT(31))
1589 #define SLC_SLC0_RXLINK_PARK_M  (BIT(31))
1590 #define SLC_SLC0_RXLINK_PARK_V  0x1
1591 #define SLC_SLC0_RXLINK_PARK_S  31
1592 /* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
1593 /*description: */
1594 #define SLC_SLC0_RXLINK_RESTART  (BIT(30))
1595 #define SLC_SLC0_RXLINK_RESTART_M  (BIT(30))
1596 #define SLC_SLC0_RXLINK_RESTART_V  0x1
1597 #define SLC_SLC0_RXLINK_RESTART_S  30
1598 /* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
1599 /*description: */
1600 #define SLC_SLC0_RXLINK_START  (BIT(29))
1601 #define SLC_SLC0_RXLINK_START_M  (BIT(29))
1602 #define SLC_SLC0_RXLINK_START_V  0x1
1603 #define SLC_SLC0_RXLINK_START_S  29
1604 /* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
1605 /*description: */
1606 #define SLC_SLC0_RXLINK_STOP  (BIT(28))
1607 #define SLC_SLC0_RXLINK_STOP_M  (BIT(28))
1608 #define SLC_SLC0_RXLINK_STOP_V  0x1
1609 #define SLC_SLC0_RXLINK_STOP_S  28
1610 /* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
1611 /*description: */
1612 #define SLC_SLC0_RXLINK_ADDR  0x000FFFFF
1613 #define SLC_SLC0_RXLINK_ADDR_M  ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S))
1614 #define SLC_SLC0_RXLINK_ADDR_V  0xFFFFF
1615 #define SLC_SLC0_RXLINK_ADDR_S  0
1616 
1617 #define SLC_0TX_LINK_REG          (DR_REG_SLC_BASE + 0x40)
1618 /* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
1619 /*description: */
1620 #define SLC_SLC0_TXLINK_PARK  (BIT(31))
1621 #define SLC_SLC0_TXLINK_PARK_M  (BIT(31))
1622 #define SLC_SLC0_TXLINK_PARK_V  0x1
1623 #define SLC_SLC0_TXLINK_PARK_S  31
1624 /* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
1625 /*description: */
1626 #define SLC_SLC0_TXLINK_RESTART  (BIT(30))
1627 #define SLC_SLC0_TXLINK_RESTART_M  (BIT(30))
1628 #define SLC_SLC0_TXLINK_RESTART_V  0x1
1629 #define SLC_SLC0_TXLINK_RESTART_S  30
1630 /* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
1631 /*description: */
1632 #define SLC_SLC0_TXLINK_START  (BIT(29))
1633 #define SLC_SLC0_TXLINK_START_M  (BIT(29))
1634 #define SLC_SLC0_TXLINK_START_V  0x1
1635 #define SLC_SLC0_TXLINK_START_S  29
1636 /* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
1637 /*description: */
1638 #define SLC_SLC0_TXLINK_STOP  (BIT(28))
1639 #define SLC_SLC0_TXLINK_STOP_M  (BIT(28))
1640 #define SLC_SLC0_TXLINK_STOP_V  0x1
1641 #define SLC_SLC0_TXLINK_STOP_S  28
1642 /* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
1643 /*description: */
1644 #define SLC_SLC0_TXLINK_ADDR  0x000FFFFF
1645 #define SLC_SLC0_TXLINK_ADDR_M  ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S))
1646 #define SLC_SLC0_TXLINK_ADDR_V  0xFFFFF
1647 #define SLC_SLC0_TXLINK_ADDR_S  0
1648 
1649 #define SLC_1RX_LINK_REG          (DR_REG_SLC_BASE + 0x44)
1650 /* SLC_SLC1_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
1651 /*description: */
1652 #define SLC_SLC1_RXLINK_PARK  (BIT(31))
1653 #define SLC_SLC1_RXLINK_PARK_M  (BIT(31))
1654 #define SLC_SLC1_RXLINK_PARK_V  0x1
1655 #define SLC_SLC1_RXLINK_PARK_S  31
1656 /* SLC_SLC1_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
1657 /*description: */
1658 #define SLC_SLC1_RXLINK_RESTART  (BIT(30))
1659 #define SLC_SLC1_RXLINK_RESTART_M  (BIT(30))
1660 #define SLC_SLC1_RXLINK_RESTART_V  0x1
1661 #define SLC_SLC1_RXLINK_RESTART_S  30
1662 /* SLC_SLC1_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
1663 /*description: */
1664 #define SLC_SLC1_RXLINK_START  (BIT(29))
1665 #define SLC_SLC1_RXLINK_START_M  (BIT(29))
1666 #define SLC_SLC1_RXLINK_START_V  0x1
1667 #define SLC_SLC1_RXLINK_START_S  29
1668 /* SLC_SLC1_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
1669 /*description: */
1670 #define SLC_SLC1_RXLINK_STOP  (BIT(28))
1671 #define SLC_SLC1_RXLINK_STOP_M  (BIT(28))
1672 #define SLC_SLC1_RXLINK_STOP_V  0x1
1673 #define SLC_SLC1_RXLINK_STOP_S  28
1674 /* SLC_SLC1_BT_PACKET : R/W ;bitpos:[20] ;default: 1'b1 ; */
1675 /*description: */
1676 #define SLC_SLC1_BT_PACKET  (BIT(20))
1677 #define SLC_SLC1_BT_PACKET_M  (BIT(20))
1678 #define SLC_SLC1_BT_PACKET_V  0x1
1679 #define SLC_SLC1_BT_PACKET_S  20
1680 /* SLC_SLC1_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
1681 /*description: */
1682 #define SLC_SLC1_RXLINK_ADDR  0x000FFFFF
1683 #define SLC_SLC1_RXLINK_ADDR_M  ((SLC_SLC1_RXLINK_ADDR_V)<<(SLC_SLC1_RXLINK_ADDR_S))
1684 #define SLC_SLC1_RXLINK_ADDR_V  0xFFFFF
1685 #define SLC_SLC1_RXLINK_ADDR_S  0
1686 
1687 #define SLC_1TX_LINK_REG          (DR_REG_SLC_BASE + 0x48)
1688 /* SLC_SLC1_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
1689 /*description: */
1690 #define SLC_SLC1_TXLINK_PARK  (BIT(31))
1691 #define SLC_SLC1_TXLINK_PARK_M  (BIT(31))
1692 #define SLC_SLC1_TXLINK_PARK_V  0x1
1693 #define SLC_SLC1_TXLINK_PARK_S  31
1694 /* SLC_SLC1_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
1695 /*description: */
1696 #define SLC_SLC1_TXLINK_RESTART  (BIT(30))
1697 #define SLC_SLC1_TXLINK_RESTART_M  (BIT(30))
1698 #define SLC_SLC1_TXLINK_RESTART_V  0x1
1699 #define SLC_SLC1_TXLINK_RESTART_S  30
1700 /* SLC_SLC1_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
1701 /*description: */
1702 #define SLC_SLC1_TXLINK_START  (BIT(29))
1703 #define SLC_SLC1_TXLINK_START_M  (BIT(29))
1704 #define SLC_SLC1_TXLINK_START_V  0x1
1705 #define SLC_SLC1_TXLINK_START_S  29
1706 /* SLC_SLC1_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
1707 /*description: */
1708 #define SLC_SLC1_TXLINK_STOP  (BIT(28))
1709 #define SLC_SLC1_TXLINK_STOP_M  (BIT(28))
1710 #define SLC_SLC1_TXLINK_STOP_V  0x1
1711 #define SLC_SLC1_TXLINK_STOP_S  28
1712 /* SLC_SLC1_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
1713 /*description: */
1714 #define SLC_SLC1_TXLINK_ADDR  0x000FFFFF
1715 #define SLC_SLC1_TXLINK_ADDR_M  ((SLC_SLC1_TXLINK_ADDR_V)<<(SLC_SLC1_TXLINK_ADDR_S))
1716 #define SLC_SLC1_TXLINK_ADDR_V  0xFFFFF
1717 #define SLC_SLC1_TXLINK_ADDR_S  0
1718 
1719 #define SLC_INTVEC_TOHOST_REG          (DR_REG_SLC_BASE + 0x4C)
1720 /* SLC_SLC1_TOHOST_INTVEC : WO ;bitpos:[23:16] ;default: 8'h0 ; */
1721 /*description: */
1722 #define SLC_SLC1_TOHOST_INTVEC  0x000000FF
1723 #define SLC_SLC1_TOHOST_INTVEC_M  ((SLC_SLC1_TOHOST_INTVEC_V)<<(SLC_SLC1_TOHOST_INTVEC_S))
1724 #define SLC_SLC1_TOHOST_INTVEC_V  0xFF
1725 #define SLC_SLC1_TOHOST_INTVEC_S  16
1726 /* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */
1727 /*description: */
1728 #define SLC_SLC0_TOHOST_INTVEC  0x000000FF
1729 #define SLC_SLC0_TOHOST_INTVEC_M  ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S))
1730 #define SLC_SLC0_TOHOST_INTVEC_V  0xFF
1731 #define SLC_SLC0_TOHOST_INTVEC_S  0
1732 
1733 #define SLC_0TOKEN0_REG          (DR_REG_SLC_BASE + 0x50)
1734 /* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
1735 /*description: */
1736 #define SLC_SLC0_TOKEN0  0x00000FFF
1737 #define SLC_SLC0_TOKEN0_M  ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S))
1738 #define SLC_SLC0_TOKEN0_V  0xFFF
1739 #define SLC_SLC0_TOKEN0_S  16
1740 /* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
1741 /*description: */
1742 #define SLC_SLC0_TOKEN0_INC_MORE  (BIT(14))
1743 #define SLC_SLC0_TOKEN0_INC_MORE_M  (BIT(14))
1744 #define SLC_SLC0_TOKEN0_INC_MORE_V  0x1
1745 #define SLC_SLC0_TOKEN0_INC_MORE_S  14
1746 /* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
1747 /*description: */
1748 #define SLC_SLC0_TOKEN0_INC  (BIT(13))
1749 #define SLC_SLC0_TOKEN0_INC_M  (BIT(13))
1750 #define SLC_SLC0_TOKEN0_INC_V  0x1
1751 #define SLC_SLC0_TOKEN0_INC_S  13
1752 /* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
1753 /*description: */
1754 #define SLC_SLC0_TOKEN0_WR  (BIT(12))
1755 #define SLC_SLC0_TOKEN0_WR_M  (BIT(12))
1756 #define SLC_SLC0_TOKEN0_WR_V  0x1
1757 #define SLC_SLC0_TOKEN0_WR_S  12
1758 /* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
1759 /*description: */
1760 #define SLC_SLC0_TOKEN0_WDATA  0x00000FFF
1761 #define SLC_SLC0_TOKEN0_WDATA_M  ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S))
1762 #define SLC_SLC0_TOKEN0_WDATA_V  0xFFF
1763 #define SLC_SLC0_TOKEN0_WDATA_S  0
1764 
1765 #define SLC_0TOKEN1_REG          (DR_REG_SLC_BASE + 0x54)
1766 /* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
1767 /*description: */
1768 #define SLC_SLC0_TOKEN1  0x00000FFF
1769 #define SLC_SLC0_TOKEN1_M  ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S))
1770 #define SLC_SLC0_TOKEN1_V  0xFFF
1771 #define SLC_SLC0_TOKEN1_S  16
1772 /* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
1773 /*description: */
1774 #define SLC_SLC0_TOKEN1_INC_MORE  (BIT(14))
1775 #define SLC_SLC0_TOKEN1_INC_MORE_M  (BIT(14))
1776 #define SLC_SLC0_TOKEN1_INC_MORE_V  0x1
1777 #define SLC_SLC0_TOKEN1_INC_MORE_S  14
1778 /* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
1779 /*description: */
1780 #define SLC_SLC0_TOKEN1_INC  (BIT(13))
1781 #define SLC_SLC0_TOKEN1_INC_M  (BIT(13))
1782 #define SLC_SLC0_TOKEN1_INC_V  0x1
1783 #define SLC_SLC0_TOKEN1_INC_S  13
1784 /* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
1785 /*description: */
1786 #define SLC_SLC0_TOKEN1_WR  (BIT(12))
1787 #define SLC_SLC0_TOKEN1_WR_M  (BIT(12))
1788 #define SLC_SLC0_TOKEN1_WR_V  0x1
1789 #define SLC_SLC0_TOKEN1_WR_S  12
1790 /* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
1791 /*description: */
1792 #define SLC_SLC0_TOKEN1_WDATA  0x00000FFF
1793 #define SLC_SLC0_TOKEN1_WDATA_M  ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S))
1794 #define SLC_SLC0_TOKEN1_WDATA_V  0xFFF
1795 #define SLC_SLC0_TOKEN1_WDATA_S  0
1796 
1797 #define SLC_1TOKEN0_REG          (DR_REG_SLC_BASE + 0x58)
1798 /* SLC_SLC1_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
1799 /*description: */
1800 #define SLC_SLC1_TOKEN0  0x00000FFF
1801 #define SLC_SLC1_TOKEN0_M  ((SLC_SLC1_TOKEN0_V)<<(SLC_SLC1_TOKEN0_S))
1802 #define SLC_SLC1_TOKEN0_V  0xFFF
1803 #define SLC_SLC1_TOKEN0_S  16
1804 /* SLC_SLC1_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
1805 /*description: */
1806 #define SLC_SLC1_TOKEN0_INC_MORE  (BIT(14))
1807 #define SLC_SLC1_TOKEN0_INC_MORE_M  (BIT(14))
1808 #define SLC_SLC1_TOKEN0_INC_MORE_V  0x1
1809 #define SLC_SLC1_TOKEN0_INC_MORE_S  14
1810 /* SLC_SLC1_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
1811 /*description: */
1812 #define SLC_SLC1_TOKEN0_INC  (BIT(13))
1813 #define SLC_SLC1_TOKEN0_INC_M  (BIT(13))
1814 #define SLC_SLC1_TOKEN0_INC_V  0x1
1815 #define SLC_SLC1_TOKEN0_INC_S  13
1816 /* SLC_SLC1_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
1817 /*description: */
1818 #define SLC_SLC1_TOKEN0_WR  (BIT(12))
1819 #define SLC_SLC1_TOKEN0_WR_M  (BIT(12))
1820 #define SLC_SLC1_TOKEN0_WR_V  0x1
1821 #define SLC_SLC1_TOKEN0_WR_S  12
1822 /* SLC_SLC1_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
1823 /*description: */
1824 #define SLC_SLC1_TOKEN0_WDATA  0x00000FFF
1825 #define SLC_SLC1_TOKEN0_WDATA_M  ((SLC_SLC1_TOKEN0_WDATA_V)<<(SLC_SLC1_TOKEN0_WDATA_S))
1826 #define SLC_SLC1_TOKEN0_WDATA_V  0xFFF
1827 #define SLC_SLC1_TOKEN0_WDATA_S  0
1828 
1829 #define SLC_1TOKEN1_REG          (DR_REG_SLC_BASE + 0x5C)
1830 /* SLC_SLC1_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
1831 /*description: */
1832 #define SLC_SLC1_TOKEN1  0x00000FFF
1833 #define SLC_SLC1_TOKEN1_M  ((SLC_SLC1_TOKEN1_V)<<(SLC_SLC1_TOKEN1_S))
1834 #define SLC_SLC1_TOKEN1_V  0xFFF
1835 #define SLC_SLC1_TOKEN1_S  16
1836 /* SLC_SLC1_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
1837 /*description: */
1838 #define SLC_SLC1_TOKEN1_INC_MORE  (BIT(14))
1839 #define SLC_SLC1_TOKEN1_INC_MORE_M  (BIT(14))
1840 #define SLC_SLC1_TOKEN1_INC_MORE_V  0x1
1841 #define SLC_SLC1_TOKEN1_INC_MORE_S  14
1842 /* SLC_SLC1_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
1843 /*description: */
1844 #define SLC_SLC1_TOKEN1_INC  (BIT(13))
1845 #define SLC_SLC1_TOKEN1_INC_M  (BIT(13))
1846 #define SLC_SLC1_TOKEN1_INC_V  0x1
1847 #define SLC_SLC1_TOKEN1_INC_S  13
1848 /* SLC_SLC1_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
1849 /*description: */
1850 #define SLC_SLC1_TOKEN1_WR  (BIT(12))
1851 #define SLC_SLC1_TOKEN1_WR_M  (BIT(12))
1852 #define SLC_SLC1_TOKEN1_WR_V  0x1
1853 #define SLC_SLC1_TOKEN1_WR_S  12
1854 /* SLC_SLC1_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
1855 /*description: */
1856 #define SLC_SLC1_TOKEN1_WDATA  0x00000FFF
1857 #define SLC_SLC1_TOKEN1_WDATA_M  ((SLC_SLC1_TOKEN1_WDATA_V)<<(SLC_SLC1_TOKEN1_WDATA_S))
1858 #define SLC_SLC1_TOKEN1_WDATA_V  0xFFF
1859 #define SLC_SLC1_TOKEN1_WDATA_S  0
1860 
1861 #define SLC_CONF1_REG          (DR_REG_SLC_BASE + 0x60)
1862 /* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
1863 /*description: */
1864 #define SLC_CLK_EN  (BIT(22))
1865 #define SLC_CLK_EN_M  (BIT(22))
1866 #define SLC_CLK_EN_V  0x1
1867 #define SLC_CLK_EN_S  22
1868 /* SLC_SLC1_RX_STITCH_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
1869 /*description: */
1870 #define SLC_SLC1_RX_STITCH_EN  (BIT(21))
1871 #define SLC_SLC1_RX_STITCH_EN_M  (BIT(21))
1872 #define SLC_SLC1_RX_STITCH_EN_V  0x1
1873 #define SLC_SLC1_RX_STITCH_EN_S  21
1874 /* SLC_SLC1_TX_STITCH_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
1875 /*description: */
1876 #define SLC_SLC1_TX_STITCH_EN  (BIT(20))
1877 #define SLC_SLC1_TX_STITCH_EN_M  (BIT(20))
1878 #define SLC_SLC1_TX_STITCH_EN_V  0x1
1879 #define SLC_SLC1_TX_STITCH_EN_S  20
1880 /* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
1881 /*description: */
1882 #define SLC_HOST_INT_LEVEL_SEL  (BIT(19))
1883 #define SLC_HOST_INT_LEVEL_SEL_M  (BIT(19))
1884 #define SLC_HOST_INT_LEVEL_SEL_V  0x1
1885 #define SLC_HOST_INT_LEVEL_SEL_S  19
1886 /* SLC_SLC1_RX_CHECK_SUM_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
1887 /*description: */
1888 #define SLC_SLC1_RX_CHECK_SUM_EN  (BIT(18))
1889 #define SLC_SLC1_RX_CHECK_SUM_EN_M  (BIT(18))
1890 #define SLC_SLC1_RX_CHECK_SUM_EN_V  0x1
1891 #define SLC_SLC1_RX_CHECK_SUM_EN_S  18
1892 /* SLC_SLC1_TX_CHECK_SUM_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
1893 /*description: */
1894 #define SLC_SLC1_TX_CHECK_SUM_EN  (BIT(17))
1895 #define SLC_SLC1_TX_CHECK_SUM_EN_M  (BIT(17))
1896 #define SLC_SLC1_TX_CHECK_SUM_EN_V  0x1
1897 #define SLC_SLC1_TX_CHECK_SUM_EN_S  17
1898 /* SLC_SLC1_CHECK_OWNER : R/W ;bitpos:[16] ;default: 1'b0 ; */
1899 /*description: */
1900 #define SLC_SLC1_CHECK_OWNER  (BIT(16))
1901 #define SLC_SLC1_CHECK_OWNER_M  (BIT(16))
1902 #define SLC_SLC1_CHECK_OWNER_V  0x1
1903 #define SLC_SLC1_CHECK_OWNER_S  16
1904 /* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
1905 /*description: */
1906 #define SLC_SLC0_RX_STITCH_EN  (BIT(6))
1907 #define SLC_SLC0_RX_STITCH_EN_M  (BIT(6))
1908 #define SLC_SLC0_RX_STITCH_EN_V  0x1
1909 #define SLC_SLC0_RX_STITCH_EN_S  6
1910 /* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
1911 /*description: */
1912 #define SLC_SLC0_TX_STITCH_EN  (BIT(5))
1913 #define SLC_SLC0_TX_STITCH_EN_M  (BIT(5))
1914 #define SLC_SLC0_TX_STITCH_EN_V  0x1
1915 #define SLC_SLC0_TX_STITCH_EN_S  5
1916 /* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */
1917 /*description: */
1918 #define SLC_SLC0_LEN_AUTO_CLR  (BIT(4))
1919 #define SLC_SLC0_LEN_AUTO_CLR_M  (BIT(4))
1920 #define SLC_SLC0_LEN_AUTO_CLR_V  0x1
1921 #define SLC_SLC0_LEN_AUTO_CLR_S  4
1922 /* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
1923 /*description: */
1924 #define SLC_CMD_HOLD_EN  (BIT(3))
1925 #define SLC_CMD_HOLD_EN_M  (BIT(3))
1926 #define SLC_CMD_HOLD_EN_V  0x1
1927 #define SLC_CMD_HOLD_EN_S  3
1928 /* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
1929 /*description: */
1930 #define SLC_SLC0_RX_CHECK_SUM_EN  (BIT(2))
1931 #define SLC_SLC0_RX_CHECK_SUM_EN_M  (BIT(2))
1932 #define SLC_SLC0_RX_CHECK_SUM_EN_V  0x1
1933 #define SLC_SLC0_RX_CHECK_SUM_EN_S  2
1934 /* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
1935 /*description: */
1936 #define SLC_SLC0_TX_CHECK_SUM_EN  (BIT(1))
1937 #define SLC_SLC0_TX_CHECK_SUM_EN_M  (BIT(1))
1938 #define SLC_SLC0_TX_CHECK_SUM_EN_V  0x1
1939 #define SLC_SLC0_TX_CHECK_SUM_EN_S  1
1940 /* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */
1941 /*description: */
1942 #define SLC_SLC0_CHECK_OWNER  (BIT(0))
1943 #define SLC_SLC0_CHECK_OWNER_M  (BIT(0))
1944 #define SLC_SLC0_CHECK_OWNER_V  0x1
1945 #define SLC_SLC0_CHECK_OWNER_S  0
1946 
1947 #define SLC_0_STATE0_REG          (DR_REG_SLC_BASE + 0x64)
1948 /* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1949 /*description: */
1950 #define SLC_SLC0_STATE0  0xFFFFFFFF
1951 #define SLC_SLC0_STATE0_M  ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S))
1952 #define SLC_SLC0_STATE0_V  0xFFFFFFFF
1953 #define SLC_SLC0_STATE0_S  0
1954 
1955 #define SLC_0_STATE1_REG          (DR_REG_SLC_BASE + 0x68)
1956 /* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1957 /*description: */
1958 #define SLC_SLC0_STATE1  0xFFFFFFFF
1959 #define SLC_SLC0_STATE1_M  ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S))
1960 #define SLC_SLC0_STATE1_V  0xFFFFFFFF
1961 #define SLC_SLC0_STATE1_S  0
1962 
1963 #define SLC_1_STATE0_REG          (DR_REG_SLC_BASE + 0x6C)
1964 /* SLC_SLC1_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1965 /*description: */
1966 #define SLC_SLC1_STATE0  0xFFFFFFFF
1967 #define SLC_SLC1_STATE0_M  ((SLC_SLC1_STATE0_V)<<(SLC_SLC1_STATE0_S))
1968 #define SLC_SLC1_STATE0_V  0xFFFFFFFF
1969 #define SLC_SLC1_STATE0_S  0
1970 
1971 #define SLC_1_STATE1_REG          (DR_REG_SLC_BASE + 0x70)
1972 /* SLC_SLC1_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1973 /*description: */
1974 #define SLC_SLC1_STATE1  0xFFFFFFFF
1975 #define SLC_SLC1_STATE1_M  ((SLC_SLC1_STATE1_V)<<(SLC_SLC1_STATE1_S))
1976 #define SLC_SLC1_STATE1_V  0xFFFFFFFF
1977 #define SLC_SLC1_STATE1_S  0
1978 
1979 #define SLC_BRIDGE_CONF_REG          (DR_REG_SLC_BASE + 0x74)
1980 /* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */
1981 /*description: */
1982 #define SLC_TX_PUSH_IDLE_NUM  0x0000FFFF
1983 #define SLC_TX_PUSH_IDLE_NUM_M  ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S))
1984 #define SLC_TX_PUSH_IDLE_NUM_V  0xFFFF
1985 #define SLC_TX_PUSH_IDLE_NUM_S  16
1986 /* SLC_SLC1_TX_DUMMY_MODE : R/W ;bitpos:[14] ;default: 1'h1 ; */
1987 /*description: */
1988 #define SLC_SLC1_TX_DUMMY_MODE  (BIT(14))
1989 #define SLC_SLC1_TX_DUMMY_MODE_M  (BIT(14))
1990 #define SLC_SLC1_TX_DUMMY_MODE_V  0x1
1991 #define SLC_SLC1_TX_DUMMY_MODE_S  14
1992 /* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */
1993 /*description: */
1994 #define SLC_HDA_MAP_128K  (BIT(13))
1995 #define SLC_HDA_MAP_128K_M  (BIT(13))
1996 #define SLC_HDA_MAP_128K_V  0x1
1997 #define SLC_HDA_MAP_128K_S  13
1998 /* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */
1999 /*description: */
2000 #define SLC_SLC0_TX_DUMMY_MODE  (BIT(12))
2001 #define SLC_SLC0_TX_DUMMY_MODE_M  (BIT(12))
2002 #define SLC_SLC0_TX_DUMMY_MODE_V  0x1
2003 #define SLC_SLC0_TX_DUMMY_MODE_S  12
2004 /* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
2005 /*description: */
2006 #define SLC_FIFO_MAP_ENA  0x0000000F
2007 #define SLC_FIFO_MAP_ENA_M  ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S))
2008 #define SLC_FIFO_MAP_ENA_V  0xF
2009 #define SLC_FIFO_MAP_ENA_S  8
2010 /* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
2011 /*description: */
2012 #define SLC_TXEOF_ENA  0x0000003F
2013 #define SLC_TXEOF_ENA_M  ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S))
2014 #define SLC_TXEOF_ENA_V  0x3F
2015 #define SLC_TXEOF_ENA_S  0
2016 
2017 #define SLC_0_TO_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x78)
2018 /* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2019 /*description: */
2020 #define SLC_SLC0_TO_EOF_DES_ADDR  0xFFFFFFFF
2021 #define SLC_SLC0_TO_EOF_DES_ADDR_M  ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S))
2022 #define SLC_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFF
2023 #define SLC_SLC0_TO_EOF_DES_ADDR_S  0
2024 
2025 #define SLC_0_TX_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x7C)
2026 /* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2027 /*description: */
2028 #define SLC_SLC0_TX_SUC_EOF_DES_ADDR  0xFFFFFFFF
2029 #define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M  ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S))
2030 #define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
2031 #define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S  0
2032 
2033 #define SLC_0_TO_EOF_BFR_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x80)
2034 /* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2035 /*description: */
2036 #define SLC_SLC0_TO_EOF_BFR_DES_ADDR  0xFFFFFFFF
2037 #define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M  ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S))
2038 #define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
2039 #define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S  0
2040 
2041 #define SLC_1_TO_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x84)
2042 /* SLC_SLC1_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2043 /*description: */
2044 #define SLC_SLC1_TO_EOF_DES_ADDR  0xFFFFFFFF
2045 #define SLC_SLC1_TO_EOF_DES_ADDR_M  ((SLC_SLC1_TO_EOF_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_DES_ADDR_S))
2046 #define SLC_SLC1_TO_EOF_DES_ADDR_V  0xFFFFFFFF
2047 #define SLC_SLC1_TO_EOF_DES_ADDR_S  0
2048 
2049 #define SLC_1_TX_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x88)
2050 /* SLC_SLC1_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2051 /*description: */
2052 #define SLC_SLC1_TX_SUC_EOF_DES_ADDR  0xFFFFFFFF
2053 #define SLC_SLC1_TX_SUC_EOF_DES_ADDR_M  ((SLC_SLC1_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_SUC_EOF_DES_ADDR_S))
2054 #define SLC_SLC1_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
2055 #define SLC_SLC1_TX_SUC_EOF_DES_ADDR_S  0
2056 
2057 #define SLC_1_TO_EOF_BFR_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x8C)
2058 /* SLC_SLC1_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2059 /*description: */
2060 #define SLC_SLC1_TO_EOF_BFR_DES_ADDR  0xFFFFFFFF
2061 #define SLC_SLC1_TO_EOF_BFR_DES_ADDR_M  ((SLC_SLC1_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_BFR_DES_ADDR_S))
2062 #define SLC_SLC1_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
2063 #define SLC_SLC1_TO_EOF_BFR_DES_ADDR_S  0
2064 
2065 #define SLC_AHB_TEST_REG          (DR_REG_SLC_BASE + 0x90)
2066 /* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
2067 /*description: */
2068 #define SLC_AHB_TESTADDR  0x00000003
2069 #define SLC_AHB_TESTADDR_M  ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S))
2070 #define SLC_AHB_TESTADDR_V  0x3
2071 #define SLC_AHB_TESTADDR_S  4
2072 /* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
2073 /*description: */
2074 #define SLC_AHB_TESTMODE  0x00000007
2075 #define SLC_AHB_TESTMODE_M  ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S))
2076 #define SLC_AHB_TESTMODE_V  0x7
2077 #define SLC_AHB_TESTMODE_S  0
2078 
2079 #define SLC_SDIO_ST_REG          (DR_REG_SLC_BASE + 0x94)
2080 /* SLC_FUNC2_ACC_STATE : RO ;bitpos:[28:24] ;default: 5'b0 ; */
2081 /*description: */
2082 #define SLC_FUNC2_ACC_STATE  0x0000001F
2083 #define SLC_FUNC2_ACC_STATE_M  ((SLC_FUNC2_ACC_STATE_V)<<(SLC_FUNC2_ACC_STATE_S))
2084 #define SLC_FUNC2_ACC_STATE_V  0x1F
2085 #define SLC_FUNC2_ACC_STATE_S  24
2086 /* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */
2087 /*description: */
2088 #define SLC_FUNC1_ACC_STATE  0x0000001F
2089 #define SLC_FUNC1_ACC_STATE_M  ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S))
2090 #define SLC_FUNC1_ACC_STATE_V  0x1F
2091 #define SLC_FUNC1_ACC_STATE_S  16
2092 /* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */
2093 /*description: */
2094 #define SLC_BUS_ST  0x00000007
2095 #define SLC_BUS_ST_M  ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S))
2096 #define SLC_BUS_ST_V  0x7
2097 #define SLC_BUS_ST_S  12
2098 /* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */
2099 /*description: */
2100 #define SLC_SDIO_WAKEUP  (BIT(8))
2101 #define SLC_SDIO_WAKEUP_M  (BIT(8))
2102 #define SLC_SDIO_WAKEUP_V  0x1
2103 #define SLC_SDIO_WAKEUP_S  8
2104 /* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
2105 /*description: */
2106 #define SLC_FUNC_ST  0x0000000F
2107 #define SLC_FUNC_ST_M  ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S))
2108 #define SLC_FUNC_ST_V  0xF
2109 #define SLC_FUNC_ST_S  4
2110 /* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
2111 /*description: */
2112 #define SLC_CMD_ST  0x00000007
2113 #define SLC_CMD_ST_M  ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S))
2114 #define SLC_CMD_ST_V  0x7
2115 #define SLC_CMD_ST_S  0
2116 
2117 #define SLC_RX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0x98)
2118 /* SLC_SLC1_RD_RETRY_THRESHOLD : R/W ;bitpos:[31:21] ;default: 11'h80 ; */
2119 /*description: */
2120 #define SLC_SLC1_RD_RETRY_THRESHOLD  0x000007FF
2121 #define SLC_SLC1_RD_RETRY_THRESHOLD_M  ((SLC_SLC1_RD_RETRY_THRESHOLD_V)<<(SLC_SLC1_RD_RETRY_THRESHOLD_S))
2122 #define SLC_SLC1_RD_RETRY_THRESHOLD_V  0x7FF
2123 #define SLC_SLC1_RD_RETRY_THRESHOLD_S  21
2124 /* SLC_SLC1_RX_FILL_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
2125 /*description: */
2126 #define SLC_SLC1_RX_FILL_EN  (BIT(20))
2127 #define SLC_SLC1_RX_FILL_EN_M  (BIT(20))
2128 #define SLC_SLC1_RX_FILL_EN_V  0x1
2129 #define SLC_SLC1_RX_FILL_EN_S  20
2130 /* SLC_SLC1_RX_EOF_MODE : R/W ;bitpos:[19] ;default: 1'b1 ; */
2131 /*description: */
2132 #define SLC_SLC1_RX_EOF_MODE  (BIT(19))
2133 #define SLC_SLC1_RX_EOF_MODE_M  (BIT(19))
2134 #define SLC_SLC1_RX_EOF_MODE_V  0x1
2135 #define SLC_SLC1_RX_EOF_MODE_S  19
2136 /* SLC_SLC1_RX_FILL_MODE : R/W ;bitpos:[18] ;default: 1'b0 ; */
2137 /*description: */
2138 #define SLC_SLC1_RX_FILL_MODE  (BIT(18))
2139 #define SLC_SLC1_RX_FILL_MODE_M  (BIT(18))
2140 #define SLC_SLC1_RX_FILL_MODE_V  0x1
2141 #define SLC_SLC1_RX_FILL_MODE_S  18
2142 /* SLC_SLC1_INFOR_NO_REPLACE : R/W ;bitpos:[17] ;default: 1'b1 ; */
2143 /*description: */
2144 #define SLC_SLC1_INFOR_NO_REPLACE  (BIT(17))
2145 #define SLC_SLC1_INFOR_NO_REPLACE_M  (BIT(17))
2146 #define SLC_SLC1_INFOR_NO_REPLACE_V  0x1
2147 #define SLC_SLC1_INFOR_NO_REPLACE_S  17
2148 /* SLC_SLC1_TOKEN_NO_REPLACE : R/W ;bitpos:[16] ;default: 1'b1 ; */
2149 /*description: */
2150 #define SLC_SLC1_TOKEN_NO_REPLACE  (BIT(16))
2151 #define SLC_SLC1_TOKEN_NO_REPLACE_M  (BIT(16))
2152 #define SLC_SLC1_TOKEN_NO_REPLACE_V  0x1
2153 #define SLC_SLC1_TOKEN_NO_REPLACE_S  16
2154 /* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */
2155 /*description: */
2156 #define SLC_SLC0_RD_RETRY_THRESHOLD  0x000007FF
2157 #define SLC_SLC0_RD_RETRY_THRESHOLD_M  ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S))
2158 #define SLC_SLC0_RD_RETRY_THRESHOLD_V  0x7FF
2159 #define SLC_SLC0_RD_RETRY_THRESHOLD_S  5
2160 /* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
2161 /*description: */
2162 #define SLC_SLC0_RX_FILL_EN  (BIT(4))
2163 #define SLC_SLC0_RX_FILL_EN_M  (BIT(4))
2164 #define SLC_SLC0_RX_FILL_EN_V  0x1
2165 #define SLC_SLC0_RX_FILL_EN_S  4
2166 /* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */
2167 /*description: */
2168 #define SLC_SLC0_RX_EOF_MODE  (BIT(3))
2169 #define SLC_SLC0_RX_EOF_MODE_M  (BIT(3))
2170 #define SLC_SLC0_RX_EOF_MODE_V  0x1
2171 #define SLC_SLC0_RX_EOF_MODE_S  3
2172 /* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
2173 /*description: */
2174 #define SLC_SLC0_RX_FILL_MODE  (BIT(2))
2175 #define SLC_SLC0_RX_FILL_MODE_M  (BIT(2))
2176 #define SLC_SLC0_RX_FILL_MODE_V  0x1
2177 #define SLC_SLC0_RX_FILL_MODE_S  2
2178 /* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */
2179 /*description: */
2180 #define SLC_SLC0_INFOR_NO_REPLACE  (BIT(1))
2181 #define SLC_SLC0_INFOR_NO_REPLACE_M  (BIT(1))
2182 #define SLC_SLC0_INFOR_NO_REPLACE_V  0x1
2183 #define SLC_SLC0_INFOR_NO_REPLACE_S  1
2184 /* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */
2185 /*description: */
2186 #define SLC_SLC0_TOKEN_NO_REPLACE  (BIT(0))
2187 #define SLC_SLC0_TOKEN_NO_REPLACE_M  (BIT(0))
2188 #define SLC_SLC0_TOKEN_NO_REPLACE_V  0x1
2189 #define SLC_SLC0_TOKEN_NO_REPLACE_S  0
2190 
2191 #define SLC_0_TXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0x9C)
2192 /* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2193 /*description: */
2194 #define SLC_SLC0_TXLINK_DSCR  0xFFFFFFFF
2195 #define SLC_SLC0_TXLINK_DSCR_M  ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S))
2196 #define SLC_SLC0_TXLINK_DSCR_V  0xFFFFFFFF
2197 #define SLC_SLC0_TXLINK_DSCR_S  0
2198 
2199 #define SLC_0_TXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xA0)
2200 /* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2201 /*description: */
2202 #define SLC_SLC0_TXLINK_DSCR_BF0  0xFFFFFFFF
2203 #define SLC_SLC0_TXLINK_DSCR_BF0_M  ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S))
2204 #define SLC_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFF
2205 #define SLC_SLC0_TXLINK_DSCR_BF0_S  0
2206 
2207 #define SLC_0_TXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xA4)
2208 /* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2209 /*description: */
2210 #define SLC_SLC0_TXLINK_DSCR_BF1  0xFFFFFFFF
2211 #define SLC_SLC0_TXLINK_DSCR_BF1_M  ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S))
2212 #define SLC_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFF
2213 #define SLC_SLC0_TXLINK_DSCR_BF1_S  0
2214 
2215 #define SLC_0_RXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xA8)
2216 /* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2217 /*description: */
2218 #define SLC_SLC0_RXLINK_DSCR  0xFFFFFFFF
2219 #define SLC_SLC0_RXLINK_DSCR_M  ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S))
2220 #define SLC_SLC0_RXLINK_DSCR_V  0xFFFFFFFF
2221 #define SLC_SLC0_RXLINK_DSCR_S  0
2222 
2223 #define SLC_0_RXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xAC)
2224 /* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2225 /*description: */
2226 #define SLC_SLC0_RXLINK_DSCR_BF0  0xFFFFFFFF
2227 #define SLC_SLC0_RXLINK_DSCR_BF0_M  ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S))
2228 #define SLC_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFF
2229 #define SLC_SLC0_RXLINK_DSCR_BF0_S  0
2230 
2231 #define SLC_0_RXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xB0)
2232 /* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2233 /*description: */
2234 #define SLC_SLC0_RXLINK_DSCR_BF1  0xFFFFFFFF
2235 #define SLC_SLC0_RXLINK_DSCR_BF1_M  ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S))
2236 #define SLC_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFF
2237 #define SLC_SLC0_RXLINK_DSCR_BF1_S  0
2238 
2239 #define SLC_1_TXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xB4)
2240 /* SLC_SLC1_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2241 /*description: */
2242 #define SLC_SLC1_TXLINK_DSCR  0xFFFFFFFF
2243 #define SLC_SLC1_TXLINK_DSCR_M  ((SLC_SLC1_TXLINK_DSCR_V)<<(SLC_SLC1_TXLINK_DSCR_S))
2244 #define SLC_SLC1_TXLINK_DSCR_V  0xFFFFFFFF
2245 #define SLC_SLC1_TXLINK_DSCR_S  0
2246 
2247 #define SLC_1_TXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xB8)
2248 /* SLC_SLC1_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2249 /*description: */
2250 #define SLC_SLC1_TXLINK_DSCR_BF0  0xFFFFFFFF
2251 #define SLC_SLC1_TXLINK_DSCR_BF0_M  ((SLC_SLC1_TXLINK_DSCR_BF0_V)<<(SLC_SLC1_TXLINK_DSCR_BF0_S))
2252 #define SLC_SLC1_TXLINK_DSCR_BF0_V  0xFFFFFFFF
2253 #define SLC_SLC1_TXLINK_DSCR_BF0_S  0
2254 
2255 #define SLC_1_TXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xBC)
2256 /* SLC_SLC1_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2257 /*description: */
2258 #define SLC_SLC1_TXLINK_DSCR_BF1  0xFFFFFFFF
2259 #define SLC_SLC1_TXLINK_DSCR_BF1_M  ((SLC_SLC1_TXLINK_DSCR_BF1_V)<<(SLC_SLC1_TXLINK_DSCR_BF1_S))
2260 #define SLC_SLC1_TXLINK_DSCR_BF1_V  0xFFFFFFFF
2261 #define SLC_SLC1_TXLINK_DSCR_BF1_S  0
2262 
2263 #define SLC_1_RXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xC0)
2264 /* SLC_SLC1_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2265 /*description: */
2266 #define SLC_SLC1_RXLINK_DSCR  0xFFFFFFFF
2267 #define SLC_SLC1_RXLINK_DSCR_M  ((SLC_SLC1_RXLINK_DSCR_V)<<(SLC_SLC1_RXLINK_DSCR_S))
2268 #define SLC_SLC1_RXLINK_DSCR_V  0xFFFFFFFF
2269 #define SLC_SLC1_RXLINK_DSCR_S  0
2270 
2271 #define SLC_1_RXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xC4)
2272 /* SLC_SLC1_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2273 /*description: */
2274 #define SLC_SLC1_RXLINK_DSCR_BF0  0xFFFFFFFF
2275 #define SLC_SLC1_RXLINK_DSCR_BF0_M  ((SLC_SLC1_RXLINK_DSCR_BF0_V)<<(SLC_SLC1_RXLINK_DSCR_BF0_S))
2276 #define SLC_SLC1_RXLINK_DSCR_BF0_V  0xFFFFFFFF
2277 #define SLC_SLC1_RXLINK_DSCR_BF0_S  0
2278 
2279 #define SLC_1_RXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xC8)
2280 /* SLC_SLC1_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2281 /*description: */
2282 #define SLC_SLC1_RXLINK_DSCR_BF1  0xFFFFFFFF
2283 #define SLC_SLC1_RXLINK_DSCR_BF1_M  ((SLC_SLC1_RXLINK_DSCR_BF1_V)<<(SLC_SLC1_RXLINK_DSCR_BF1_S))
2284 #define SLC_SLC1_RXLINK_DSCR_BF1_V  0xFFFFFFFF
2285 #define SLC_SLC1_RXLINK_DSCR_BF1_S  0
2286 
2287 #define SLC_0_TX_ERREOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0xCC)
2288 /* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2289 /*description: */
2290 #define SLC_SLC0_TX_ERR_EOF_DES_ADDR  0xFFFFFFFF
2291 #define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M  ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S))
2292 #define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
2293 #define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S  0
2294 
2295 #define SLC_1_TX_ERREOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0xD0)
2296 /* SLC_SLC1_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2297 /*description: */
2298 #define SLC_SLC1_TX_ERR_EOF_DES_ADDR  0xFFFFFFFF
2299 #define SLC_SLC1_TX_ERR_EOF_DES_ADDR_M  ((SLC_SLC1_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_ERR_EOF_DES_ADDR_S))
2300 #define SLC_SLC1_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
2301 #define SLC_SLC1_TX_ERR_EOF_DES_ADDR_S  0
2302 
2303 #define SLC_TOKEN_LAT_REG          (DR_REG_SLC_BASE + 0xD4)
2304 /* SLC_SLC1_TOKEN : RO ;bitpos:[27:16] ;default: 12'b0 ; */
2305 /*description: */
2306 #define SLC_SLC1_TOKEN  0x00000FFF
2307 #define SLC_SLC1_TOKEN_M  ((SLC_SLC1_TOKEN_V)<<(SLC_SLC1_TOKEN_S))
2308 #define SLC_SLC1_TOKEN_V  0xFFF
2309 #define SLC_SLC1_TOKEN_S  16
2310 /* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */
2311 /*description: */
2312 #define SLC_SLC0_TOKEN  0x00000FFF
2313 #define SLC_SLC0_TOKEN_M  ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S))
2314 #define SLC_SLC0_TOKEN_V  0xFFF
2315 #define SLC_SLC0_TOKEN_S  0
2316 
2317 #define SLC_TX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0xD8)
2318 /* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */
2319 /*description: */
2320 #define SLC_WR_RETRY_THRESHOLD  0x000007FF
2321 #define SLC_WR_RETRY_THRESHOLD_M  ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S))
2322 #define SLC_WR_RETRY_THRESHOLD_V  0x7FF
2323 #define SLC_WR_RETRY_THRESHOLD_S  0
2324 
2325 #define SLC_CMD_INFOR0_REG          (DR_REG_SLC_BASE + 0xDC)
2326 /* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2327 /*description: */
2328 #define SLC_CMD_CONTENT0  0xFFFFFFFF
2329 #define SLC_CMD_CONTENT0_M  ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S))
2330 #define SLC_CMD_CONTENT0_V  0xFFFFFFFF
2331 #define SLC_CMD_CONTENT0_S  0
2332 
2333 #define SLC_CMD_INFOR1_REG          (DR_REG_SLC_BASE + 0xE0)
2334 /* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2335 /*description: */
2336 #define SLC_CMD_CONTENT1  0xFFFFFFFF
2337 #define SLC_CMD_CONTENT1_M  ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S))
2338 #define SLC_CMD_CONTENT1_V  0xFFFFFFFF
2339 #define SLC_CMD_CONTENT1_S  0
2340 
2341 #define SLC_0_LEN_CONF_REG          (DR_REG_SLC_BASE + 0xE4)
2342 /* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */
2343 /*description: */
2344 #define SLC_SLC0_TX_NEW_PKT_IND  (BIT(28))
2345 #define SLC_SLC0_TX_NEW_PKT_IND_M  (BIT(28))
2346 #define SLC_SLC0_TX_NEW_PKT_IND_V  0x1
2347 #define SLC_SLC0_TX_NEW_PKT_IND_S  28
2348 /* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */
2349 /*description: */
2350 #define SLC_SLC0_RX_NEW_PKT_IND  (BIT(27))
2351 #define SLC_SLC0_RX_NEW_PKT_IND_M  (BIT(27))
2352 #define SLC_SLC0_RX_NEW_PKT_IND_V  0x1
2353 #define SLC_SLC0_RX_NEW_PKT_IND_S  27
2354 /* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */
2355 /*description: */
2356 #define SLC_SLC0_TX_GET_USED_DSCR  (BIT(26))
2357 #define SLC_SLC0_TX_GET_USED_DSCR_M  (BIT(26))
2358 #define SLC_SLC0_TX_GET_USED_DSCR_V  0x1
2359 #define SLC_SLC0_TX_GET_USED_DSCR_S  26
2360 /* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */
2361 /*description: */
2362 #define SLC_SLC0_RX_GET_USED_DSCR  (BIT(25))
2363 #define SLC_SLC0_RX_GET_USED_DSCR_M  (BIT(25))
2364 #define SLC_SLC0_RX_GET_USED_DSCR_V  0x1
2365 #define SLC_SLC0_RX_GET_USED_DSCR_S  25
2366 /* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
2367 /*description: */
2368 #define SLC_SLC0_TX_PACKET_LOAD_EN  (BIT(24))
2369 #define SLC_SLC0_TX_PACKET_LOAD_EN_M  (BIT(24))
2370 #define SLC_SLC0_TX_PACKET_LOAD_EN_V  0x1
2371 #define SLC_SLC0_TX_PACKET_LOAD_EN_S  24
2372 /* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
2373 /*description: */
2374 #define SLC_SLC0_RX_PACKET_LOAD_EN  (BIT(23))
2375 #define SLC_SLC0_RX_PACKET_LOAD_EN_M  (BIT(23))
2376 #define SLC_SLC0_RX_PACKET_LOAD_EN_V  0x1
2377 #define SLC_SLC0_RX_PACKET_LOAD_EN_S  23
2378 /* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */
2379 /*description: */
2380 #define SLC_SLC0_LEN_INC_MORE  (BIT(22))
2381 #define SLC_SLC0_LEN_INC_MORE_M  (BIT(22))
2382 #define SLC_SLC0_LEN_INC_MORE_V  0x1
2383 #define SLC_SLC0_LEN_INC_MORE_S  22
2384 /* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */
2385 /*description: */
2386 #define SLC_SLC0_LEN_INC  (BIT(21))
2387 #define SLC_SLC0_LEN_INC_M  (BIT(21))
2388 #define SLC_SLC0_LEN_INC_V  0x1
2389 #define SLC_SLC0_LEN_INC_S  21
2390 /* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */
2391 /*description: */
2392 #define SLC_SLC0_LEN_WR  (BIT(20))
2393 #define SLC_SLC0_LEN_WR_M  (BIT(20))
2394 #define SLC_SLC0_LEN_WR_V  0x1
2395 #define SLC_SLC0_LEN_WR_S  20
2396 /* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */
2397 /*description: */
2398 #define SLC_SLC0_LEN_WDATA  0x000FFFFF
2399 #define SLC_SLC0_LEN_WDATA_M  ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S))
2400 #define SLC_SLC0_LEN_WDATA_V  0xFFFFF
2401 #define SLC_SLC0_LEN_WDATA_S  0
2402 
2403 #define SLC_0_LENGTH_REG          (DR_REG_SLC_BASE + 0xE8)
2404 /* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
2405 /*description: */
2406 #define SLC_SLC0_LEN  0x000FFFFF
2407 #define SLC_SLC0_LEN_M  ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S))
2408 #define SLC_SLC0_LEN_V  0xFFFFF
2409 #define SLC_SLC0_LEN_S  0
2410 
2411 #define SLC_0_TXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xEC)
2412 /* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
2413 /*description: */
2414 #define SLC_SLC0_TX_PKT_H_DSCR_ADDR  0xFFFFFFFF
2415 #define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S))
2416 #define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
2417 #define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S  0
2418 
2419 #define SLC_0_TXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF0)
2420 /* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
2421 /*description: */
2422 #define SLC_SLC0_TX_PKT_E_DSCR_ADDR  0xFFFFFFFF
2423 #define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S))
2424 #define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
2425 #define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S  0
2426 
2427 #define SLC_0_RXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xF4)
2428 /* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
2429 /*description: */
2430 #define SLC_SLC0_RX_PKT_H_DSCR_ADDR  0xFFFFFFFF
2431 #define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S))
2432 #define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
2433 #define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S  0
2434 
2435 #define SLC_0_RXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF8)
2436 /* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
2437 /*description: */
2438 #define SLC_SLC0_RX_PKT_E_DSCR_ADDR  0xFFFFFFFF
2439 #define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S))
2440 #define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
2441 #define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S  0
2442 
2443 #define SLC_0_TXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0xFC)
2444 /* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2445 /*description: */
2446 #define SLC_SLC0_TX_PKT_START_DSCR_ADDR  0xFFFFFFFF
2447 #define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S))
2448 #define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
2449 #define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S  0
2450 
2451 #define SLC_0_TXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x100)
2452 /* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2453 /*description: */
2454 #define SLC_SLC0_TX_PKT_END_DSCR_ADDR  0xFFFFFFFF
2455 #define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S))
2456 #define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
2457 #define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S  0
2458 
2459 #define SLC_0_RXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0x104)
2460 /* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2461 /*description: */
2462 #define SLC_SLC0_RX_PKT_START_DSCR_ADDR  0xFFFFFFFF
2463 #define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S))
2464 #define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
2465 #define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S  0
2466 
2467 #define SLC_0_RXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x108)
2468 /* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
2469 /*description: */
2470 #define SLC_SLC0_RX_PKT_END_DSCR_ADDR  0xFFFFFFFF
2471 #define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S))
2472 #define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
2473 #define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S  0
2474 
2475 #define SLC_SEQ_POSITION_REG          (DR_REG_SLC_BASE + 0x114)
2476 /* SLC_SLC1_SEQ_POSITION : R/W ;bitpos:[15:8] ;default: 8'h5 ; */
2477 /*description: */
2478 #define SLC_SLC1_SEQ_POSITION  0x000000FF
2479 #define SLC_SLC1_SEQ_POSITION_M  ((SLC_SLC1_SEQ_POSITION_V)<<(SLC_SLC1_SEQ_POSITION_S))
2480 #define SLC_SLC1_SEQ_POSITION_V  0xFF
2481 #define SLC_SLC1_SEQ_POSITION_S  8
2482 /* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */
2483 /*description: */
2484 #define SLC_SLC0_SEQ_POSITION  0x000000FF
2485 #define SLC_SLC0_SEQ_POSITION_M  ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S))
2486 #define SLC_SLC0_SEQ_POSITION_V  0xFF
2487 #define SLC_SLC0_SEQ_POSITION_S  0
2488 
2489 #define SLC_0_DSCR_REC_CONF_REG          (DR_REG_SLC_BASE + 0x118)
2490 /* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
2491 /*description: */
2492 #define SLC_SLC0_RX_DSCR_REC_LIM  0x000003FF
2493 #define SLC_SLC0_RX_DSCR_REC_LIM_M  ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S))
2494 #define SLC_SLC0_RX_DSCR_REC_LIM_V  0x3FF
2495 #define SLC_SLC0_RX_DSCR_REC_LIM_S  0
2496 
2497 #define SLC_SDIO_CRC_ST0_REG          (DR_REG_SLC_BASE + 0x11C)
2498 /* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */
2499 /*description: */
2500 #define SLC_DAT3_CRC_ERR_CNT  0x000000FF
2501 #define SLC_DAT3_CRC_ERR_CNT_M  ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S))
2502 #define SLC_DAT3_CRC_ERR_CNT_V  0xFF
2503 #define SLC_DAT3_CRC_ERR_CNT_S  24
2504 /* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */
2505 /*description: */
2506 #define SLC_DAT2_CRC_ERR_CNT  0x000000FF
2507 #define SLC_DAT2_CRC_ERR_CNT_M  ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S))
2508 #define SLC_DAT2_CRC_ERR_CNT_V  0xFF
2509 #define SLC_DAT2_CRC_ERR_CNT_S  16
2510 /* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */
2511 /*description: */
2512 #define SLC_DAT1_CRC_ERR_CNT  0x000000FF
2513 #define SLC_DAT1_CRC_ERR_CNT_M  ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S))
2514 #define SLC_DAT1_CRC_ERR_CNT_V  0xFF
2515 #define SLC_DAT1_CRC_ERR_CNT_S  8
2516 /* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
2517 /*description: */
2518 #define SLC_DAT0_CRC_ERR_CNT  0x000000FF
2519 #define SLC_DAT0_CRC_ERR_CNT_M  ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S))
2520 #define SLC_DAT0_CRC_ERR_CNT_V  0xFF
2521 #define SLC_DAT0_CRC_ERR_CNT_S  0
2522 
2523 #define SLC_SDIO_CRC_ST1_REG          (DR_REG_SLC_BASE + 0x120)
2524 /* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */
2525 /*description: */
2526 #define SLC_ERR_CNT_CLR  (BIT(31))
2527 #define SLC_ERR_CNT_CLR_M  (BIT(31))
2528 #define SLC_ERR_CNT_CLR_V  0x1
2529 #define SLC_ERR_CNT_CLR_S  31
2530 /* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
2531 /*description: */
2532 #define SLC_CMD_CRC_ERR_CNT  0x000000FF
2533 #define SLC_CMD_CRC_ERR_CNT_M  ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S))
2534 #define SLC_CMD_CRC_ERR_CNT_V  0xFF
2535 #define SLC_CMD_CRC_ERR_CNT_S  0
2536 
2537 #define SLC_0_EOF_START_DES_REG          (DR_REG_SLC_BASE + 0x124)
2538 /* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2539 /*description: */
2540 #define SLC_SLC0_EOF_START_DES_ADDR  0xFFFFFFFF
2541 #define SLC_SLC0_EOF_START_DES_ADDR_M  ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S))
2542 #define SLC_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFF
2543 #define SLC_SLC0_EOF_START_DES_ADDR_S  0
2544 
2545 #define SLC_0_PUSH_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x128)
2546 /* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2547 /*description: */
2548 #define SLC_SLC0_RX_PUSH_DSCR_ADDR  0xFFFFFFFF
2549 #define SLC_SLC0_RX_PUSH_DSCR_ADDR_M  ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S))
2550 #define SLC_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFF
2551 #define SLC_SLC0_RX_PUSH_DSCR_ADDR_S  0
2552 
2553 #define SLC_0_DONE_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x12C)
2554 /* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2555 /*description: */
2556 #define SLC_SLC0_RX_DONE_DSCR_ADDR  0xFFFFFFFF
2557 #define SLC_SLC0_RX_DONE_DSCR_ADDR_M  ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S))
2558 #define SLC_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFF
2559 #define SLC_SLC0_RX_DONE_DSCR_ADDR_S  0
2560 
2561 #define SLC_0_SUB_START_DES_REG          (DR_REG_SLC_BASE + 0x130)
2562 /* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2563 /*description: */
2564 #define SLC_SLC0_SUB_PAC_START_DSCR_ADDR  0xFFFFFFFF
2565 #define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M  ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S))
2566 #define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFF
2567 #define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
2568 
2569 #define SLC_0_DSCR_CNT_REG          (DR_REG_SLC_BASE + 0x134)
2570 /* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */
2571 /*description: */
2572 #define SLC_SLC0_RX_GET_EOF_OCC  (BIT(16))
2573 #define SLC_SLC0_RX_GET_EOF_OCC_M  (BIT(16))
2574 #define SLC_SLC0_RX_GET_EOF_OCC_V  0x1
2575 #define SLC_SLC0_RX_GET_EOF_OCC_S  16
2576 /* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
2577 /*description: */
2578 #define SLC_SLC0_RX_DSCR_CNT_LAT  0x000003FF
2579 #define SLC_SLC0_RX_DSCR_CNT_LAT_M  ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S))
2580 #define SLC_SLC0_RX_DSCR_CNT_LAT_V  0x3FF
2581 #define SLC_SLC0_RX_DSCR_CNT_LAT_S  0
2582 
2583 #define SLC_0_LEN_LIM_CONF_REG          (DR_REG_SLC_BASE + 0x138)
2584 /* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */
2585 /*description: */
2586 #define SLC_SLC0_LEN_LIM  0x000FFFFF
2587 #define SLC_SLC0_LEN_LIM_M  ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S))
2588 #define SLC_SLC0_LEN_LIM_V  0xFFFFF
2589 #define SLC_SLC0_LEN_LIM_S  0
2590 
2591 #define SLC_0INT_ST1_REG          (DR_REG_SLC_BASE + 0x13C)
2592 /* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */
2593 /*description: */
2594 #define SLC_SLC0_RX_QUICK_EOF_INT_ST1  (BIT(26))
2595 #define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M  (BIT(26))
2596 #define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V  0x1
2597 #define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S  26
2598 /* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */
2599 /*description: */
2600 #define SLC_CMD_DTC_INT_ST1  (BIT(25))
2601 #define SLC_CMD_DTC_INT_ST1_M  (BIT(25))
2602 #define SLC_CMD_DTC_INT_ST1_V  0x1
2603 #define SLC_CMD_DTC_INT_ST1_S  25
2604 /* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
2605 /*description: */
2606 #define SLC_SLC0_TX_ERR_EOF_INT_ST1  (BIT(24))
2607 #define SLC_SLC0_TX_ERR_EOF_INT_ST1_M  (BIT(24))
2608 #define SLC_SLC0_TX_ERR_EOF_INT_ST1_V  0x1
2609 #define SLC_SLC0_TX_ERR_EOF_INT_ST1_S  24
2610 /* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
2611 /*description: */
2612 #define SLC_SLC0_WR_RETRY_DONE_INT_ST1  (BIT(23))
2613 #define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M  (BIT(23))
2614 #define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V  0x1
2615 #define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S  23
2616 /* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
2617 /*description: */
2618 #define SLC_SLC0_HOST_RD_ACK_INT_ST1  (BIT(22))
2619 #define SLC_SLC0_HOST_RD_ACK_INT_ST1_M  (BIT(22))
2620 #define SLC_SLC0_HOST_RD_ACK_INT_ST1_V  0x1
2621 #define SLC_SLC0_HOST_RD_ACK_INT_ST1_S  22
2622 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
2623 /*description: */
2624 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1  (BIT(21))
2625 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (BIT(21))
2626 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x1
2627 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
2628 /* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
2629 /*description: */
2630 #define SLC_SLC0_RX_DSCR_ERR_INT_ST1  (BIT(20))
2631 #define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M  (BIT(20))
2632 #define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V  0x1
2633 #define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S  20
2634 /* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
2635 /*description: */
2636 #define SLC_SLC0_TX_DSCR_ERR_INT_ST1  (BIT(19))
2637 #define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M  (BIT(19))
2638 #define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V  0x1
2639 #define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S  19
2640 /* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
2641 /*description: */
2642 #define SLC_SLC0_TOHOST_INT_ST1  (BIT(18))
2643 #define SLC_SLC0_TOHOST_INT_ST1_M  (BIT(18))
2644 #define SLC_SLC0_TOHOST_INT_ST1_V  0x1
2645 #define SLC_SLC0_TOHOST_INT_ST1_S  18
2646 /* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
2647 /*description: */
2648 #define SLC_SLC0_RX_EOF_INT_ST1  (BIT(17))
2649 #define SLC_SLC0_RX_EOF_INT_ST1_M  (BIT(17))
2650 #define SLC_SLC0_RX_EOF_INT_ST1_V  0x1
2651 #define SLC_SLC0_RX_EOF_INT_ST1_S  17
2652 /* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
2653 /*description: */
2654 #define SLC_SLC0_RX_DONE_INT_ST1  (BIT(16))
2655 #define SLC_SLC0_RX_DONE_INT_ST1_M  (BIT(16))
2656 #define SLC_SLC0_RX_DONE_INT_ST1_V  0x1
2657 #define SLC_SLC0_RX_DONE_INT_ST1_S  16
2658 /* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
2659 /*description: */
2660 #define SLC_SLC0_TX_SUC_EOF_INT_ST1  (BIT(15))
2661 #define SLC_SLC0_TX_SUC_EOF_INT_ST1_M  (BIT(15))
2662 #define SLC_SLC0_TX_SUC_EOF_INT_ST1_V  0x1
2663 #define SLC_SLC0_TX_SUC_EOF_INT_ST1_S  15
2664 /* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
2665 /*description: */
2666 #define SLC_SLC0_TX_DONE_INT_ST1  (BIT(14))
2667 #define SLC_SLC0_TX_DONE_INT_ST1_M  (BIT(14))
2668 #define SLC_SLC0_TX_DONE_INT_ST1_V  0x1
2669 #define SLC_SLC0_TX_DONE_INT_ST1_S  14
2670 /* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
2671 /*description: */
2672 #define SLC_SLC0_TOKEN1_1TO0_INT_ST1  (BIT(13))
2673 #define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M  (BIT(13))
2674 #define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V  0x1
2675 #define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S  13
2676 /* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
2677 /*description: */
2678 #define SLC_SLC0_TOKEN0_1TO0_INT_ST1  (BIT(12))
2679 #define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M  (BIT(12))
2680 #define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V  0x1
2681 #define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S  12
2682 /* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
2683 /*description: */
2684 #define SLC_SLC0_TX_OVF_INT_ST1  (BIT(11))
2685 #define SLC_SLC0_TX_OVF_INT_ST1_M  (BIT(11))
2686 #define SLC_SLC0_TX_OVF_INT_ST1_V  0x1
2687 #define SLC_SLC0_TX_OVF_INT_ST1_S  11
2688 /* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
2689 /*description: */
2690 #define SLC_SLC0_RX_UDF_INT_ST1  (BIT(10))
2691 #define SLC_SLC0_RX_UDF_INT_ST1_M  (BIT(10))
2692 #define SLC_SLC0_RX_UDF_INT_ST1_V  0x1
2693 #define SLC_SLC0_RX_UDF_INT_ST1_S  10
2694 /* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
2695 /*description: */
2696 #define SLC_SLC0_TX_START_INT_ST1  (BIT(9))
2697 #define SLC_SLC0_TX_START_INT_ST1_M  (BIT(9))
2698 #define SLC_SLC0_TX_START_INT_ST1_V  0x1
2699 #define SLC_SLC0_TX_START_INT_ST1_S  9
2700 /* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
2701 /*description: */
2702 #define SLC_SLC0_RX_START_INT_ST1  (BIT(8))
2703 #define SLC_SLC0_RX_START_INT_ST1_M  (BIT(8))
2704 #define SLC_SLC0_RX_START_INT_ST1_V  0x1
2705 #define SLC_SLC0_RX_START_INT_ST1_S  8
2706 /* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
2707 /*description: */
2708 #define SLC_FRHOST_BIT7_INT_ST1  (BIT(7))
2709 #define SLC_FRHOST_BIT7_INT_ST1_M  (BIT(7))
2710 #define SLC_FRHOST_BIT7_INT_ST1_V  0x1
2711 #define SLC_FRHOST_BIT7_INT_ST1_S  7
2712 /* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
2713 /*description: */
2714 #define SLC_FRHOST_BIT6_INT_ST1  (BIT(6))
2715 #define SLC_FRHOST_BIT6_INT_ST1_M  (BIT(6))
2716 #define SLC_FRHOST_BIT6_INT_ST1_V  0x1
2717 #define SLC_FRHOST_BIT6_INT_ST1_S  6
2718 /* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
2719 /*description: */
2720 #define SLC_FRHOST_BIT5_INT_ST1  (BIT(5))
2721 #define SLC_FRHOST_BIT5_INT_ST1_M  (BIT(5))
2722 #define SLC_FRHOST_BIT5_INT_ST1_V  0x1
2723 #define SLC_FRHOST_BIT5_INT_ST1_S  5
2724 /* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
2725 /*description: */
2726 #define SLC_FRHOST_BIT4_INT_ST1  (BIT(4))
2727 #define SLC_FRHOST_BIT4_INT_ST1_M  (BIT(4))
2728 #define SLC_FRHOST_BIT4_INT_ST1_V  0x1
2729 #define SLC_FRHOST_BIT4_INT_ST1_S  4
2730 /* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
2731 /*description: */
2732 #define SLC_FRHOST_BIT3_INT_ST1  (BIT(3))
2733 #define SLC_FRHOST_BIT3_INT_ST1_M  (BIT(3))
2734 #define SLC_FRHOST_BIT3_INT_ST1_V  0x1
2735 #define SLC_FRHOST_BIT3_INT_ST1_S  3
2736 /* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
2737 /*description: */
2738 #define SLC_FRHOST_BIT2_INT_ST1  (BIT(2))
2739 #define SLC_FRHOST_BIT2_INT_ST1_M  (BIT(2))
2740 #define SLC_FRHOST_BIT2_INT_ST1_V  0x1
2741 #define SLC_FRHOST_BIT2_INT_ST1_S  2
2742 /* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
2743 /*description: */
2744 #define SLC_FRHOST_BIT1_INT_ST1  (BIT(1))
2745 #define SLC_FRHOST_BIT1_INT_ST1_M  (BIT(1))
2746 #define SLC_FRHOST_BIT1_INT_ST1_V  0x1
2747 #define SLC_FRHOST_BIT1_INT_ST1_S  1
2748 /* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
2749 /*description: */
2750 #define SLC_FRHOST_BIT0_INT_ST1  (BIT(0))
2751 #define SLC_FRHOST_BIT0_INT_ST1_M  (BIT(0))
2752 #define SLC_FRHOST_BIT0_INT_ST1_V  0x1
2753 #define SLC_FRHOST_BIT0_INT_ST1_S  0
2754 
2755 #define SLC_0INT_ENA1_REG          (DR_REG_SLC_BASE + 0x140)
2756 /* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */
2757 /*description: */
2758 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA1  (BIT(26))
2759 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M  (BIT(26))
2760 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x1
2761 #define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
2762 /* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
2763 /*description: */
2764 #define SLC_CMD_DTC_INT_ENA1  (BIT(25))
2765 #define SLC_CMD_DTC_INT_ENA1_M  (BIT(25))
2766 #define SLC_CMD_DTC_INT_ENA1_V  0x1
2767 #define SLC_CMD_DTC_INT_ENA1_S  25
2768 /* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
2769 /*description: */
2770 #define SLC_SLC0_TX_ERR_EOF_INT_ENA1  (BIT(24))
2771 #define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M  (BIT(24))
2772 #define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V  0x1
2773 #define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S  24
2774 /* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
2775 /*description: */
2776 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA1  (BIT(23))
2777 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M  (BIT(23))
2778 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x1
2779 #define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
2780 /* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
2781 /*description: */
2782 #define SLC_SLC0_HOST_RD_ACK_INT_ENA1  (BIT(22))
2783 #define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M  (BIT(22))
2784 #define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V  0x1
2785 #define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S  22
2786 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
2787 /*description: */
2788 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1  (BIT(21))
2789 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (BIT(21))
2790 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x1
2791 #define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
2792 /* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
2793 /*description: */
2794 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA1  (BIT(20))
2795 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M  (BIT(20))
2796 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x1
2797 #define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
2798 /* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
2799 /*description: */
2800 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA1  (BIT(19))
2801 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M  (BIT(19))
2802 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x1
2803 #define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
2804 /* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
2805 /*description: */
2806 #define SLC_SLC0_TOHOST_INT_ENA1  (BIT(18))
2807 #define SLC_SLC0_TOHOST_INT_ENA1_M  (BIT(18))
2808 #define SLC_SLC0_TOHOST_INT_ENA1_V  0x1
2809 #define SLC_SLC0_TOHOST_INT_ENA1_S  18
2810 /* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
2811 /*description: */
2812 #define SLC_SLC0_RX_EOF_INT_ENA1  (BIT(17))
2813 #define SLC_SLC0_RX_EOF_INT_ENA1_M  (BIT(17))
2814 #define SLC_SLC0_RX_EOF_INT_ENA1_V  0x1
2815 #define SLC_SLC0_RX_EOF_INT_ENA1_S  17
2816 /* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
2817 /*description: */
2818 #define SLC_SLC0_RX_DONE_INT_ENA1  (BIT(16))
2819 #define SLC_SLC0_RX_DONE_INT_ENA1_M  (BIT(16))
2820 #define SLC_SLC0_RX_DONE_INT_ENA1_V  0x1
2821 #define SLC_SLC0_RX_DONE_INT_ENA1_S  16
2822 /* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
2823 /*description: */
2824 #define SLC_SLC0_TX_SUC_EOF_INT_ENA1  (BIT(15))
2825 #define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M  (BIT(15))
2826 #define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V  0x1
2827 #define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S  15
2828 /* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
2829 /*description: */
2830 #define SLC_SLC0_TX_DONE_INT_ENA1  (BIT(14))
2831 #define SLC_SLC0_TX_DONE_INT_ENA1_M  (BIT(14))
2832 #define SLC_SLC0_TX_DONE_INT_ENA1_V  0x1
2833 #define SLC_SLC0_TX_DONE_INT_ENA1_S  14
2834 /* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
2835 /*description: */
2836 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA1  (BIT(13))
2837 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(13))
2838 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
2839 #define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
2840 /* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
2841 /*description: */
2842 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA1  (BIT(12))
2843 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(12))
2844 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
2845 #define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
2846 /* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
2847 /*description: */
2848 #define SLC_SLC0_TX_OVF_INT_ENA1  (BIT(11))
2849 #define SLC_SLC0_TX_OVF_INT_ENA1_M  (BIT(11))
2850 #define SLC_SLC0_TX_OVF_INT_ENA1_V  0x1
2851 #define SLC_SLC0_TX_OVF_INT_ENA1_S  11
2852 /* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
2853 /*description: */
2854 #define SLC_SLC0_RX_UDF_INT_ENA1  (BIT(10))
2855 #define SLC_SLC0_RX_UDF_INT_ENA1_M  (BIT(10))
2856 #define SLC_SLC0_RX_UDF_INT_ENA1_V  0x1
2857 #define SLC_SLC0_RX_UDF_INT_ENA1_S  10
2858 /* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
2859 /*description: */
2860 #define SLC_SLC0_TX_START_INT_ENA1  (BIT(9))
2861 #define SLC_SLC0_TX_START_INT_ENA1_M  (BIT(9))
2862 #define SLC_SLC0_TX_START_INT_ENA1_V  0x1
2863 #define SLC_SLC0_TX_START_INT_ENA1_S  9
2864 /* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
2865 /*description: */
2866 #define SLC_SLC0_RX_START_INT_ENA1  (BIT(8))
2867 #define SLC_SLC0_RX_START_INT_ENA1_M  (BIT(8))
2868 #define SLC_SLC0_RX_START_INT_ENA1_V  0x1
2869 #define SLC_SLC0_RX_START_INT_ENA1_S  8
2870 /* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
2871 /*description: */
2872 #define SLC_FRHOST_BIT7_INT_ENA1  (BIT(7))
2873 #define SLC_FRHOST_BIT7_INT_ENA1_M  (BIT(7))
2874 #define SLC_FRHOST_BIT7_INT_ENA1_V  0x1
2875 #define SLC_FRHOST_BIT7_INT_ENA1_S  7
2876 /* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
2877 /*description: */
2878 #define SLC_FRHOST_BIT6_INT_ENA1  (BIT(6))
2879 #define SLC_FRHOST_BIT6_INT_ENA1_M  (BIT(6))
2880 #define SLC_FRHOST_BIT6_INT_ENA1_V  0x1
2881 #define SLC_FRHOST_BIT6_INT_ENA1_S  6
2882 /* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
2883 /*description: */
2884 #define SLC_FRHOST_BIT5_INT_ENA1  (BIT(5))
2885 #define SLC_FRHOST_BIT5_INT_ENA1_M  (BIT(5))
2886 #define SLC_FRHOST_BIT5_INT_ENA1_V  0x1
2887 #define SLC_FRHOST_BIT5_INT_ENA1_S  5
2888 /* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
2889 /*description: */
2890 #define SLC_FRHOST_BIT4_INT_ENA1  (BIT(4))
2891 #define SLC_FRHOST_BIT4_INT_ENA1_M  (BIT(4))
2892 #define SLC_FRHOST_BIT4_INT_ENA1_V  0x1
2893 #define SLC_FRHOST_BIT4_INT_ENA1_S  4
2894 /* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
2895 /*description: */
2896 #define SLC_FRHOST_BIT3_INT_ENA1  (BIT(3))
2897 #define SLC_FRHOST_BIT3_INT_ENA1_M  (BIT(3))
2898 #define SLC_FRHOST_BIT3_INT_ENA1_V  0x1
2899 #define SLC_FRHOST_BIT3_INT_ENA1_S  3
2900 /* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
2901 /*description: */
2902 #define SLC_FRHOST_BIT2_INT_ENA1  (BIT(2))
2903 #define SLC_FRHOST_BIT2_INT_ENA1_M  (BIT(2))
2904 #define SLC_FRHOST_BIT2_INT_ENA1_V  0x1
2905 #define SLC_FRHOST_BIT2_INT_ENA1_S  2
2906 /* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
2907 /*description: */
2908 #define SLC_FRHOST_BIT1_INT_ENA1  (BIT(1))
2909 #define SLC_FRHOST_BIT1_INT_ENA1_M  (BIT(1))
2910 #define SLC_FRHOST_BIT1_INT_ENA1_V  0x1
2911 #define SLC_FRHOST_BIT1_INT_ENA1_S  1
2912 /* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
2913 /*description: */
2914 #define SLC_FRHOST_BIT0_INT_ENA1  (BIT(0))
2915 #define SLC_FRHOST_BIT0_INT_ENA1_M  (BIT(0))
2916 #define SLC_FRHOST_BIT0_INT_ENA1_V  0x1
2917 #define SLC_FRHOST_BIT0_INT_ENA1_S  0
2918 
2919 #define SLC_1INT_ST1_REG          (DR_REG_SLC_BASE + 0x144)
2920 /* SLC_SLC1_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
2921 /*description: */
2922 #define SLC_SLC1_TX_ERR_EOF_INT_ST1  (BIT(24))
2923 #define SLC_SLC1_TX_ERR_EOF_INT_ST1_M  (BIT(24))
2924 #define SLC_SLC1_TX_ERR_EOF_INT_ST1_V  0x1
2925 #define SLC_SLC1_TX_ERR_EOF_INT_ST1_S  24
2926 /* SLC_SLC1_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
2927 /*description: */
2928 #define SLC_SLC1_WR_RETRY_DONE_INT_ST1  (BIT(23))
2929 #define SLC_SLC1_WR_RETRY_DONE_INT_ST1_M  (BIT(23))
2930 #define SLC_SLC1_WR_RETRY_DONE_INT_ST1_V  0x1
2931 #define SLC_SLC1_WR_RETRY_DONE_INT_ST1_S  23
2932 /* SLC_SLC1_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
2933 /*description: */
2934 #define SLC_SLC1_HOST_RD_ACK_INT_ST1  (BIT(22))
2935 #define SLC_SLC1_HOST_RD_ACK_INT_ST1_M  (BIT(22))
2936 #define SLC_SLC1_HOST_RD_ACK_INT_ST1_V  0x1
2937 #define SLC_SLC1_HOST_RD_ACK_INT_ST1_S  22
2938 /* SLC_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
2939 /*description: */
2940 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1  (BIT(21))
2941 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_M  (BIT(21))
2942 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_V  0x1
2943 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_S  21
2944 /* SLC_SLC1_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
2945 /*description: */
2946 #define SLC_SLC1_RX_DSCR_ERR_INT_ST1  (BIT(20))
2947 #define SLC_SLC1_RX_DSCR_ERR_INT_ST1_M  (BIT(20))
2948 #define SLC_SLC1_RX_DSCR_ERR_INT_ST1_V  0x1
2949 #define SLC_SLC1_RX_DSCR_ERR_INT_ST1_S  20
2950 /* SLC_SLC1_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
2951 /*description: */
2952 #define SLC_SLC1_TX_DSCR_ERR_INT_ST1  (BIT(19))
2953 #define SLC_SLC1_TX_DSCR_ERR_INT_ST1_M  (BIT(19))
2954 #define SLC_SLC1_TX_DSCR_ERR_INT_ST1_V  0x1
2955 #define SLC_SLC1_TX_DSCR_ERR_INT_ST1_S  19
2956 /* SLC_SLC1_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
2957 /*description: */
2958 #define SLC_SLC1_TOHOST_INT_ST1  (BIT(18))
2959 #define SLC_SLC1_TOHOST_INT_ST1_M  (BIT(18))
2960 #define SLC_SLC1_TOHOST_INT_ST1_V  0x1
2961 #define SLC_SLC1_TOHOST_INT_ST1_S  18
2962 /* SLC_SLC1_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
2963 /*description: */
2964 #define SLC_SLC1_RX_EOF_INT_ST1  (BIT(17))
2965 #define SLC_SLC1_RX_EOF_INT_ST1_M  (BIT(17))
2966 #define SLC_SLC1_RX_EOF_INT_ST1_V  0x1
2967 #define SLC_SLC1_RX_EOF_INT_ST1_S  17
2968 /* SLC_SLC1_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
2969 /*description: */
2970 #define SLC_SLC1_RX_DONE_INT_ST1  (BIT(16))
2971 #define SLC_SLC1_RX_DONE_INT_ST1_M  (BIT(16))
2972 #define SLC_SLC1_RX_DONE_INT_ST1_V  0x1
2973 #define SLC_SLC1_RX_DONE_INT_ST1_S  16
2974 /* SLC_SLC1_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
2975 /*description: */
2976 #define SLC_SLC1_TX_SUC_EOF_INT_ST1  (BIT(15))
2977 #define SLC_SLC1_TX_SUC_EOF_INT_ST1_M  (BIT(15))
2978 #define SLC_SLC1_TX_SUC_EOF_INT_ST1_V  0x1
2979 #define SLC_SLC1_TX_SUC_EOF_INT_ST1_S  15
2980 /* SLC_SLC1_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
2981 /*description: */
2982 #define SLC_SLC1_TX_DONE_INT_ST1  (BIT(14))
2983 #define SLC_SLC1_TX_DONE_INT_ST1_M  (BIT(14))
2984 #define SLC_SLC1_TX_DONE_INT_ST1_V  0x1
2985 #define SLC_SLC1_TX_DONE_INT_ST1_S  14
2986 /* SLC_SLC1_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
2987 /*description: */
2988 #define SLC_SLC1_TOKEN1_1TO0_INT_ST1  (BIT(13))
2989 #define SLC_SLC1_TOKEN1_1TO0_INT_ST1_M  (BIT(13))
2990 #define SLC_SLC1_TOKEN1_1TO0_INT_ST1_V  0x1
2991 #define SLC_SLC1_TOKEN1_1TO0_INT_ST1_S  13
2992 /* SLC_SLC1_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
2993 /*description: */
2994 #define SLC_SLC1_TOKEN0_1TO0_INT_ST1  (BIT(12))
2995 #define SLC_SLC1_TOKEN0_1TO0_INT_ST1_M  (BIT(12))
2996 #define SLC_SLC1_TOKEN0_1TO0_INT_ST1_V  0x1
2997 #define SLC_SLC1_TOKEN0_1TO0_INT_ST1_S  12
2998 /* SLC_SLC1_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
2999 /*description: */
3000 #define SLC_SLC1_TX_OVF_INT_ST1  (BIT(11))
3001 #define SLC_SLC1_TX_OVF_INT_ST1_M  (BIT(11))
3002 #define SLC_SLC1_TX_OVF_INT_ST1_V  0x1
3003 #define SLC_SLC1_TX_OVF_INT_ST1_S  11
3004 /* SLC_SLC1_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
3005 /*description: */
3006 #define SLC_SLC1_RX_UDF_INT_ST1  (BIT(10))
3007 #define SLC_SLC1_RX_UDF_INT_ST1_M  (BIT(10))
3008 #define SLC_SLC1_RX_UDF_INT_ST1_V  0x1
3009 #define SLC_SLC1_RX_UDF_INT_ST1_S  10
3010 /* SLC_SLC1_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
3011 /*description: */
3012 #define SLC_SLC1_TX_START_INT_ST1  (BIT(9))
3013 #define SLC_SLC1_TX_START_INT_ST1_M  (BIT(9))
3014 #define SLC_SLC1_TX_START_INT_ST1_V  0x1
3015 #define SLC_SLC1_TX_START_INT_ST1_S  9
3016 /* SLC_SLC1_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
3017 /*description: */
3018 #define SLC_SLC1_RX_START_INT_ST1  (BIT(8))
3019 #define SLC_SLC1_RX_START_INT_ST1_M  (BIT(8))
3020 #define SLC_SLC1_RX_START_INT_ST1_V  0x1
3021 #define SLC_SLC1_RX_START_INT_ST1_S  8
3022 /* SLC_FRHOST_BIT15_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
3023 /*description: */
3024 #define SLC_FRHOST_BIT15_INT_ST1  (BIT(7))
3025 #define SLC_FRHOST_BIT15_INT_ST1_M  (BIT(7))
3026 #define SLC_FRHOST_BIT15_INT_ST1_V  0x1
3027 #define SLC_FRHOST_BIT15_INT_ST1_S  7
3028 /* SLC_FRHOST_BIT14_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
3029 /*description: */
3030 #define SLC_FRHOST_BIT14_INT_ST1  (BIT(6))
3031 #define SLC_FRHOST_BIT14_INT_ST1_M  (BIT(6))
3032 #define SLC_FRHOST_BIT14_INT_ST1_V  0x1
3033 #define SLC_FRHOST_BIT14_INT_ST1_S  6
3034 /* SLC_FRHOST_BIT13_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
3035 /*description: */
3036 #define SLC_FRHOST_BIT13_INT_ST1  (BIT(5))
3037 #define SLC_FRHOST_BIT13_INT_ST1_M  (BIT(5))
3038 #define SLC_FRHOST_BIT13_INT_ST1_V  0x1
3039 #define SLC_FRHOST_BIT13_INT_ST1_S  5
3040 /* SLC_FRHOST_BIT12_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
3041 /*description: */
3042 #define SLC_FRHOST_BIT12_INT_ST1  (BIT(4))
3043 #define SLC_FRHOST_BIT12_INT_ST1_M  (BIT(4))
3044 #define SLC_FRHOST_BIT12_INT_ST1_V  0x1
3045 #define SLC_FRHOST_BIT12_INT_ST1_S  4
3046 /* SLC_FRHOST_BIT11_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
3047 /*description: */
3048 #define SLC_FRHOST_BIT11_INT_ST1  (BIT(3))
3049 #define SLC_FRHOST_BIT11_INT_ST1_M  (BIT(3))
3050 #define SLC_FRHOST_BIT11_INT_ST1_V  0x1
3051 #define SLC_FRHOST_BIT11_INT_ST1_S  3
3052 /* SLC_FRHOST_BIT10_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
3053 /*description: */
3054 #define SLC_FRHOST_BIT10_INT_ST1  (BIT(2))
3055 #define SLC_FRHOST_BIT10_INT_ST1_M  (BIT(2))
3056 #define SLC_FRHOST_BIT10_INT_ST1_V  0x1
3057 #define SLC_FRHOST_BIT10_INT_ST1_S  2
3058 /* SLC_FRHOST_BIT9_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
3059 /*description: */
3060 #define SLC_FRHOST_BIT9_INT_ST1  (BIT(1))
3061 #define SLC_FRHOST_BIT9_INT_ST1_M  (BIT(1))
3062 #define SLC_FRHOST_BIT9_INT_ST1_V  0x1
3063 #define SLC_FRHOST_BIT9_INT_ST1_S  1
3064 /* SLC_FRHOST_BIT8_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
3065 /*description: */
3066 #define SLC_FRHOST_BIT8_INT_ST1  (BIT(0))
3067 #define SLC_FRHOST_BIT8_INT_ST1_M  (BIT(0))
3068 #define SLC_FRHOST_BIT8_INT_ST1_V  0x1
3069 #define SLC_FRHOST_BIT8_INT_ST1_S  0
3070 
3071 #define SLC_1INT_ENA1_REG          (DR_REG_SLC_BASE + 0x148)
3072 /* SLC_SLC1_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
3073 /*description: */
3074 #define SLC_SLC1_TX_ERR_EOF_INT_ENA1  (BIT(24))
3075 #define SLC_SLC1_TX_ERR_EOF_INT_ENA1_M  (BIT(24))
3076 #define SLC_SLC1_TX_ERR_EOF_INT_ENA1_V  0x1
3077 #define SLC_SLC1_TX_ERR_EOF_INT_ENA1_S  24
3078 /* SLC_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
3079 /*description: */
3080 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA1  (BIT(23))
3081 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_M  (BIT(23))
3082 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_V  0x1
3083 #define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_S  23
3084 /* SLC_SLC1_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
3085 /*description: */
3086 #define SLC_SLC1_HOST_RD_ACK_INT_ENA1  (BIT(22))
3087 #define SLC_SLC1_HOST_RD_ACK_INT_ENA1_M  (BIT(22))
3088 #define SLC_SLC1_HOST_RD_ACK_INT_ENA1_V  0x1
3089 #define SLC_SLC1_HOST_RD_ACK_INT_ENA1_S  22
3090 /* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
3091 /*description: */
3092 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1  (BIT(21))
3093 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_M  (BIT(21))
3094 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_V  0x1
3095 #define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_S  21
3096 /* SLC_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
3097 /*description: */
3098 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA1  (BIT(20))
3099 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_M  (BIT(20))
3100 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_V  0x1
3101 #define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_S  20
3102 /* SLC_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
3103 /*description: */
3104 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA1  (BIT(19))
3105 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_M  (BIT(19))
3106 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_V  0x1
3107 #define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_S  19
3108 /* SLC_SLC1_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
3109 /*description: */
3110 #define SLC_SLC1_TOHOST_INT_ENA1  (BIT(18))
3111 #define SLC_SLC1_TOHOST_INT_ENA1_M  (BIT(18))
3112 #define SLC_SLC1_TOHOST_INT_ENA1_V  0x1
3113 #define SLC_SLC1_TOHOST_INT_ENA1_S  18
3114 /* SLC_SLC1_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
3115 /*description: */
3116 #define SLC_SLC1_RX_EOF_INT_ENA1  (BIT(17))
3117 #define SLC_SLC1_RX_EOF_INT_ENA1_M  (BIT(17))
3118 #define SLC_SLC1_RX_EOF_INT_ENA1_V  0x1
3119 #define SLC_SLC1_RX_EOF_INT_ENA1_S  17
3120 /* SLC_SLC1_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
3121 /*description: */
3122 #define SLC_SLC1_RX_DONE_INT_ENA1  (BIT(16))
3123 #define SLC_SLC1_RX_DONE_INT_ENA1_M  (BIT(16))
3124 #define SLC_SLC1_RX_DONE_INT_ENA1_V  0x1
3125 #define SLC_SLC1_RX_DONE_INT_ENA1_S  16
3126 /* SLC_SLC1_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
3127 /*description: */
3128 #define SLC_SLC1_TX_SUC_EOF_INT_ENA1  (BIT(15))
3129 #define SLC_SLC1_TX_SUC_EOF_INT_ENA1_M  (BIT(15))
3130 #define SLC_SLC1_TX_SUC_EOF_INT_ENA1_V  0x1
3131 #define SLC_SLC1_TX_SUC_EOF_INT_ENA1_S  15
3132 /* SLC_SLC1_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
3133 /*description: */
3134 #define SLC_SLC1_TX_DONE_INT_ENA1  (BIT(14))
3135 #define SLC_SLC1_TX_DONE_INT_ENA1_M  (BIT(14))
3136 #define SLC_SLC1_TX_DONE_INT_ENA1_V  0x1
3137 #define SLC_SLC1_TX_DONE_INT_ENA1_S  14
3138 /* SLC_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
3139 /*description: */
3140 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA1  (BIT(13))
3141 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_M  (BIT(13))
3142 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x1
3143 #define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_S  13
3144 /* SLC_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
3145 /*description: */
3146 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA1  (BIT(12))
3147 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_M  (BIT(12))
3148 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x1
3149 #define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_S  12
3150 /* SLC_SLC1_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
3151 /*description: */
3152 #define SLC_SLC1_TX_OVF_INT_ENA1  (BIT(11))
3153 #define SLC_SLC1_TX_OVF_INT_ENA1_M  (BIT(11))
3154 #define SLC_SLC1_TX_OVF_INT_ENA1_V  0x1
3155 #define SLC_SLC1_TX_OVF_INT_ENA1_S  11
3156 /* SLC_SLC1_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
3157 /*description: */
3158 #define SLC_SLC1_RX_UDF_INT_ENA1  (BIT(10))
3159 #define SLC_SLC1_RX_UDF_INT_ENA1_M  (BIT(10))
3160 #define SLC_SLC1_RX_UDF_INT_ENA1_V  0x1
3161 #define SLC_SLC1_RX_UDF_INT_ENA1_S  10
3162 /* SLC_SLC1_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
3163 /*description: */
3164 #define SLC_SLC1_TX_START_INT_ENA1  (BIT(9))
3165 #define SLC_SLC1_TX_START_INT_ENA1_M  (BIT(9))
3166 #define SLC_SLC1_TX_START_INT_ENA1_V  0x1
3167 #define SLC_SLC1_TX_START_INT_ENA1_S  9
3168 /* SLC_SLC1_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
3169 /*description: */
3170 #define SLC_SLC1_RX_START_INT_ENA1  (BIT(8))
3171 #define SLC_SLC1_RX_START_INT_ENA1_M  (BIT(8))
3172 #define SLC_SLC1_RX_START_INT_ENA1_V  0x1
3173 #define SLC_SLC1_RX_START_INT_ENA1_S  8
3174 /* SLC_FRHOST_BIT15_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
3175 /*description: */
3176 #define SLC_FRHOST_BIT15_INT_ENA1  (BIT(7))
3177 #define SLC_FRHOST_BIT15_INT_ENA1_M  (BIT(7))
3178 #define SLC_FRHOST_BIT15_INT_ENA1_V  0x1
3179 #define SLC_FRHOST_BIT15_INT_ENA1_S  7
3180 /* SLC_FRHOST_BIT14_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
3181 /*description: */
3182 #define SLC_FRHOST_BIT14_INT_ENA1  (BIT(6))
3183 #define SLC_FRHOST_BIT14_INT_ENA1_M  (BIT(6))
3184 #define SLC_FRHOST_BIT14_INT_ENA1_V  0x1
3185 #define SLC_FRHOST_BIT14_INT_ENA1_S  6
3186 /* SLC_FRHOST_BIT13_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
3187 /*description: */
3188 #define SLC_FRHOST_BIT13_INT_ENA1  (BIT(5))
3189 #define SLC_FRHOST_BIT13_INT_ENA1_M  (BIT(5))
3190 #define SLC_FRHOST_BIT13_INT_ENA1_V  0x1
3191 #define SLC_FRHOST_BIT13_INT_ENA1_S  5
3192 /* SLC_FRHOST_BIT12_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
3193 /*description: */
3194 #define SLC_FRHOST_BIT12_INT_ENA1  (BIT(4))
3195 #define SLC_FRHOST_BIT12_INT_ENA1_M  (BIT(4))
3196 #define SLC_FRHOST_BIT12_INT_ENA1_V  0x1
3197 #define SLC_FRHOST_BIT12_INT_ENA1_S  4
3198 /* SLC_FRHOST_BIT11_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
3199 /*description: */
3200 #define SLC_FRHOST_BIT11_INT_ENA1  (BIT(3))
3201 #define SLC_FRHOST_BIT11_INT_ENA1_M  (BIT(3))
3202 #define SLC_FRHOST_BIT11_INT_ENA1_V  0x1
3203 #define SLC_FRHOST_BIT11_INT_ENA1_S  3
3204 /* SLC_FRHOST_BIT10_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
3205 /*description: */
3206 #define SLC_FRHOST_BIT10_INT_ENA1  (BIT(2))
3207 #define SLC_FRHOST_BIT10_INT_ENA1_M  (BIT(2))
3208 #define SLC_FRHOST_BIT10_INT_ENA1_V  0x1
3209 #define SLC_FRHOST_BIT10_INT_ENA1_S  2
3210 /* SLC_FRHOST_BIT9_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
3211 /*description: */
3212 #define SLC_FRHOST_BIT9_INT_ENA1  (BIT(1))
3213 #define SLC_FRHOST_BIT9_INT_ENA1_M  (BIT(1))
3214 #define SLC_FRHOST_BIT9_INT_ENA1_V  0x1
3215 #define SLC_FRHOST_BIT9_INT_ENA1_S  1
3216 /* SLC_FRHOST_BIT8_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
3217 /*description: */
3218 #define SLC_FRHOST_BIT8_INT_ENA1  (BIT(0))
3219 #define SLC_FRHOST_BIT8_INT_ENA1_M  (BIT(0))
3220 #define SLC_FRHOST_BIT8_INT_ENA1_V  0x1
3221 #define SLC_FRHOST_BIT8_INT_ENA1_S  0
3222 
3223 #define SLC_DATE_REG          (DR_REG_SLC_BASE + 0x1F8)
3224 /* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022500 ; */
3225 /*description: */
3226 #define SLC_DATE  0xFFFFFFFF
3227 #define SLC_DATE_M  ((SLC_DATE_V)<<(SLC_DATE_S))
3228 #define SLC_DATE_V  0xFFFFFFFF
3229 #define SLC_DATE_S  0
3230 
3231 #define SLC_ID_REG          (DR_REG_SLC_BASE + 0x1FC)
3232 /* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */
3233 /*description: */
3234 #define SLC_ID  0xFFFFFFFF
3235 #define SLC_ID_M  ((SLC_ID_V)<<(SLC_ID_S))
3236 #define SLC_ID_V  0xFFFFFFFF
3237 #define SLC_ID_S  0
3238 
3239 
3240 
3241 
3242 #endif /*_SOC_SLC_REG_H_ */
3243