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Searched refs:SENS_SAR1_DIG_FORCE (Results 1 – 9 of 9) sorted by relevance

/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c56 SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); in soc_random_enable()
84 CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); in soc_random_disable()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32s2.c61 SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG,SENS_SAR1_DIG_FORCE); in bootloader_random_enable()
89 CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); in bootloader_random_disable()
Dbootloader_random_esp32s3.c55 SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); in bootloader_random_enable()
89 CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); in bootloader_random_disable()
Dbootloader_random_esp32.c58 SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); in bootloader_random_enable()
98 CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); in bootloader_random_disable()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c64 SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); in soc_random_enable()
97 CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32/src/
Dsoc_random.c48 SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); in soc_random_enable()
90 CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); in soc_random_disable()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dsens_reg.h28 #define SENS_SAR1_DIG_FORCE (BIT(27)) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dsens_reg.h144 #define SENS_SAR1_DIG_FORCE (BIT(31)) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dsens_reg.h130 #define SENS_SAR1_DIG_FORCE (BIT(31)) macro