1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SENS_REG_H_ 15 #define _SOC_SENS_REG_H_ 16 17 18 #include "soc.h" 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0) 24 /* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ 25 /*description: enable saradc1 to send out interrupt.*/ 26 #define SENS_SAR1_INT_EN (BIT(29)) 27 #define SENS_SAR1_INT_EN_M (BIT(29)) 28 #define SENS_SAR1_INT_EN_V 0x1 29 #define SENS_SAR1_INT_EN_S 29 30 /* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ 31 /*description: Invert SAR ADC1 data.*/ 32 #define SENS_SAR1_DATA_INV (BIT(28)) 33 #define SENS_SAR1_DATA_INV_M (BIT(28)) 34 #define SENS_SAR1_DATA_INV_V 0x1 35 #define SENS_SAR1_DATA_INV_S 28 36 /* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ 37 /*description: .*/ 38 #define SENS_SAR1_SAMPLE_NUM 0x000000FF 39 #define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S)) 40 #define SENS_SAR1_SAMPLE_NUM_V 0xFF 41 #define SENS_SAR1_SAMPLE_NUM_S 19 42 /* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ 43 /*description: .*/ 44 #define SENS_SAR1_CLK_GATED (BIT(18)) 45 #define SENS_SAR1_CLK_GATED_M (BIT(18)) 46 #define SENS_SAR1_CLK_GATED_V 0x1 47 #define SENS_SAR1_CLK_GATED_S 18 48 /* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ 49 /*description: clock divider.*/ 50 #define SENS_SAR1_CLK_DIV 0x000000FF 51 #define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S)) 52 #define SENS_SAR1_CLK_DIV_V 0xFF 53 #define SENS_SAR1_CLK_DIV_S 0 54 55 #define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x4) 56 /* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 57 /*description: .*/ 58 #define SENS_SAR1_READER_STATUS 0xFFFFFFFF 59 #define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S)) 60 #define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF 61 #define SENS_SAR1_READER_STATUS_S 0 62 63 #define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x8) 64 /* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ 65 /*description: .*/ 66 #define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 67 #define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) 68 #define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 69 #define SENS_AMP_SHORT_REF_GND_FORCE_S 30 70 /* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */ 71 /*description: .*/ 72 #define SENS_AMP_SHORT_REF_FORCE 0x00000003 73 #define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) 74 #define SENS_AMP_SHORT_REF_FORCE_V 0x3 75 #define SENS_AMP_SHORT_REF_FORCE_S 28 76 /* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ 77 /*description: .*/ 78 #define SENS_AMP_RST_FB_FORCE 0x00000003 79 #define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) 80 #define SENS_AMP_RST_FB_FORCE_V 0x3 81 #define SENS_AMP_RST_FB_FORCE_S 26 82 /* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ 83 /*description: .*/ 84 #define SENS_FORCE_XPD_AMP 0x00000003 85 #define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S)) 86 #define SENS_FORCE_XPD_AMP_V 0x3 87 #define SENS_FORCE_XPD_AMP_S 24 88 89 #define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0xC) 90 /* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 91 /*description: 1: SAR ADC1 pad enable bitmap is controlled by SW.*/ 92 #define SENS_SAR1_EN_PAD_FORCE (BIT(31)) 93 #define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) 94 #define SENS_SAR1_EN_PAD_FORCE_V 0x1 95 #define SENS_SAR1_EN_PAD_FORCE_S 31 96 /* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ 97 /*description: SAR ADC1 pad enable bitmap.*/ 98 #define SENS_SAR1_EN_PAD 0x00000FFF 99 #define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S)) 100 #define SENS_SAR1_EN_PAD_V 0xFFF 101 #define SENS_SAR1_EN_PAD_S 19 102 /* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ 103 /*description: 1: SAR ADC1 controller (in RTC) is started by SW.*/ 104 #define SENS_MEAS1_START_FORCE (BIT(18)) 105 #define SENS_MEAS1_START_FORCE_M (BIT(18)) 106 #define SENS_MEAS1_START_FORCE_V 0x1 107 #define SENS_MEAS1_START_FORCE_S 18 108 /* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 109 /*description: SAR ADC1 controller (in RTC) starts conversion.*/ 110 #define SENS_MEAS1_START_SAR (BIT(17)) 111 #define SENS_MEAS1_START_SAR_M (BIT(17)) 112 #define SENS_MEAS1_START_SAR_V 0x1 113 #define SENS_MEAS1_START_SAR_S 17 114 /* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ 115 /*description: SAR ADC1 conversion done indication.*/ 116 #define SENS_MEAS1_DONE_SAR (BIT(16)) 117 #define SENS_MEAS1_DONE_SAR_M (BIT(16)) 118 #define SENS_MEAS1_DONE_SAR_V 0x1 119 #define SENS_MEAS1_DONE_SAR_S 16 120 /* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ 121 /*description: SAR ADC1 data.*/ 122 #define SENS_MEAS1_DATA_SAR 0x0000FFFF 123 #define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S)) 124 #define SENS_MEAS1_DATA_SAR_V 0xFFFF 125 #define SENS_MEAS1_DATA_SAR_S 0 126 127 #define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x10) 128 /* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[31] ;default: 1'd0 ; */ 129 /*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL.*/ 130 #define SENS_SAR1_DIG_FORCE (BIT(31)) 131 #define SENS_SAR1_DIG_FORCE_M (BIT(31)) 132 #define SENS_SAR1_DIG_FORCE_V 0x1 133 #define SENS_SAR1_DIG_FORCE_S 31 134 135 #define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x14) 136 /* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 137 /*description: 2-bit attenuation for each pad.*/ 138 #define SENS_SAR1_ATTEN 0xFFFFFFFF 139 #define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) 140 #define SENS_SAR1_ATTEN_V 0xFFFFFFFF 141 #define SENS_SAR1_ATTEN_S 0 142 143 #define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x18) 144 /* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ 145 /*description: .*/ 146 #define SENS_SAR_AMP_WAIT2 0x0000FFFF 147 #define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) 148 #define SENS_SAR_AMP_WAIT2_V 0xFFFF 149 #define SENS_SAR_AMP_WAIT2_S 16 150 /* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ 151 /*description: .*/ 152 #define SENS_SAR_AMP_WAIT1 0x0000FFFF 153 #define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) 154 #define SENS_SAR_AMP_WAIT1_V 0xFFFF 155 #define SENS_SAR_AMP_WAIT1_S 0 156 157 #define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x1C) 158 /* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ 159 /*description: .*/ 160 #define SENS_SAR_AMP_WAIT3 0x0000FFFF 161 #define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) 162 #define SENS_SAR_AMP_WAIT3_V 0xFFFF 163 #define SENS_SAR_AMP_WAIT3_S 16 164 /* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ 165 /*description: .*/ 166 #define SENS_SAR_RSTB_FSM_IDLE (BIT(6)) 167 #define SENS_SAR_RSTB_FSM_IDLE_M (BIT(6)) 168 #define SENS_SAR_RSTB_FSM_IDLE_V 0x1 169 #define SENS_SAR_RSTB_FSM_IDLE_S 6 170 /* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 171 /*description: .*/ 172 #define SENS_XPD_SAR_FSM_IDLE (BIT(5)) 173 #define SENS_XPD_SAR_FSM_IDLE_M (BIT(5)) 174 #define SENS_XPD_SAR_FSM_IDLE_V 0x1 175 #define SENS_XPD_SAR_FSM_IDLE_S 5 176 /* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 177 /*description: .*/ 178 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(4)) 179 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(4)) 180 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 181 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 4 182 /* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 183 /*description: .*/ 184 #define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3)) 185 #define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3)) 186 #define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 187 #define SENS_AMP_SHORT_REF_FSM_IDLE_S 3 188 /* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 189 /*description: .*/ 190 #define SENS_AMP_RST_FB_FSM_IDLE (BIT(2)) 191 #define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(2)) 192 #define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 193 #define SENS_AMP_RST_FB_FSM_IDLE_S 2 194 /* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 195 /*description: .*/ 196 #define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(1)) 197 #define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(1)) 198 #define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 199 #define SENS_XPD_SAR_AMP_FSM_IDLE_S 1 200 /* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 201 /*description: .*/ 202 #define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(0)) 203 #define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(0)) 204 #define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 205 #define SENS_SAR1_DAC_XPD_FSM_IDLE_S 0 206 207 #define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x20) 208 /* SENS_SAR_RSTB_FSM : R/W ;bitpos:[27:24] ;default: 4'b0000 ; */ 209 /*description: .*/ 210 #define SENS_SAR_RSTB_FSM 0x0000000F 211 #define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) 212 #define SENS_SAR_RSTB_FSM_V 0xF 213 #define SENS_SAR_RSTB_FSM_S 24 214 /* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */ 215 /*description: .*/ 216 #define SENS_XPD_SAR_FSM 0x0000000F 217 #define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) 218 #define SENS_XPD_SAR_FSM_V 0xF 219 #define SENS_XPD_SAR_FSM_S 20 220 /* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[19:16] ;default: 4'b0011 ; */ 221 /*description: .*/ 222 #define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F 223 #define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) 224 #define SENS_AMP_SHORT_REF_GND_FSM_V 0xF 225 #define SENS_AMP_SHORT_REF_GND_FSM_S 16 226 /* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ 227 /*description: .*/ 228 #define SENS_AMP_SHORT_REF_FSM 0x0000000F 229 #define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) 230 #define SENS_AMP_SHORT_REF_FSM_V 0xF 231 #define SENS_AMP_SHORT_REF_FSM_S 12 232 /* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[11:8] ;default: 4'b1000 ; */ 233 /*description: .*/ 234 #define SENS_AMP_RST_FB_FSM 0x0000000F 235 #define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) 236 #define SENS_AMP_RST_FB_FSM_V 0xF 237 #define SENS_AMP_RST_FB_FSM_S 8 238 /* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */ 239 /*description: .*/ 240 #define SENS_XPD_SAR_AMP_FSM 0x0000000F 241 #define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) 242 #define SENS_XPD_SAR_AMP_FSM_V 0xF 243 #define SENS_XPD_SAR_AMP_FSM_S 4 244 /* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ 245 /*description: .*/ 246 #define SENS_SAR1_DAC_XPD_FSM 0x0000000F 247 #define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) 248 #define SENS_SAR1_DAC_XPD_FSM_V 0xF 249 #define SENS_SAR1_DAC_XPD_FSM_S 0 250 251 #define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x24) 252 /* SENS_SAR2_INT_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ 253 /*description: enable saradc2 to send out interrupt.*/ 254 #define SENS_SAR2_INT_EN (BIT(30)) 255 #define SENS_SAR2_INT_EN_M (BIT(30)) 256 #define SENS_SAR2_INT_EN_V 0x1 257 #define SENS_SAR2_INT_EN_S 30 258 /* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ 259 /*description: Invert SAR ADC2 data.*/ 260 #define SENS_SAR2_DATA_INV (BIT(29)) 261 #define SENS_SAR2_DATA_INV_M (BIT(29)) 262 #define SENS_SAR2_DATA_INV_V 0x1 263 #define SENS_SAR2_DATA_INV_S 29 264 /* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ 265 /*description: .*/ 266 #define SENS_SAR2_SAMPLE_NUM 0x000000FF 267 #define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S)) 268 #define SENS_SAR2_SAMPLE_NUM_V 0xFF 269 #define SENS_SAR2_SAMPLE_NUM_S 19 270 /* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ 271 /*description: .*/ 272 #define SENS_SAR2_CLK_GATED (BIT(18)) 273 #define SENS_SAR2_CLK_GATED_M (BIT(18)) 274 #define SENS_SAR2_CLK_GATED_V 0x1 275 #define SENS_SAR2_CLK_GATED_S 18 276 /* SENS_SAR2_WAIT_ARB_CYCLE : R/W ;bitpos:[17:16] ;default: 2'b1 ; */ 277 /*description: wait arbit stable after sar_done.*/ 278 #define SENS_SAR2_WAIT_ARB_CYCLE 0x00000003 279 #define SENS_SAR2_WAIT_ARB_CYCLE_M ((SENS_SAR2_WAIT_ARB_CYCLE_V)<<(SENS_SAR2_WAIT_ARB_CYCLE_S)) 280 #define SENS_SAR2_WAIT_ARB_CYCLE_V 0x3 281 #define SENS_SAR2_WAIT_ARB_CYCLE_S 16 282 /* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ 283 /*description: clock divider.*/ 284 #define SENS_SAR2_CLK_DIV 0x000000FF 285 #define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S)) 286 #define SENS_SAR2_CLK_DIV_V 0xFF 287 #define SENS_SAR2_CLK_DIV_S 0 288 289 #define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x28) 290 /* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 291 /*description: .*/ 292 #define SENS_SAR2_READER_STATUS 0xFFFFFFFF 293 #define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) 294 #define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF 295 #define SENS_SAR2_READER_STATUS_S 0 296 297 #define SENS_SAR_MEAS2_CTRL1_REG (DR_REG_SENS_BASE + 0x2C) 298 /* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ 299 /*description: .*/ 300 #define SENS_SAR2_XPD_WAIT 0x000000FF 301 #define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) 302 #define SENS_SAR2_XPD_WAIT_V 0xFF 303 #define SENS_SAR2_XPD_WAIT_S 24 304 /* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[23:16] ;default: 8'd2 ; */ 305 /*description: .*/ 306 #define SENS_SAR2_RSTB_WAIT 0x000000FF 307 #define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) 308 #define SENS_SAR2_RSTB_WAIT_V 0xFF 309 #define SENS_SAR2_RSTB_WAIT_S 16 310 /* SENS_SAR2_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd2 ; */ 311 /*description: .*/ 312 #define SENS_SAR2_STANDBY_WAIT 0x000000FF 313 #define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V)<<(SENS_SAR2_STANDBY_WAIT_S)) 314 #define SENS_SAR2_STANDBY_WAIT_V 0xFF 315 #define SENS_SAR2_STANDBY_WAIT_S 8 316 /* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ 317 /*description: .*/ 318 #define SENS_SAR2_RSTB_FORCE 0x00000003 319 #define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) 320 #define SENS_SAR2_RSTB_FORCE_V 0x3 321 #define SENS_SAR2_RSTB_FORCE_S 6 322 /* SENS_SAR2_EN_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 323 /*description: SAR2_EN_TEST.*/ 324 #define SENS_SAR2_EN_TEST (BIT(5)) 325 #define SENS_SAR2_EN_TEST_M (BIT(5)) 326 #define SENS_SAR2_EN_TEST_V 0x1 327 #define SENS_SAR2_EN_TEST_S 5 328 /* SENS_SAR2_PKDET_CAL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 329 /*description: rtc control pkdet enable.*/ 330 #define SENS_SAR2_PKDET_CAL_EN (BIT(4)) 331 #define SENS_SAR2_PKDET_CAL_EN_M (BIT(4)) 332 #define SENS_SAR2_PKDET_CAL_EN_V 0x1 333 #define SENS_SAR2_PKDET_CAL_EN_S 4 334 /* SENS_SAR2_PWDET_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 335 /*description: rtc control pwdet enable.*/ 336 #define SENS_SAR2_PWDET_CAL_EN (BIT(3)) 337 #define SENS_SAR2_PWDET_CAL_EN_M (BIT(3)) 338 #define SENS_SAR2_PWDET_CAL_EN_V 0x1 339 #define SENS_SAR2_PWDET_CAL_EN_S 3 340 /* SENS_SAR2_CNTL_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 341 /*description: saradc2_cntl_fsm.*/ 342 #define SENS_SAR2_CNTL_STATE 0x00000007 343 #define SENS_SAR2_CNTL_STATE_M ((SENS_SAR2_CNTL_STATE_V)<<(SENS_SAR2_CNTL_STATE_S)) 344 #define SENS_SAR2_CNTL_STATE_V 0x7 345 #define SENS_SAR2_CNTL_STATE_S 0 346 347 #define SENS_SAR_MEAS2_CTRL2_REG (DR_REG_SENS_BASE + 0x30) 348 /* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 349 /*description: 1: SAR ADC2 pad enable bitmap is controlled by SW.*/ 350 #define SENS_SAR2_EN_PAD_FORCE (BIT(31)) 351 #define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) 352 #define SENS_SAR2_EN_PAD_FORCE_V 0x1 353 #define SENS_SAR2_EN_PAD_FORCE_S 31 354 /* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ 355 /*description: SAR ADC2 pad enable bitmap.*/ 356 #define SENS_SAR2_EN_PAD 0x00000FFF 357 #define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S)) 358 #define SENS_SAR2_EN_PAD_V 0xFFF 359 #define SENS_SAR2_EN_PAD_S 19 360 /* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ 361 /*description: 1: SAR ADC2 controller (in RTC) is started by SW.*/ 362 #define SENS_MEAS2_START_FORCE (BIT(18)) 363 #define SENS_MEAS2_START_FORCE_M (BIT(18)) 364 #define SENS_MEAS2_START_FORCE_V 0x1 365 #define SENS_MEAS2_START_FORCE_S 18 366 /* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 367 /*description: SAR ADC2 controller (in RTC) starts conversion.*/ 368 #define SENS_MEAS2_START_SAR (BIT(17)) 369 #define SENS_MEAS2_START_SAR_M (BIT(17)) 370 #define SENS_MEAS2_START_SAR_V 0x1 371 #define SENS_MEAS2_START_SAR_S 17 372 /* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ 373 /*description: SAR ADC2 conversion done indication.*/ 374 #define SENS_MEAS2_DONE_SAR (BIT(16)) 375 #define SENS_MEAS2_DONE_SAR_M (BIT(16)) 376 #define SENS_MEAS2_DONE_SAR_V 0x1 377 #define SENS_MEAS2_DONE_SAR_S 16 378 /* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ 379 /*description: SAR ADC2 data.*/ 380 #define SENS_MEAS2_DATA_SAR 0x0000FFFF 381 #define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S)) 382 #define SENS_MEAS2_DATA_SAR_V 0xFFFF 383 #define SENS_MEAS2_DATA_SAR_S 0 384 385 #define SENS_SAR_MEAS2_MUX_REG (DR_REG_SENS_BASE + 0x34) 386 /* SENS_SAR2_RTC_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 387 /*description: in sleep, force to use rtc to control ADC.*/ 388 #define SENS_SAR2_RTC_FORCE (BIT(31)) 389 #define SENS_SAR2_RTC_FORCE_M (BIT(31)) 390 #define SENS_SAR2_RTC_FORCE_V 0x1 391 #define SENS_SAR2_RTC_FORCE_S 31 392 /* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ 393 /*description: SAR2_PWDET_CCT.*/ 394 #define SENS_SAR2_PWDET_CCT 0x00000007 395 #define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) 396 #define SENS_SAR2_PWDET_CCT_V 0x7 397 #define SENS_SAR2_PWDET_CCT_S 28 398 399 #define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x38) 400 /* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 401 /*description: 2-bit attenuation for each pad.*/ 402 #define SENS_SAR2_ATTEN 0xFFFFFFFF 403 #define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) 404 #define SENS_SAR2_ATTEN_V 0xFFFFFFFF 405 #define SENS_SAR2_ATTEN_S 0 406 407 #define SENS_SAR_POWER_XPD_SAR_REG (DR_REG_SENS_BASE + 0x3C) 408 /* SENS_SARCLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 409 /*description: .*/ 410 #define SENS_SARCLK_EN (BIT(31)) 411 #define SENS_SARCLK_EN_M (BIT(31)) 412 #define SENS_SARCLK_EN_V 0x1 413 #define SENS_SARCLK_EN_S 31 414 /* SENS_FORCE_XPD_SAR : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ 415 /*description: .*/ 416 #define SENS_FORCE_XPD_SAR 0x00000003 417 #define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) 418 #define SENS_FORCE_XPD_SAR_V 0x3 419 #define SENS_FORCE_XPD_SAR_S 29 420 421 #define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x40) 422 /* SENS_SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ 423 /*description: .*/ 424 #define SENS_SARADC_MEAS_STATUS 0x000000FF 425 #define SENS_SARADC_MEAS_STATUS_M ((SENS_SARADC_MEAS_STATUS_V)<<(SENS_SARADC_MEAS_STATUS_S)) 426 #define SENS_SARADC_MEAS_STATUS_V 0xFF 427 #define SENS_SARADC_MEAS_STATUS_S 22 428 /* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 429 /*description: .*/ 430 #define SENS_I2C_SLAVE_ADDR0 0x000007FF 431 #define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) 432 #define SENS_I2C_SLAVE_ADDR0_V 0x7FF 433 #define SENS_I2C_SLAVE_ADDR0_S 11 434 /* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 435 /*description: .*/ 436 #define SENS_I2C_SLAVE_ADDR1 0x000007FF 437 #define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) 438 #define SENS_I2C_SLAVE_ADDR1_V 0x7FF 439 #define SENS_I2C_SLAVE_ADDR1_S 0 440 441 #define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x44) 442 /* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 443 /*description: .*/ 444 #define SENS_I2C_SLAVE_ADDR2 0x000007FF 445 #define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) 446 #define SENS_I2C_SLAVE_ADDR2_V 0x7FF 447 #define SENS_I2C_SLAVE_ADDR2_S 11 448 /* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 449 /*description: .*/ 450 #define SENS_I2C_SLAVE_ADDR3 0x000007FF 451 #define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) 452 #define SENS_I2C_SLAVE_ADDR3_V 0x7FF 453 #define SENS_I2C_SLAVE_ADDR3_S 0 454 455 #define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x48) 456 /* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 457 /*description: .*/ 458 #define SENS_I2C_SLAVE_ADDR4 0x000007FF 459 #define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) 460 #define SENS_I2C_SLAVE_ADDR4_V 0x7FF 461 #define SENS_I2C_SLAVE_ADDR4_S 11 462 /* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 463 /*description: .*/ 464 #define SENS_I2C_SLAVE_ADDR5 0x000007FF 465 #define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) 466 #define SENS_I2C_SLAVE_ADDR5_V 0x7FF 467 #define SENS_I2C_SLAVE_ADDR5_S 0 468 469 #define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x4C) 470 /* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 471 /*description: .*/ 472 #define SENS_I2C_SLAVE_ADDR6 0x000007FF 473 #define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) 474 #define SENS_I2C_SLAVE_ADDR6_V 0x7FF 475 #define SENS_I2C_SLAVE_ADDR6_S 11 476 /* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 477 /*description: .*/ 478 #define SENS_I2C_SLAVE_ADDR7 0x000007FF 479 #define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) 480 #define SENS_I2C_SLAVE_ADDR7_V 0x7FF 481 #define SENS_I2C_SLAVE_ADDR7_S 0 482 483 #define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x50) 484 /* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */ 485 /*description: temperature sensor dump out.*/ 486 #define SENS_TSENS_DUMP_OUT (BIT(24)) 487 #define SENS_TSENS_DUMP_OUT_M (BIT(24)) 488 #define SENS_TSENS_DUMP_OUT_V 0x1 489 #define SENS_TSENS_DUMP_OUT_S 24 490 /* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 491 /*description: 1: dump out & power up controlled by SW.*/ 492 #define SENS_TSENS_POWER_UP_FORCE (BIT(23)) 493 #define SENS_TSENS_POWER_UP_FORCE_M (BIT(23)) 494 #define SENS_TSENS_POWER_UP_FORCE_V 0x1 495 #define SENS_TSENS_POWER_UP_FORCE_S 23 496 /* SENS_TSENS_POWER_UP : R/W ;bitpos:[22] ;default: 1'b0 ; */ 497 /*description: temperature sensor power up.*/ 498 #define SENS_TSENS_POWER_UP (BIT(22)) 499 #define SENS_TSENS_POWER_UP_M (BIT(22)) 500 #define SENS_TSENS_POWER_UP_V 0x1 501 #define SENS_TSENS_POWER_UP_S 22 502 /* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ 503 /*description: temperature sensor clock divider.*/ 504 #define SENS_TSENS_CLK_DIV 0x000000FF 505 #define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) 506 #define SENS_TSENS_CLK_DIV_V 0xFF 507 #define SENS_TSENS_CLK_DIV_S 14 508 /* SENS_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ 509 /*description: invert temperature sensor data.*/ 510 #define SENS_TSENS_IN_INV (BIT(13)) 511 #define SENS_TSENS_IN_INV_M (BIT(13)) 512 #define SENS_TSENS_IN_INV_V 0x1 513 #define SENS_TSENS_IN_INV_S 13 514 /* SENS_TSENS_INT_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ 515 /*description: enable temperature sensor to send out interrupt.*/ 516 #define SENS_TSENS_INT_EN (BIT(12)) 517 #define SENS_TSENS_INT_EN_M (BIT(12)) 518 #define SENS_TSENS_INT_EN_V 0x1 519 #define SENS_TSENS_INT_EN_S 12 520 /* SENS_TSENS_READY : RO ;bitpos:[8] ;default: 1'h0 ; */ 521 /*description: indicate temperature sensor out ready.*/ 522 #define SENS_TSENS_READY (BIT(8)) 523 #define SENS_TSENS_READY_M (BIT(8)) 524 #define SENS_TSENS_READY_V 0x1 525 #define SENS_TSENS_READY_S 8 526 /* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ 527 /*description: temperature sensor data out.*/ 528 #define SENS_TSENS_OUT 0x000000FF 529 #define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) 530 #define SENS_TSENS_OUT_V 0xFF 531 #define SENS_TSENS_OUT_S 0 532 533 #define SENS_SAR_TSENS_CTRL2_REG (DR_REG_SENS_BASE + 0x54) 534 /* SENS_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ 535 /*description: .*/ 536 #define SENS_TSENS_CLK_INV (BIT(14)) 537 #define SENS_TSENS_CLK_INV_M (BIT(14)) 538 #define SENS_TSENS_CLK_INV_V 0x1 539 #define SENS_TSENS_CLK_INV_S 14 540 /* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ 541 /*description: .*/ 542 #define SENS_TSENS_XPD_FORCE 0x00000003 543 #define SENS_TSENS_XPD_FORCE_M ((SENS_TSENS_XPD_FORCE_V)<<(SENS_TSENS_XPD_FORCE_S)) 544 #define SENS_TSENS_XPD_FORCE_V 0x3 545 #define SENS_TSENS_XPD_FORCE_S 12 546 /* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ 547 /*description: .*/ 548 #define SENS_TSENS_XPD_WAIT 0x00000FFF 549 #define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) 550 #define SENS_TSENS_XPD_WAIT_V 0xFFF 551 #define SENS_TSENS_XPD_WAIT_S 0 552 553 #define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x58) 554 /* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ 555 /*description: 1: I2C started by SW.*/ 556 #define SENS_SAR_I2C_START_FORCE (BIT(29)) 557 #define SENS_SAR_I2C_START_FORCE_M (BIT(29)) 558 #define SENS_SAR_I2C_START_FORCE_V 0x1 559 #define SENS_SAR_I2C_START_FORCE_S 29 560 /* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ 561 /*description: start I2C.*/ 562 #define SENS_SAR_I2C_START (BIT(28)) 563 #define SENS_SAR_I2C_START_M (BIT(28)) 564 #define SENS_SAR_I2C_START_V 0x1 565 #define SENS_SAR_I2C_START_S 28 566 /* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ 567 /*description: I2C control data.*/ 568 #define SENS_SAR_I2C_CTRL 0x0FFFFFFF 569 #define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) 570 #define SENS_SAR_I2C_CTRL_V 0xFFFFFFF 571 #define SENS_SAR_I2C_CTRL_S 0 572 573 #define SENS_SAR_TOUCH_CONF_REG (DR_REG_SENS_BASE + 0x5C) 574 /* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hf ; */ 575 /*description: indicate which pad is approach pad0.*/ 576 #define SENS_TOUCH_APPROACH_PAD0 0x0000000F 577 #define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V)<<(SENS_TOUCH_APPROACH_PAD0_S)) 578 #define SENS_TOUCH_APPROACH_PAD0_V 0xF 579 #define SENS_TOUCH_APPROACH_PAD0_S 28 580 /* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hf ; */ 581 /*description: indicate which pad is approach pad1.*/ 582 #define SENS_TOUCH_APPROACH_PAD1 0x0000000F 583 #define SENS_TOUCH_APPROACH_PAD1_M ((SENS_TOUCH_APPROACH_PAD1_V)<<(SENS_TOUCH_APPROACH_PAD1_S)) 584 #define SENS_TOUCH_APPROACH_PAD1_V 0xF 585 #define SENS_TOUCH_APPROACH_PAD1_S 24 586 /* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hf ; */ 587 /*description: indicate which pad is approach pad2.*/ 588 #define SENS_TOUCH_APPROACH_PAD2 0x0000000F 589 #define SENS_TOUCH_APPROACH_PAD2_M ((SENS_TOUCH_APPROACH_PAD2_V)<<(SENS_TOUCH_APPROACH_PAD2_S)) 590 #define SENS_TOUCH_APPROACH_PAD2_V 0xF 591 #define SENS_TOUCH_APPROACH_PAD2_S 20 592 /* SENS_TOUCH_UNIT_END : RO ;bitpos:[19] ;default: 1'd0 ; */ 593 /*description: touch_unit_done.*/ 594 #define SENS_TOUCH_UNIT_END (BIT(19)) 595 #define SENS_TOUCH_UNIT_END_M (BIT(19)) 596 #define SENS_TOUCH_UNIT_END_V 0x1 597 #define SENS_TOUCH_UNIT_END_S 19 598 /* SENS_TOUCH_DENOISE_END : RO ;bitpos:[18] ;default: 1'd0 ; */ 599 /*description: touch_denoise_done.*/ 600 #define SENS_TOUCH_DENOISE_END (BIT(18)) 601 #define SENS_TOUCH_DENOISE_END_M (BIT(18)) 602 #define SENS_TOUCH_DENOISE_END_V 0x1 603 #define SENS_TOUCH_DENOISE_END_S 18 604 /* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ 605 /*description: 3: smooth data 2: baseline 1,0: raw_data.*/ 606 #define SENS_TOUCH_DATA_SEL 0x00000003 607 #define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V)<<(SENS_TOUCH_DATA_SEL_S)) 608 #define SENS_TOUCH_DATA_SEL_V 0x3 609 #define SENS_TOUCH_DATA_SEL_S 16 610 /* SENS_TOUCH_STATUS_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ 611 /*description: clear all touch active status.*/ 612 #define SENS_TOUCH_STATUS_CLR (BIT(15)) 613 #define SENS_TOUCH_STATUS_CLR_M (BIT(15)) 614 #define SENS_TOUCH_STATUS_CLR_V 0x1 615 #define SENS_TOUCH_STATUS_CLR_S 15 616 /* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7fff ; */ 617 /*description: touch controller output enable.*/ 618 #define SENS_TOUCH_OUTEN 0x00007FFF 619 #define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V)<<(SENS_TOUCH_OUTEN_S)) 620 #define SENS_TOUCH_OUTEN_V 0x7FFF 621 #define SENS_TOUCH_OUTEN_S 0 622 623 #define SENS_SAR_TOUCH_DENOISE_REG (DR_REG_SENS_BASE + 0x60) 624 /* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'b0 ; */ 625 /*description: .*/ 626 #define SENS_TOUCH_DENOISE_DATA 0x003FFFFF 627 #define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S)) 628 #define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF 629 #define SENS_TOUCH_DENOISE_DATA_S 0 630 631 #define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x64) 632 /* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 633 /*description: Finger threshold for touch pad 1.*/ 634 #define SENS_TOUCH_OUT_TH1 0x003FFFFF 635 #define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) 636 #define SENS_TOUCH_OUT_TH1_V 0x3FFFFF 637 #define SENS_TOUCH_OUT_TH1_S 0 638 639 #define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x68) 640 /* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 641 /*description: Finger threshold for touch pad 2.*/ 642 #define SENS_TOUCH_OUT_TH2 0x003FFFFF 643 #define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) 644 #define SENS_TOUCH_OUT_TH2_V 0x3FFFFF 645 #define SENS_TOUCH_OUT_TH2_S 0 646 647 #define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x6C) 648 /* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 649 /*description: Finger threshold for touch pad 3.*/ 650 #define SENS_TOUCH_OUT_TH3 0x003FFFFF 651 #define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) 652 #define SENS_TOUCH_OUT_TH3_V 0x3FFFFF 653 #define SENS_TOUCH_OUT_TH3_S 0 654 655 #define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x70) 656 /* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 657 /*description: Finger threshold for touch pad 4.*/ 658 #define SENS_TOUCH_OUT_TH4 0x003FFFFF 659 #define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) 660 #define SENS_TOUCH_OUT_TH4_V 0x3FFFFF 661 #define SENS_TOUCH_OUT_TH4_S 0 662 663 #define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x74) 664 /* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 665 /*description: Finger threshold for touch pad 5.*/ 666 #define SENS_TOUCH_OUT_TH5 0x003FFFFF 667 #define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) 668 #define SENS_TOUCH_OUT_TH5_V 0x3FFFFF 669 #define SENS_TOUCH_OUT_TH5_S 0 670 671 #define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x78) 672 /* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 673 /*description: Finger threshold for touch pad 6.*/ 674 #define SENS_TOUCH_OUT_TH6 0x003FFFFF 675 #define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) 676 #define SENS_TOUCH_OUT_TH6_V 0x3FFFFF 677 #define SENS_TOUCH_OUT_TH6_S 0 678 679 #define SENS_SAR_TOUCH_THRES7_REG (DR_REG_SENS_BASE + 0x7C) 680 /* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 681 /*description: Finger threshold for touch pad 7.*/ 682 #define SENS_TOUCH_OUT_TH7 0x003FFFFF 683 #define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) 684 #define SENS_TOUCH_OUT_TH7_V 0x3FFFFF 685 #define SENS_TOUCH_OUT_TH7_S 0 686 687 #define SENS_SAR_TOUCH_THRES8_REG (DR_REG_SENS_BASE + 0x80) 688 /* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 689 /*description: Finger threshold for touch pad 8.*/ 690 #define SENS_TOUCH_OUT_TH8 0x003FFFFF 691 #define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) 692 #define SENS_TOUCH_OUT_TH8_V 0x3FFFFF 693 #define SENS_TOUCH_OUT_TH8_S 0 694 695 #define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x84) 696 /* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 697 /*description: Finger threshold for touch pad 9.*/ 698 #define SENS_TOUCH_OUT_TH9 0x003FFFFF 699 #define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) 700 #define SENS_TOUCH_OUT_TH9_V 0x3FFFFF 701 #define SENS_TOUCH_OUT_TH9_S 0 702 703 #define SENS_SAR_TOUCH_THRES10_REG (DR_REG_SENS_BASE + 0x88) 704 /* SENS_TOUCH_OUT_TH10 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 705 /*description: Finger threshold for touch pad 10.*/ 706 #define SENS_TOUCH_OUT_TH10 0x003FFFFF 707 #define SENS_TOUCH_OUT_TH10_M ((SENS_TOUCH_OUT_TH10_V)<<(SENS_TOUCH_OUT_TH10_S)) 708 #define SENS_TOUCH_OUT_TH10_V 0x3FFFFF 709 #define SENS_TOUCH_OUT_TH10_S 0 710 711 #define SENS_SAR_TOUCH_THRES11_REG (DR_REG_SENS_BASE + 0x8C) 712 /* SENS_TOUCH_OUT_TH11 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 713 /*description: Finger threshold for touch pad 11.*/ 714 #define SENS_TOUCH_OUT_TH11 0x003FFFFF 715 #define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V)<<(SENS_TOUCH_OUT_TH11_S)) 716 #define SENS_TOUCH_OUT_TH11_V 0x3FFFFF 717 #define SENS_TOUCH_OUT_TH11_S 0 718 719 #define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x90) 720 /* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 721 /*description: Finger threshold for touch pad 12.*/ 722 #define SENS_TOUCH_OUT_TH12 0x003FFFFF 723 #define SENS_TOUCH_OUT_TH12_M ((SENS_TOUCH_OUT_TH12_V)<<(SENS_TOUCH_OUT_TH12_S)) 724 #define SENS_TOUCH_OUT_TH12_V 0x3FFFFF 725 #define SENS_TOUCH_OUT_TH12_S 0 726 727 #define SENS_SAR_TOUCH_THRES13_REG (DR_REG_SENS_BASE + 0x94) 728 /* SENS_TOUCH_OUT_TH13 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 729 /*description: Finger threshold for touch pad 13.*/ 730 #define SENS_TOUCH_OUT_TH13 0x003FFFFF 731 #define SENS_TOUCH_OUT_TH13_M ((SENS_TOUCH_OUT_TH13_V)<<(SENS_TOUCH_OUT_TH13_S)) 732 #define SENS_TOUCH_OUT_TH13_V 0x3FFFFF 733 #define SENS_TOUCH_OUT_TH13_S 0 734 735 #define SENS_SAR_TOUCH_THRES14_REG (DR_REG_SENS_BASE + 0x98) 736 /* SENS_TOUCH_OUT_TH14 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 737 /*description: Finger threshold for touch pad 14.*/ 738 #define SENS_TOUCH_OUT_TH14 0x003FFFFF 739 #define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V)<<(SENS_TOUCH_OUT_TH14_S)) 740 #define SENS_TOUCH_OUT_TH14_V 0x3FFFFF 741 #define SENS_TOUCH_OUT_TH14_S 0 742 743 #define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x9C) 744 /* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ 745 /*description: .*/ 746 #define SENS_TOUCH_MEAS_DONE (BIT(31)) 747 #define SENS_TOUCH_MEAS_DONE_M (BIT(31)) 748 #define SENS_TOUCH_MEAS_DONE_V 0x1 749 #define SENS_TOUCH_MEAS_DONE_S 31 750 /* SENS_TOUCH_CHANNEL_CLR : WO ;bitpos:[29:15] ;default: 15'd0 ; */ 751 /*description: Clear touch channel.*/ 752 #define SENS_TOUCH_CHANNEL_CLR 0x00007FFF 753 #define SENS_TOUCH_CHANNEL_CLR_M ((SENS_TOUCH_CHANNEL_CLR_V)<<(SENS_TOUCH_CHANNEL_CLR_S)) 754 #define SENS_TOUCH_CHANNEL_CLR_V 0x7FFF 755 #define SENS_TOUCH_CHANNEL_CLR_S 15 756 /* SENS_TOUCH_PAD_ACTIVE : RO ;bitpos:[14:0] ;default: 15'd0 ; */ 757 /*description: touch active status.*/ 758 #define SENS_TOUCH_PAD_ACTIVE 0x00007FFF 759 #define SENS_TOUCH_PAD_ACTIVE_M ((SENS_TOUCH_PAD_ACTIVE_V)<<(SENS_TOUCH_PAD_ACTIVE_S)) 760 #define SENS_TOUCH_PAD_ACTIVE_V 0x7FFF 761 #define SENS_TOUCH_PAD_ACTIVE_S 0 762 763 #define SENS_SAR_TOUCH_STATUS0_REG (DR_REG_SENS_BASE + 0xA0) 764 /* SENS_TOUCH_SCAN_CURR : RO ;bitpos:[25:22] ;default: 4'd0 ; */ 765 /*description: .*/ 766 #define SENS_TOUCH_SCAN_CURR 0x0000000F 767 #define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V)<<(SENS_TOUCH_SCAN_CURR_S)) 768 #define SENS_TOUCH_SCAN_CURR_V 0xF 769 #define SENS_TOUCH_SCAN_CURR_S 22 770 /* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 771 /*description: the counter for touch pad 0.*/ 772 #define SENS_TOUCH_DENOISE_DATA 0x003FFFFF 773 #define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S)) 774 #define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF 775 #define SENS_TOUCH_DENOISE_DATA_S 0 776 777 #define SENS_SAR_TOUCH_STATUS1_REG (DR_REG_SENS_BASE + 0xA4) 778 /* SENS_TOUCH_PAD1_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 779 /*description: .*/ 780 #define SENS_TOUCH_PAD1_DEBOUNCE 0x00000007 781 #define SENS_TOUCH_PAD1_DEBOUNCE_M ((SENS_TOUCH_PAD1_DEBOUNCE_V)<<(SENS_TOUCH_PAD1_DEBOUNCE_S)) 782 #define SENS_TOUCH_PAD1_DEBOUNCE_V 0x7 783 #define SENS_TOUCH_PAD1_DEBOUNCE_S 29 784 /* SENS_TOUCH_PAD1_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 785 /*description: .*/ 786 #define SENS_TOUCH_PAD1_DATA 0x003FFFFF 787 #define SENS_TOUCH_PAD1_DATA_M ((SENS_TOUCH_PAD1_DATA_V)<<(SENS_TOUCH_PAD1_DATA_S)) 788 #define SENS_TOUCH_PAD1_DATA_V 0x3FFFFF 789 #define SENS_TOUCH_PAD1_DATA_S 0 790 791 #define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0xA8) 792 /* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 793 /*description: .*/ 794 #define SENS_TOUCH_PAD2_DEBOUNCE 0x00000007 795 #define SENS_TOUCH_PAD2_DEBOUNCE_M ((SENS_TOUCH_PAD2_DEBOUNCE_V)<<(SENS_TOUCH_PAD2_DEBOUNCE_S)) 796 #define SENS_TOUCH_PAD2_DEBOUNCE_V 0x7 797 #define SENS_TOUCH_PAD2_DEBOUNCE_S 29 798 /* SENS_TOUCH_PAD2_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 799 /*description: .*/ 800 #define SENS_TOUCH_PAD2_DATA 0x003FFFFF 801 #define SENS_TOUCH_PAD2_DATA_M ((SENS_TOUCH_PAD2_DATA_V)<<(SENS_TOUCH_PAD2_DATA_S)) 802 #define SENS_TOUCH_PAD2_DATA_V 0x3FFFFF 803 #define SENS_TOUCH_PAD2_DATA_S 0 804 805 #define SENS_SAR_TOUCH_STATUS3_REG (DR_REG_SENS_BASE + 0xAC) 806 /* SENS_TOUCH_PAD3_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 807 /*description: .*/ 808 #define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007 809 #define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V)<<(SENS_TOUCH_PAD3_DEBOUNCE_S)) 810 #define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7 811 #define SENS_TOUCH_PAD3_DEBOUNCE_S 29 812 /* SENS_TOUCH_PAD3_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 813 /*description: .*/ 814 #define SENS_TOUCH_PAD3_DATA 0x003FFFFF 815 #define SENS_TOUCH_PAD3_DATA_M ((SENS_TOUCH_PAD3_DATA_V)<<(SENS_TOUCH_PAD3_DATA_S)) 816 #define SENS_TOUCH_PAD3_DATA_V 0x3FFFFF 817 #define SENS_TOUCH_PAD3_DATA_S 0 818 819 #define SENS_SAR_TOUCH_STATUS4_REG (DR_REG_SENS_BASE + 0xB0) 820 /* SENS_TOUCH_PAD4_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 821 /*description: .*/ 822 #define SENS_TOUCH_PAD4_DEBOUNCE 0x00000007 823 #define SENS_TOUCH_PAD4_DEBOUNCE_M ((SENS_TOUCH_PAD4_DEBOUNCE_V)<<(SENS_TOUCH_PAD4_DEBOUNCE_S)) 824 #define SENS_TOUCH_PAD4_DEBOUNCE_V 0x7 825 #define SENS_TOUCH_PAD4_DEBOUNCE_S 29 826 /* SENS_TOUCH_PAD4_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 827 /*description: .*/ 828 #define SENS_TOUCH_PAD4_DATA 0x003FFFFF 829 #define SENS_TOUCH_PAD4_DATA_M ((SENS_TOUCH_PAD4_DATA_V)<<(SENS_TOUCH_PAD4_DATA_S)) 830 #define SENS_TOUCH_PAD4_DATA_V 0x3FFFFF 831 #define SENS_TOUCH_PAD4_DATA_S 0 832 833 #define SENS_SAR_TOUCH_STATUS5_REG (DR_REG_SENS_BASE + 0xB4) 834 /* SENS_TOUCH_PAD5_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 835 /*description: .*/ 836 #define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007 837 #define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V)<<(SENS_TOUCH_PAD5_DEBOUNCE_S)) 838 #define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7 839 #define SENS_TOUCH_PAD5_DEBOUNCE_S 29 840 /* SENS_TOUCH_PAD5_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 841 /*description: .*/ 842 #define SENS_TOUCH_PAD5_DATA 0x003FFFFF 843 #define SENS_TOUCH_PAD5_DATA_M ((SENS_TOUCH_PAD5_DATA_V)<<(SENS_TOUCH_PAD5_DATA_S)) 844 #define SENS_TOUCH_PAD5_DATA_V 0x3FFFFF 845 #define SENS_TOUCH_PAD5_DATA_S 0 846 847 #define SENS_SAR_TOUCH_STATUS6_REG (DR_REG_SENS_BASE + 0xB8) 848 /* SENS_TOUCH_PAD6_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 849 /*description: .*/ 850 #define SENS_TOUCH_PAD6_DEBOUNCE 0x00000007 851 #define SENS_TOUCH_PAD6_DEBOUNCE_M ((SENS_TOUCH_PAD6_DEBOUNCE_V)<<(SENS_TOUCH_PAD6_DEBOUNCE_S)) 852 #define SENS_TOUCH_PAD6_DEBOUNCE_V 0x7 853 #define SENS_TOUCH_PAD6_DEBOUNCE_S 29 854 /* SENS_TOUCH_PAD6_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 855 /*description: .*/ 856 #define SENS_TOUCH_PAD6_DATA 0x003FFFFF 857 #define SENS_TOUCH_PAD6_DATA_M ((SENS_TOUCH_PAD6_DATA_V)<<(SENS_TOUCH_PAD6_DATA_S)) 858 #define SENS_TOUCH_PAD6_DATA_V 0x3FFFFF 859 #define SENS_TOUCH_PAD6_DATA_S 0 860 861 #define SENS_SAR_TOUCH_STATUS7_REG (DR_REG_SENS_BASE + 0xBC) 862 /* SENS_TOUCH_PAD7_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 863 /*description: .*/ 864 #define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007 865 #define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V)<<(SENS_TOUCH_PAD7_DEBOUNCE_S)) 866 #define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7 867 #define SENS_TOUCH_PAD7_DEBOUNCE_S 29 868 /* SENS_TOUCH_PAD7_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 869 /*description: .*/ 870 #define SENS_TOUCH_PAD7_DATA 0x003FFFFF 871 #define SENS_TOUCH_PAD7_DATA_M ((SENS_TOUCH_PAD7_DATA_V)<<(SENS_TOUCH_PAD7_DATA_S)) 872 #define SENS_TOUCH_PAD7_DATA_V 0x3FFFFF 873 #define SENS_TOUCH_PAD7_DATA_S 0 874 875 #define SENS_SAR_TOUCH_STATUS8_REG (DR_REG_SENS_BASE + 0xC0) 876 /* SENS_TOUCH_PAD8_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 877 /*description: .*/ 878 #define SENS_TOUCH_PAD8_DEBOUNCE 0x00000007 879 #define SENS_TOUCH_PAD8_DEBOUNCE_M ((SENS_TOUCH_PAD8_DEBOUNCE_V)<<(SENS_TOUCH_PAD8_DEBOUNCE_S)) 880 #define SENS_TOUCH_PAD8_DEBOUNCE_V 0x7 881 #define SENS_TOUCH_PAD8_DEBOUNCE_S 29 882 /* SENS_TOUCH_PAD8_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 883 /*description: .*/ 884 #define SENS_TOUCH_PAD8_DATA 0x003FFFFF 885 #define SENS_TOUCH_PAD8_DATA_M ((SENS_TOUCH_PAD8_DATA_V)<<(SENS_TOUCH_PAD8_DATA_S)) 886 #define SENS_TOUCH_PAD8_DATA_V 0x3FFFFF 887 #define SENS_TOUCH_PAD8_DATA_S 0 888 889 #define SENS_SAR_TOUCH_STATUS9_REG (DR_REG_SENS_BASE + 0xC4) 890 /* SENS_TOUCH_PAD9_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 891 /*description: .*/ 892 #define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007 893 #define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V)<<(SENS_TOUCH_PAD9_DEBOUNCE_S)) 894 #define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7 895 #define SENS_TOUCH_PAD9_DEBOUNCE_S 29 896 /* SENS_TOUCH_PAD9_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 897 /*description: .*/ 898 #define SENS_TOUCH_PAD9_DATA 0x003FFFFF 899 #define SENS_TOUCH_PAD9_DATA_M ((SENS_TOUCH_PAD9_DATA_V)<<(SENS_TOUCH_PAD9_DATA_S)) 900 #define SENS_TOUCH_PAD9_DATA_V 0x3FFFFF 901 #define SENS_TOUCH_PAD9_DATA_S 0 902 903 #define SENS_SAR_TOUCH_STATUS10_REG (DR_REG_SENS_BASE + 0xC8) 904 /* SENS_TOUCH_PAD10_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 905 /*description: .*/ 906 #define SENS_TOUCH_PAD10_DEBOUNCE 0x00000007 907 #define SENS_TOUCH_PAD10_DEBOUNCE_M ((SENS_TOUCH_PAD10_DEBOUNCE_V)<<(SENS_TOUCH_PAD10_DEBOUNCE_S)) 908 #define SENS_TOUCH_PAD10_DEBOUNCE_V 0x7 909 #define SENS_TOUCH_PAD10_DEBOUNCE_S 29 910 /* SENS_TOUCH_PAD10_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 911 /*description: .*/ 912 #define SENS_TOUCH_PAD10_DATA 0x003FFFFF 913 #define SENS_TOUCH_PAD10_DATA_M ((SENS_TOUCH_PAD10_DATA_V)<<(SENS_TOUCH_PAD10_DATA_S)) 914 #define SENS_TOUCH_PAD10_DATA_V 0x3FFFFF 915 #define SENS_TOUCH_PAD10_DATA_S 0 916 917 #define SENS_SAR_TOUCH_STATUS11_REG (DR_REG_SENS_BASE + 0xCC) 918 /* SENS_TOUCH_PAD11_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 919 /*description: .*/ 920 #define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007 921 #define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V)<<(SENS_TOUCH_PAD11_DEBOUNCE_S)) 922 #define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7 923 #define SENS_TOUCH_PAD11_DEBOUNCE_S 29 924 /* SENS_TOUCH_PAD11_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 925 /*description: .*/ 926 #define SENS_TOUCH_PAD11_DATA 0x003FFFFF 927 #define SENS_TOUCH_PAD11_DATA_M ((SENS_TOUCH_PAD11_DATA_V)<<(SENS_TOUCH_PAD11_DATA_S)) 928 #define SENS_TOUCH_PAD11_DATA_V 0x3FFFFF 929 #define SENS_TOUCH_PAD11_DATA_S 0 930 931 #define SENS_SAR_TOUCH_STATUS12_REG (DR_REG_SENS_BASE + 0xD0) 932 /* SENS_TOUCH_PAD12_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 933 /*description: .*/ 934 #define SENS_TOUCH_PAD12_DEBOUNCE 0x00000007 935 #define SENS_TOUCH_PAD12_DEBOUNCE_M ((SENS_TOUCH_PAD12_DEBOUNCE_V)<<(SENS_TOUCH_PAD12_DEBOUNCE_S)) 936 #define SENS_TOUCH_PAD12_DEBOUNCE_V 0x7 937 #define SENS_TOUCH_PAD12_DEBOUNCE_S 29 938 /* SENS_TOUCH_PAD12_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 939 /*description: .*/ 940 #define SENS_TOUCH_PAD12_DATA 0x003FFFFF 941 #define SENS_TOUCH_PAD12_DATA_M ((SENS_TOUCH_PAD12_DATA_V)<<(SENS_TOUCH_PAD12_DATA_S)) 942 #define SENS_TOUCH_PAD12_DATA_V 0x3FFFFF 943 #define SENS_TOUCH_PAD12_DATA_S 0 944 945 #define SENS_SAR_TOUCH_STATUS13_REG (DR_REG_SENS_BASE + 0xD4) 946 /* SENS_TOUCH_PAD13_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 947 /*description: .*/ 948 #define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007 949 #define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V)<<(SENS_TOUCH_PAD13_DEBOUNCE_S)) 950 #define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7 951 #define SENS_TOUCH_PAD13_DEBOUNCE_S 29 952 /* SENS_TOUCH_PAD13_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 953 /*description: .*/ 954 #define SENS_TOUCH_PAD13_DATA 0x003FFFFF 955 #define SENS_TOUCH_PAD13_DATA_M ((SENS_TOUCH_PAD13_DATA_V)<<(SENS_TOUCH_PAD13_DATA_S)) 956 #define SENS_TOUCH_PAD13_DATA_V 0x3FFFFF 957 #define SENS_TOUCH_PAD13_DATA_S 0 958 959 #define SENS_SAR_TOUCH_STATUS14_REG (DR_REG_SENS_BASE + 0xD8) 960 /* SENS_TOUCH_PAD14_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 961 /*description: .*/ 962 #define SENS_TOUCH_PAD14_DEBOUNCE 0x00000007 963 #define SENS_TOUCH_PAD14_DEBOUNCE_M ((SENS_TOUCH_PAD14_DEBOUNCE_V)<<(SENS_TOUCH_PAD14_DEBOUNCE_S)) 964 #define SENS_TOUCH_PAD14_DEBOUNCE_V 0x7 965 #define SENS_TOUCH_PAD14_DEBOUNCE_S 29 966 /* SENS_TOUCH_PAD14_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 967 /*description: .*/ 968 #define SENS_TOUCH_PAD14_DATA 0x003FFFFF 969 #define SENS_TOUCH_PAD14_DATA_M ((SENS_TOUCH_PAD14_DATA_V)<<(SENS_TOUCH_PAD14_DATA_S)) 970 #define SENS_TOUCH_PAD14_DATA_V 0x3FFFFF 971 #define SENS_TOUCH_PAD14_DATA_S 0 972 973 #define SENS_SAR_TOUCH_SLP_STATUS_REG (DR_REG_SENS_BASE + 0xDC) 974 /* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ 975 /*description: .*/ 976 #define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 977 #define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V)<<(SENS_TOUCH_SLP_DEBOUNCE_S)) 978 #define SENS_TOUCH_SLP_DEBOUNCE_V 0x7 979 #define SENS_TOUCH_SLP_DEBOUNCE_S 29 980 /* SENS_TOUCH_SLP_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ 981 /*description: .*/ 982 #define SENS_TOUCH_SLP_DATA 0x003FFFFF 983 #define SENS_TOUCH_SLP_DATA_M ((SENS_TOUCH_SLP_DATA_V)<<(SENS_TOUCH_SLP_DATA_S)) 984 #define SENS_TOUCH_SLP_DATA_V 0x3FFFFF 985 #define SENS_TOUCH_SLP_DATA_S 0 986 987 #define SENS_SAR_TOUCH_APPR_STATUS_REG (DR_REG_SENS_BASE + 0xE0) 988 /* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ 989 /*description: .*/ 990 #define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF 991 #define SENS_TOUCH_SLP_APPROACH_CNT_M ((SENS_TOUCH_SLP_APPROACH_CNT_V)<<(SENS_TOUCH_SLP_APPROACH_CNT_S)) 992 #define SENS_TOUCH_SLP_APPROACH_CNT_V 0xFF 993 #define SENS_TOUCH_SLP_APPROACH_CNT_S 24 994 /* SENS_TOUCH_APPROACH_PAD0_CNT : RO ;bitpos:[23:16] ;default: 8'd0 ; */ 995 /*description: .*/ 996 #define SENS_TOUCH_APPROACH_PAD0_CNT 0x000000FF 997 #define SENS_TOUCH_APPROACH_PAD0_CNT_M ((SENS_TOUCH_APPROACH_PAD0_CNT_V)<<(SENS_TOUCH_APPROACH_PAD0_CNT_S)) 998 #define SENS_TOUCH_APPROACH_PAD0_CNT_V 0xFF 999 #define SENS_TOUCH_APPROACH_PAD0_CNT_S 16 1000 /* SENS_TOUCH_APPROACH_PAD1_CNT : RO ;bitpos:[15:8] ;default: 8'd0 ; */ 1001 /*description: .*/ 1002 #define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF 1003 #define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V)<<(SENS_TOUCH_APPROACH_PAD1_CNT_S)) 1004 #define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF 1005 #define SENS_TOUCH_APPROACH_PAD1_CNT_S 8 1006 /* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ 1007 /*description: .*/ 1008 #define SENS_TOUCH_APPROACH_PAD2_CNT 0x000000FF 1009 #define SENS_TOUCH_APPROACH_PAD2_CNT_M ((SENS_TOUCH_APPROACH_PAD2_CNT_V)<<(SENS_TOUCH_APPROACH_PAD2_CNT_S)) 1010 #define SENS_TOUCH_APPROACH_PAD2_CNT_V 0xFF 1011 #define SENS_TOUCH_APPROACH_PAD2_CNT_S 0 1012 1013 #define SENS_SAR_COCPU_STATE_REG (DR_REG_SENS_BASE + 0xE4) 1014 /* SENS_COCPU_EBREAK : RO ;bitpos:[30] ;default: 1'b0 ; */ 1015 /*description: check cocpu whether in ebreak.*/ 1016 #define SENS_COCPU_EBREAK (BIT(30)) 1017 #define SENS_COCPU_EBREAK_M (BIT(30)) 1018 #define SENS_COCPU_EBREAK_V 0x1 1019 #define SENS_COCPU_EBREAK_S 30 1020 /* SENS_COCPU_TRAP : RO ;bitpos:[29] ;default: 1'b0 ; */ 1021 /*description: check cocpu whether in trap state.*/ 1022 #define SENS_COCPU_TRAP (BIT(29)) 1023 #define SENS_COCPU_TRAP_M (BIT(29)) 1024 #define SENS_COCPU_TRAP_V 0x1 1025 #define SENS_COCPU_TRAP_S 29 1026 /* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */ 1027 /*description: check cocpu whether in interrupt state.*/ 1028 #define SENS_COCPU_EOI (BIT(28)) 1029 #define SENS_COCPU_EOI_M (BIT(28)) 1030 #define SENS_COCPU_EOI_V 0x1 1031 #define SENS_COCPU_EOI_S 28 1032 /* SENS_COCPU_RESET_N : RO ;bitpos:[27] ;default: 1'b0 ; */ 1033 /*description: check cocpu whether in reset state.*/ 1034 #define SENS_COCPU_RESET_N (BIT(27)) 1035 #define SENS_COCPU_RESET_N_M (BIT(27)) 1036 #define SENS_COCPU_RESET_N_V 0x1 1037 #define SENS_COCPU_RESET_N_S 27 1038 /* SENS_COCPU_CLK_EN_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ 1039 /*description: check cocpu whether clk on.*/ 1040 #define SENS_COCPU_CLK_EN_ST (BIT(26)) 1041 #define SENS_COCPU_CLK_EN_ST_M (BIT(26)) 1042 #define SENS_COCPU_CLK_EN_ST_V 0x1 1043 #define SENS_COCPU_CLK_EN_ST_S 26 1044 /* SENS_COCPU_DBG_TRIGGER : WO ;bitpos:[25] ;default: 1'b0 ; */ 1045 /*description: trigger cocpu debug registers.*/ 1046 #define SENS_COCPU_DBG_TRIGGER (BIT(25)) 1047 #define SENS_COCPU_DBG_TRIGGER_M (BIT(25)) 1048 #define SENS_COCPU_DBG_TRIGGER_V 0x1 1049 #define SENS_COCPU_DBG_TRIGGER_S 25 1050 1051 #define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0xE8) 1052 /* SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 1053 /*description: .*/ 1054 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW (BIT(11)) 1055 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_M (BIT(11)) 1056 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_V 0x1 1057 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_S 11 1058 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 1059 /*description: .*/ 1060 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(10)) 1061 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(10)) 1062 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 1063 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 10 1064 /* SENS_COCPU_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 1065 /*description: .*/ 1066 #define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW (BIT(9)) 1067 #define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_M (BIT(9)) 1068 #define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_V 0x1 1069 #define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_S 9 1070 /* SENS_COCPU_SWD_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 1071 /*description: int from super watch dog.*/ 1072 #define SENS_COCPU_SWD_INT_RAW (BIT(8)) 1073 #define SENS_COCPU_SWD_INT_RAW_M (BIT(8)) 1074 #define SENS_COCPU_SWD_INT_RAW_V 0x1 1075 #define SENS_COCPU_SWD_INT_RAW_S 8 1076 /* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 1077 /*description: int from software.*/ 1078 #define SENS_COCPU_SW_INT_RAW (BIT(7)) 1079 #define SENS_COCPU_SW_INT_RAW_M (BIT(7)) 1080 #define SENS_COCPU_SW_INT_RAW_V 0x1 1081 #define SENS_COCPU_SW_INT_RAW_S 7 1082 /* SENS_COCPU_START_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 1083 /*description: int from start.*/ 1084 #define SENS_COCPU_START_INT_RAW (BIT(6)) 1085 #define SENS_COCPU_START_INT_RAW_M (BIT(6)) 1086 #define SENS_COCPU_START_INT_RAW_V 0x1 1087 #define SENS_COCPU_START_INT_RAW_S 6 1088 /* SENS_COCPU_TSENS_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 1089 /*description: int from tsens.*/ 1090 #define SENS_COCPU_TSENS_INT_RAW (BIT(5)) 1091 #define SENS_COCPU_TSENS_INT_RAW_M (BIT(5)) 1092 #define SENS_COCPU_TSENS_INT_RAW_V 0x1 1093 #define SENS_COCPU_TSENS_INT_RAW_S 5 1094 /* SENS_COCPU_SARADC2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 1095 /*description: int from saradc2.*/ 1096 #define SENS_COCPU_SARADC2_INT_RAW (BIT(4)) 1097 #define SENS_COCPU_SARADC2_INT_RAW_M (BIT(4)) 1098 #define SENS_COCPU_SARADC2_INT_RAW_V 0x1 1099 #define SENS_COCPU_SARADC2_INT_RAW_S 4 1100 /* SENS_COCPU_SARADC1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 1101 /*description: int from saradc1.*/ 1102 #define SENS_COCPU_SARADC1_INT_RAW (BIT(3)) 1103 #define SENS_COCPU_SARADC1_INT_RAW_M (BIT(3)) 1104 #define SENS_COCPU_SARADC1_INT_RAW_V 0x1 1105 #define SENS_COCPU_SARADC1_INT_RAW_S 3 1106 /* SENS_COCPU_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 1107 /*description: int from touch active.*/ 1108 #define SENS_COCPU_TOUCH_ACTIVE_INT_RAW (BIT(2)) 1109 #define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M (BIT(2)) 1110 #define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V 0x1 1111 #define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S 2 1112 /* SENS_COCPU_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 1113 /*description: int from touch inactive.*/ 1114 #define SENS_COCPU_TOUCH_INACTIVE_INT_RAW (BIT(1)) 1115 #define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M (BIT(1)) 1116 #define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V 0x1 1117 #define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S 1 1118 /* SENS_COCPU_TOUCH_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 1119 /*description: int from touch done.*/ 1120 #define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0)) 1121 #define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0)) 1122 #define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1 1123 #define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0 1124 1125 #define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0xEC) 1126 /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1127 /*description: .*/ 1128 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA (BIT(11)) 1129 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_M (BIT(11)) 1130 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_V 0x1 1131 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_S 11 1132 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1133 /*description: .*/ 1134 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(10)) 1135 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(10)) 1136 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 1137 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 10 1138 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1139 /*description: .*/ 1140 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA (BIT(9)) 1141 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_M (BIT(9)) 1142 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V 0x1 1143 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S 9 1144 /* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1145 /*description: .*/ 1146 #define SENS_COCPU_SWD_INT_ENA (BIT(8)) 1147 #define SENS_COCPU_SWD_INT_ENA_M (BIT(8)) 1148 #define SENS_COCPU_SWD_INT_ENA_V 0x1 1149 #define SENS_COCPU_SWD_INT_ENA_S 8 1150 /* SENS_COCPU_SW_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1151 /*description: cocpu int enable.*/ 1152 #define SENS_COCPU_SW_INT_ENA (BIT(7)) 1153 #define SENS_COCPU_SW_INT_ENA_M (BIT(7)) 1154 #define SENS_COCPU_SW_INT_ENA_V 0x1 1155 #define SENS_COCPU_SW_INT_ENA_S 7 1156 /* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1157 /*description: .*/ 1158 #define SENS_COCPU_START_INT_ENA (BIT(6)) 1159 #define SENS_COCPU_START_INT_ENA_M (BIT(6)) 1160 #define SENS_COCPU_START_INT_ENA_V 0x1 1161 #define SENS_COCPU_START_INT_ENA_S 6 1162 /* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1163 /*description: .*/ 1164 #define SENS_COCPU_TSENS_INT_ENA (BIT(5)) 1165 #define SENS_COCPU_TSENS_INT_ENA_M (BIT(5)) 1166 #define SENS_COCPU_TSENS_INT_ENA_V 0x1 1167 #define SENS_COCPU_TSENS_INT_ENA_S 5 1168 /* SENS_COCPU_SARADC2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1169 /*description: .*/ 1170 #define SENS_COCPU_SARADC2_INT_ENA (BIT(4)) 1171 #define SENS_COCPU_SARADC2_INT_ENA_M (BIT(4)) 1172 #define SENS_COCPU_SARADC2_INT_ENA_V 0x1 1173 #define SENS_COCPU_SARADC2_INT_ENA_S 4 1174 /* SENS_COCPU_SARADC1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1175 /*description: .*/ 1176 #define SENS_COCPU_SARADC1_INT_ENA (BIT(3)) 1177 #define SENS_COCPU_SARADC1_INT_ENA_M (BIT(3)) 1178 #define SENS_COCPU_SARADC1_INT_ENA_V 0x1 1179 #define SENS_COCPU_SARADC1_INT_ENA_S 3 1180 /* SENS_COCPU_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1181 /*description: .*/ 1182 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA (BIT(2)) 1183 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M (BIT(2)) 1184 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V 0x1 1185 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S 2 1186 /* SENS_COCPU_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1187 /*description: .*/ 1188 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1)) 1189 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1)) 1190 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1 1191 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1 1192 /* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1193 /*description: .*/ 1194 #define SENS_COCPU_TOUCH_DONE_INT_ENA (BIT(0)) 1195 #define SENS_COCPU_TOUCH_DONE_INT_ENA_M (BIT(0)) 1196 #define SENS_COCPU_TOUCH_DONE_INT_ENA_V 0x1 1197 #define SENS_COCPU_TOUCH_DONE_INT_ENA_S 0 1198 1199 #define SENS_SAR_COCPU_INT_ST_REG (DR_REG_SENS_BASE + 0xF0) 1200 /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 1201 /*description: .*/ 1202 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST (BIT(11)) 1203 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_M (BIT(11)) 1204 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_V 0x1 1205 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_S 11 1206 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 1207 /*description: .*/ 1208 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(10)) 1209 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(10)) 1210 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 1211 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 10 1212 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 1213 /*description: .*/ 1214 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ST (BIT(9)) 1215 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_M (BIT(9)) 1216 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V 0x1 1217 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S 9 1218 /* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 1219 /*description: .*/ 1220 #define SENS_COCPU_SWD_INT_ST (BIT(8)) 1221 #define SENS_COCPU_SWD_INT_ST_M (BIT(8)) 1222 #define SENS_COCPU_SWD_INT_ST_V 0x1 1223 #define SENS_COCPU_SWD_INT_ST_S 8 1224 /* SENS_COCPU_SW_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 1225 /*description: cocpu int status.*/ 1226 #define SENS_COCPU_SW_INT_ST (BIT(7)) 1227 #define SENS_COCPU_SW_INT_ST_M (BIT(7)) 1228 #define SENS_COCPU_SW_INT_ST_V 0x1 1229 #define SENS_COCPU_SW_INT_ST_S 7 1230 /* SENS_COCPU_START_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 1231 /*description: .*/ 1232 #define SENS_COCPU_START_INT_ST (BIT(6)) 1233 #define SENS_COCPU_START_INT_ST_M (BIT(6)) 1234 #define SENS_COCPU_START_INT_ST_V 0x1 1235 #define SENS_COCPU_START_INT_ST_S 6 1236 /* SENS_COCPU_TSENS_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 1237 /*description: .*/ 1238 #define SENS_COCPU_TSENS_INT_ST (BIT(5)) 1239 #define SENS_COCPU_TSENS_INT_ST_M (BIT(5)) 1240 #define SENS_COCPU_TSENS_INT_ST_V 0x1 1241 #define SENS_COCPU_TSENS_INT_ST_S 5 1242 /* SENS_COCPU_SARADC2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1243 /*description: .*/ 1244 #define SENS_COCPU_SARADC2_INT_ST (BIT(4)) 1245 #define SENS_COCPU_SARADC2_INT_ST_M (BIT(4)) 1246 #define SENS_COCPU_SARADC2_INT_ST_V 0x1 1247 #define SENS_COCPU_SARADC2_INT_ST_S 4 1248 /* SENS_COCPU_SARADC1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1249 /*description: .*/ 1250 #define SENS_COCPU_SARADC1_INT_ST (BIT(3)) 1251 #define SENS_COCPU_SARADC1_INT_ST_M (BIT(3)) 1252 #define SENS_COCPU_SARADC1_INT_ST_V 0x1 1253 #define SENS_COCPU_SARADC1_INT_ST_S 3 1254 /* SENS_COCPU_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1255 /*description: .*/ 1256 #define SENS_COCPU_TOUCH_ACTIVE_INT_ST (BIT(2)) 1257 #define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M (BIT(2)) 1258 #define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V 0x1 1259 #define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S 2 1260 /* SENS_COCPU_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1261 /*description: .*/ 1262 #define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1)) 1263 #define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1)) 1264 #define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1 1265 #define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1 1266 /* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1267 /*description: .*/ 1268 #define SENS_COCPU_TOUCH_DONE_INT_ST (BIT(0)) 1269 #define SENS_COCPU_TOUCH_DONE_INT_ST_M (BIT(0)) 1270 #define SENS_COCPU_TOUCH_DONE_INT_ST_V 0x1 1271 #define SENS_COCPU_TOUCH_DONE_INT_ST_S 0 1272 1273 #define SENS_SAR_COCPU_INT_CLR_REG (DR_REG_SENS_BASE + 0xF4) 1274 /* SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 1275 /*description: .*/ 1276 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR (BIT(11)) 1277 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_M (BIT(11)) 1278 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_V 0x1 1279 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_S 11 1280 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 1281 /*description: .*/ 1282 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(10)) 1283 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(10)) 1284 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 1285 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 10 1286 /* SENS_COCPU_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 1287 /*description: .*/ 1288 #define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR (BIT(9)) 1289 #define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_M (BIT(9)) 1290 #define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V 0x1 1291 #define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S 9 1292 /* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 1293 /*description: .*/ 1294 #define SENS_COCPU_SWD_INT_CLR (BIT(8)) 1295 #define SENS_COCPU_SWD_INT_CLR_M (BIT(8)) 1296 #define SENS_COCPU_SWD_INT_CLR_V 0x1 1297 #define SENS_COCPU_SWD_INT_CLR_S 8 1298 /* SENS_COCPU_SW_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 1299 /*description: cocpu int clear.*/ 1300 #define SENS_COCPU_SW_INT_CLR (BIT(7)) 1301 #define SENS_COCPU_SW_INT_CLR_M (BIT(7)) 1302 #define SENS_COCPU_SW_INT_CLR_V 0x1 1303 #define SENS_COCPU_SW_INT_CLR_S 7 1304 /* SENS_COCPU_START_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 1305 /*description: .*/ 1306 #define SENS_COCPU_START_INT_CLR (BIT(6)) 1307 #define SENS_COCPU_START_INT_CLR_M (BIT(6)) 1308 #define SENS_COCPU_START_INT_CLR_V 0x1 1309 #define SENS_COCPU_START_INT_CLR_S 6 1310 /* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 1311 /*description: .*/ 1312 #define SENS_COCPU_TSENS_INT_CLR (BIT(5)) 1313 #define SENS_COCPU_TSENS_INT_CLR_M (BIT(5)) 1314 #define SENS_COCPU_TSENS_INT_CLR_V 0x1 1315 #define SENS_COCPU_TSENS_INT_CLR_S 5 1316 /* SENS_COCPU_SARADC2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 1317 /*description: .*/ 1318 #define SENS_COCPU_SARADC2_INT_CLR (BIT(4)) 1319 #define SENS_COCPU_SARADC2_INT_CLR_M (BIT(4)) 1320 #define SENS_COCPU_SARADC2_INT_CLR_V 0x1 1321 #define SENS_COCPU_SARADC2_INT_CLR_S 4 1322 /* SENS_COCPU_SARADC1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 1323 /*description: .*/ 1324 #define SENS_COCPU_SARADC1_INT_CLR (BIT(3)) 1325 #define SENS_COCPU_SARADC1_INT_CLR_M (BIT(3)) 1326 #define SENS_COCPU_SARADC1_INT_CLR_V 0x1 1327 #define SENS_COCPU_SARADC1_INT_CLR_S 3 1328 /* SENS_COCPU_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 1329 /*description: .*/ 1330 #define SENS_COCPU_TOUCH_ACTIVE_INT_CLR (BIT(2)) 1331 #define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M (BIT(2)) 1332 #define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V 0x1 1333 #define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S 2 1334 /* SENS_COCPU_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 1335 /*description: .*/ 1336 #define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1)) 1337 #define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1)) 1338 #define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1 1339 #define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1 1340 /* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 1341 /*description: .*/ 1342 #define SENS_COCPU_TOUCH_DONE_INT_CLR (BIT(0)) 1343 #define SENS_COCPU_TOUCH_DONE_INT_CLR_M (BIT(0)) 1344 #define SENS_COCPU_TOUCH_DONE_INT_CLR_V 0x1 1345 #define SENS_COCPU_TOUCH_DONE_INT_CLR_S 0 1346 1347 #define SENS_SAR_COCPU_DEBUG_REG (DR_REG_SENS_BASE + 0xF8) 1348 /* SENS_COCPU_MEM_ADDR : RO ;bitpos:[31:19] ;default: 13'd0 ; */ 1349 /*description: cocpu mem address output.*/ 1350 #define SENS_COCPU_MEM_ADDR 0x00001FFF 1351 #define SENS_COCPU_MEM_ADDR_M ((SENS_COCPU_MEM_ADDR_V)<<(SENS_COCPU_MEM_ADDR_S)) 1352 #define SENS_COCPU_MEM_ADDR_V 0x1FFF 1353 #define SENS_COCPU_MEM_ADDR_S 19 1354 /* SENS_COCPU_MEM_WEN : RO ;bitpos:[18:15] ;default: 4'd0 ; */ 1355 /*description: cocpu mem write enable output.*/ 1356 #define SENS_COCPU_MEM_WEN 0x0000000F 1357 #define SENS_COCPU_MEM_WEN_M ((SENS_COCPU_MEM_WEN_V)<<(SENS_COCPU_MEM_WEN_S)) 1358 #define SENS_COCPU_MEM_WEN_V 0xF 1359 #define SENS_COCPU_MEM_WEN_S 15 1360 /* SENS_COCPU_MEM_RDY : RO ;bitpos:[14] ;default: 1'b0 ; */ 1361 /*description: cocpu mem ready input.*/ 1362 #define SENS_COCPU_MEM_RDY (BIT(14)) 1363 #define SENS_COCPU_MEM_RDY_M (BIT(14)) 1364 #define SENS_COCPU_MEM_RDY_V 0x1 1365 #define SENS_COCPU_MEM_RDY_S 14 1366 /* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */ 1367 /*description: cocpu mem valid output.*/ 1368 #define SENS_COCPU_MEM_VLD (BIT(13)) 1369 #define SENS_COCPU_MEM_VLD_M (BIT(13)) 1370 #define SENS_COCPU_MEM_VLD_V 0x1 1371 #define SENS_COCPU_MEM_VLD_S 13 1372 /* SENS_COCPU_PC : RO ;bitpos:[12:0] ;default: 13'd0 ; */ 1373 /*description: cocpu Program counter.*/ 1374 #define SENS_COCPU_PC 0x00001FFF 1375 #define SENS_COCPU_PC_M ((SENS_COCPU_PC_V)<<(SENS_COCPU_PC_S)) 1376 #define SENS_COCPU_PC_V 0x1FFF 1377 #define SENS_COCPU_PC_S 0 1378 1379 #define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0xFC) 1380 /* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */ 1381 /*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-cop 1382 rocessor.*/ 1383 #define SENS_HALL_PHASE_FORCE (BIT(31)) 1384 #define SENS_HALL_PHASE_FORCE_M (BIT(31)) 1385 #define SENS_HALL_PHASE_FORCE_V 0x1 1386 #define SENS_HALL_PHASE_FORCE_S 31 1387 /* SENS_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1388 /*description: Reverse phase of hall sensor.*/ 1389 #define SENS_HALL_PHASE (BIT(30)) 1390 #define SENS_HALL_PHASE_M (BIT(30)) 1391 #define SENS_HALL_PHASE_V 0x1 1392 #define SENS_HALL_PHASE_S 30 1393 /* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */ 1394 /*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coproce 1395 ssor.*/ 1396 #define SENS_XPD_HALL_FORCE (BIT(29)) 1397 #define SENS_XPD_HALL_FORCE_M (BIT(29)) 1398 #define SENS_XPD_HALL_FORCE_V 0x1 1399 #define SENS_XPD_HALL_FORCE_S 29 1400 /* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */ 1401 /*description: Power on hall sensor and connect to VP and VN.*/ 1402 #define SENS_XPD_HALL (BIT(28)) 1403 #define SENS_XPD_HALL_M (BIT(28)) 1404 #define SENS_XPD_HALL_V 0x1 1405 #define SENS_XPD_HALL_S 28 1406 1407 #define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x100) 1408 /* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1409 /*description: .*/ 1410 #define SENS_SAR_NOUSE 0xFFFFFFFF 1411 #define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S)) 1412 #define SENS_SAR_NOUSE_V 0xFFFFFFFF 1413 #define SENS_SAR_NOUSE_S 0 1414 1415 #define SENS_SAR_PERI_CLK_GATE_CONF_REG (DR_REG_SENS_BASE + 0x104) 1416 /* SENS_IOMUX_CLK_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 1417 /*description: .*/ 1418 #define SENS_IOMUX_CLK_EN (BIT(31)) 1419 #define SENS_IOMUX_CLK_EN_M (BIT(31)) 1420 #define SENS_IOMUX_CLK_EN_V 0x1 1421 #define SENS_IOMUX_CLK_EN_S 31 1422 /* SENS_SARADC_CLK_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1423 /*description: .*/ 1424 #define SENS_SARADC_CLK_EN (BIT(30)) 1425 #define SENS_SARADC_CLK_EN_M (BIT(30)) 1426 #define SENS_SARADC_CLK_EN_V 0x1 1427 #define SENS_SARADC_CLK_EN_S 30 1428 /* SENS_TSENS_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1429 /*description: .*/ 1430 #define SENS_TSENS_CLK_EN (BIT(29)) 1431 #define SENS_TSENS_CLK_EN_M (BIT(29)) 1432 #define SENS_TSENS_CLK_EN_V 0x1 1433 #define SENS_TSENS_CLK_EN_S 29 1434 /* SENS_RTC_I2C_CLK_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1435 /*description: .*/ 1436 #define SENS_RTC_I2C_CLK_EN (BIT(27)) 1437 #define SENS_RTC_I2C_CLK_EN_M (BIT(27)) 1438 #define SENS_RTC_I2C_CLK_EN_V 0x1 1439 #define SENS_RTC_I2C_CLK_EN_S 27 1440 1441 #define SENS_SAR_PERI_RESET_CONF_REG (DR_REG_SENS_BASE + 0x108) 1442 /* SENS_SARADC_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1443 /*description: .*/ 1444 #define SENS_SARADC_RESET (BIT(30)) 1445 #define SENS_SARADC_RESET_M (BIT(30)) 1446 #define SENS_SARADC_RESET_V 0x1 1447 #define SENS_SARADC_RESET_S 30 1448 /* SENS_TSENS_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1449 /*description: .*/ 1450 #define SENS_TSENS_RESET (BIT(29)) 1451 #define SENS_TSENS_RESET_M (BIT(29)) 1452 #define SENS_TSENS_RESET_V 0x1 1453 #define SENS_TSENS_RESET_S 29 1454 /* SENS_RTC_I2C_RESET : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1455 /*description: .*/ 1456 #define SENS_RTC_I2C_RESET (BIT(27)) 1457 #define SENS_RTC_I2C_RESET_M (BIT(27)) 1458 #define SENS_RTC_I2C_RESET_V 0x1 1459 #define SENS_RTC_I2C_RESET_S 27 1460 /* SENS_COCPU_RESET : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1461 /*description: .*/ 1462 #define SENS_COCPU_RESET (BIT(25)) 1463 #define SENS_COCPU_RESET_M (BIT(25)) 1464 #define SENS_COCPU_RESET_V 0x1 1465 #define SENS_COCPU_RESET_S 25 1466 1467 #define SENS_SAR_COCPU_INT_ENA_W1TS_REG (DR_REG_SENS_BASE + 0x10C) 1468 /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ 1469 /*description: .*/ 1470 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(11)) 1471 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(11)) 1472 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 1473 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 11 1474 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ 1475 /*description: .*/ 1476 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(10)) 1477 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(10)) 1478 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 1479 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 10 1480 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ 1481 /*description: .*/ 1482 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(9)) 1483 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(9)) 1484 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 1485 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_S 9 1486 /* SENS_COCPU_SWD_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ 1487 /*description: .*/ 1488 #define SENS_COCPU_SWD_INT_ENA_W1TS (BIT(8)) 1489 #define SENS_COCPU_SWD_INT_ENA_W1TS_M (BIT(8)) 1490 #define SENS_COCPU_SWD_INT_ENA_W1TS_V 0x1 1491 #define SENS_COCPU_SWD_INT_ENA_W1TS_S 8 1492 /* SENS_COCPU_SW_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ 1493 /*description: .*/ 1494 #define SENS_COCPU_SW_INT_ENA_W1TS (BIT(7)) 1495 #define SENS_COCPU_SW_INT_ENA_W1TS_M (BIT(7)) 1496 #define SENS_COCPU_SW_INT_ENA_W1TS_V 0x1 1497 #define SENS_COCPU_SW_INT_ENA_W1TS_S 7 1498 /* SENS_COCPU_START_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ 1499 /*description: .*/ 1500 #define SENS_COCPU_START_INT_ENA_W1TS (BIT(6)) 1501 #define SENS_COCPU_START_INT_ENA_W1TS_M (BIT(6)) 1502 #define SENS_COCPU_START_INT_ENA_W1TS_V 0x1 1503 #define SENS_COCPU_START_INT_ENA_W1TS_S 6 1504 /* SENS_COCPU_TSENS_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ 1505 /*description: .*/ 1506 #define SENS_COCPU_TSENS_INT_ENA_W1TS (BIT(5)) 1507 #define SENS_COCPU_TSENS_INT_ENA_W1TS_M (BIT(5)) 1508 #define SENS_COCPU_TSENS_INT_ENA_W1TS_V 0x1 1509 #define SENS_COCPU_TSENS_INT_ENA_W1TS_S 5 1510 /* SENS_COCPU_SARADC2_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ 1511 /*description: .*/ 1512 #define SENS_COCPU_SARADC2_INT_ENA_W1TS (BIT(4)) 1513 #define SENS_COCPU_SARADC2_INT_ENA_W1TS_M (BIT(4)) 1514 #define SENS_COCPU_SARADC2_INT_ENA_W1TS_V 0x1 1515 #define SENS_COCPU_SARADC2_INT_ENA_W1TS_S 4 1516 /* SENS_COCPU_SARADC1_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ 1517 /*description: .*/ 1518 #define SENS_COCPU_SARADC1_INT_ENA_W1TS (BIT(3)) 1519 #define SENS_COCPU_SARADC1_INT_ENA_W1TS_M (BIT(3)) 1520 #define SENS_COCPU_SARADC1_INT_ENA_W1TS_V 0x1 1521 #define SENS_COCPU_SARADC1_INT_ENA_W1TS_S 3 1522 /* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ 1523 /*description: .*/ 1524 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(2)) 1525 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(2)) 1526 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 1527 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S 2 1528 /* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ 1529 /*description: .*/ 1530 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(1)) 1531 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(1)) 1532 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 1533 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_S 1 1534 /* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ 1535 /*description: .*/ 1536 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS (BIT(0)) 1537 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_M (BIT(0)) 1538 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_V 0x1 1539 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_S 0 1540 1541 #define SENS_SAR_COCPU_INT_ENA_W1TC_REG (DR_REG_SENS_BASE + 0x110) 1542 /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ 1543 /*description: .*/ 1544 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(11)) 1545 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(11)) 1546 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 1547 #define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 11 1548 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ 1549 /*description: .*/ 1550 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(10)) 1551 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(10)) 1552 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 1553 #define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 10 1554 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ 1555 /*description: .*/ 1556 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(9)) 1557 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(9)) 1558 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 1559 #define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_S 9 1560 /* SENS_COCPU_SWD_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ 1561 /*description: .*/ 1562 #define SENS_COCPU_SWD_INT_ENA_W1TC (BIT(8)) 1563 #define SENS_COCPU_SWD_INT_ENA_W1TC_M (BIT(8)) 1564 #define SENS_COCPU_SWD_INT_ENA_W1TC_V 0x1 1565 #define SENS_COCPU_SWD_INT_ENA_W1TC_S 8 1566 /* SENS_COCPU_SW_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ 1567 /*description: .*/ 1568 #define SENS_COCPU_SW_INT_ENA_W1TC (BIT(7)) 1569 #define SENS_COCPU_SW_INT_ENA_W1TC_M (BIT(7)) 1570 #define SENS_COCPU_SW_INT_ENA_W1TC_V 0x1 1571 #define SENS_COCPU_SW_INT_ENA_W1TC_S 7 1572 /* SENS_COCPU_START_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ 1573 /*description: .*/ 1574 #define SENS_COCPU_START_INT_ENA_W1TC (BIT(6)) 1575 #define SENS_COCPU_START_INT_ENA_W1TC_M (BIT(6)) 1576 #define SENS_COCPU_START_INT_ENA_W1TC_V 0x1 1577 #define SENS_COCPU_START_INT_ENA_W1TC_S 6 1578 /* SENS_COCPU_TSENS_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ 1579 /*description: .*/ 1580 #define SENS_COCPU_TSENS_INT_ENA_W1TC (BIT(5)) 1581 #define SENS_COCPU_TSENS_INT_ENA_W1TC_M (BIT(5)) 1582 #define SENS_COCPU_TSENS_INT_ENA_W1TC_V 0x1 1583 #define SENS_COCPU_TSENS_INT_ENA_W1TC_S 5 1584 /* SENS_COCPU_SARADC2_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ 1585 /*description: .*/ 1586 #define SENS_COCPU_SARADC2_INT_ENA_W1TC (BIT(4)) 1587 #define SENS_COCPU_SARADC2_INT_ENA_W1TC_M (BIT(4)) 1588 #define SENS_COCPU_SARADC2_INT_ENA_W1TC_V 0x1 1589 #define SENS_COCPU_SARADC2_INT_ENA_W1TC_S 4 1590 /* SENS_COCPU_SARADC1_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ 1591 /*description: .*/ 1592 #define SENS_COCPU_SARADC1_INT_ENA_W1TC (BIT(3)) 1593 #define SENS_COCPU_SARADC1_INT_ENA_W1TC_M (BIT(3)) 1594 #define SENS_COCPU_SARADC1_INT_ENA_W1TC_V 0x1 1595 #define SENS_COCPU_SARADC1_INT_ENA_W1TC_S 3 1596 /* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ 1597 /*description: .*/ 1598 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(2)) 1599 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(2)) 1600 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 1601 #define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_S 2 1602 /* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ 1603 /*description: .*/ 1604 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(1)) 1605 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(1)) 1606 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 1607 #define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_S 1 1608 /* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ 1609 /*description: .*/ 1610 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC (BIT(0)) 1611 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_M (BIT(0)) 1612 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V 0x1 1613 #define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S 0 1614 1615 #define SENS_SAR_DEBUG_CONF_REG (DR_REG_SENS_BASE + 0x114) 1616 /* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ 1617 /*description: .*/ 1618 #define SENS_DEBUG_BIT_SEL 0x0000001F 1619 #define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S)) 1620 #define SENS_DEBUG_BIT_SEL_V 0x1F 1621 #define SENS_DEBUG_BIT_SEL_S 0 1622 1623 #define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x1FC) 1624 /* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */ 1625 /*description: .*/ 1626 #define SENS_SAR_DATE 0x0FFFFFFF 1627 #define SENS_SAR_DATE_M ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S)) 1628 #define SENS_SAR_DATE_V 0xFFFFFFF 1629 #define SENS_SAR_DATE_S 0 1630 1631 1632 #ifdef __cplusplus 1633 } 1634 #endif 1635 1636 1637 1638 #endif /*_SOC_SENS_REG_H_ */ 1639
