1 /** 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** SENSITIVE_ROM_TABLE_LOCK_REG register 15 * register description 16 */ 17 #define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0) 18 /** SENSITIVE_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; 19 * Need add description 20 */ 21 #define SENSITIVE_ROM_TABLE_LOCK (BIT(0)) 22 #define SENSITIVE_ROM_TABLE_LOCK_M (SENSITIVE_ROM_TABLE_LOCK_V << SENSITIVE_ROM_TABLE_LOCK_S) 23 #define SENSITIVE_ROM_TABLE_LOCK_V 0x00000001U 24 #define SENSITIVE_ROM_TABLE_LOCK_S 0 25 26 /** SENSITIVE_ROM_TABLE_REG register 27 * register description 28 */ 29 #define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4) 30 /** SENSITIVE_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; 31 * Need add description 32 */ 33 #define SENSITIVE_ROM_TABLE 0xFFFFFFFFU 34 #define SENSITIVE_ROM_TABLE_M (SENSITIVE_ROM_TABLE_V << SENSITIVE_ROM_TABLE_S) 35 #define SENSITIVE_ROM_TABLE_V 0xFFFFFFFFU 36 #define SENSITIVE_ROM_TABLE_S 0 37 38 /** SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG register 39 * register description 40 */ 41 #define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8) 42 /** SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; 43 * Need add description 44 */ 45 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) 46 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V << SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S) 47 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x00000001U 48 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 49 50 /** SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG register 51 * register description 52 */ 53 #define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xc) 54 /** SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W; bitpos: [0]; default: 1; 55 * Need add description 56 */ 57 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) 58 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V << SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S) 59 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x00000001U 60 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 61 62 /** SENSITIVE_INTERNAL_SRAM_USAGE_0_REG register 63 * register description 64 */ 65 #define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10) 66 /** SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W; bitpos: [0]; default: 0; 67 * Need add description 68 */ 69 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) 70 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S) 71 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x00000001U 72 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 73 74 /** SENSITIVE_INTERNAL_SRAM_USAGE_1_REG register 75 * register description 76 */ 77 #define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14) 78 /** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W; bitpos: [0]; default: 1; 79 * Need add description 80 */ 81 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0)) 82 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S) 83 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x00000001U 84 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0 85 /** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W; bitpos: [3:1]; default: 7; 86 * Need add description 87 */ 88 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007U 89 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S) 90 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x00000007U 91 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1 92 93 /** SENSITIVE_INTERNAL_SRAM_USAGE_3_REG register 94 * register description 95 */ 96 #define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x18) 97 /** SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W; bitpos: [2:0]; default: 0; 98 * Need add description 99 */ 100 #define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007U 101 #define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S) 102 #define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x00000007U 103 #define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0 104 /** SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W; bitpos: [3]; default: 0; 105 * Need add description 106 */ 107 #define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3)) 108 #define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V << SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S) 109 #define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x00000001U 110 #define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3 111 112 /** SENSITIVE_CACHE_TAG_ACCESS_0_REG register 113 * register description 114 */ 115 #define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x1c) 116 /** SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; 117 * Need add description 118 */ 119 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) 120 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (SENSITIVE_CACHE_TAG_ACCESS_LOCK_V << SENSITIVE_CACHE_TAG_ACCESS_LOCK_S) 121 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x00000001U 122 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 123 124 /** SENSITIVE_CACHE_TAG_ACCESS_1_REG register 125 * register description 126 */ 127 #define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x20) 128 /** SENSITIVE_PRO_I_TAG_RD_ACS : R/W; bitpos: [0]; default: 1; 129 * Need add description 130 */ 131 #define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) 132 #define SENSITIVE_PRO_I_TAG_RD_ACS_M (SENSITIVE_PRO_I_TAG_RD_ACS_V << SENSITIVE_PRO_I_TAG_RD_ACS_S) 133 #define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x00000001U 134 #define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 135 /** SENSITIVE_PRO_I_TAG_WR_ACS : R/W; bitpos: [1]; default: 1; 136 * Need add description 137 */ 138 #define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) 139 #define SENSITIVE_PRO_I_TAG_WR_ACS_M (SENSITIVE_PRO_I_TAG_WR_ACS_V << SENSITIVE_PRO_I_TAG_WR_ACS_S) 140 #define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x00000001U 141 #define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 142 /** SENSITIVE_PRO_D_TAG_RD_ACS : R/W; bitpos: [2]; default: 1; 143 * Need add description 144 */ 145 #define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) 146 #define SENSITIVE_PRO_D_TAG_RD_ACS_M (SENSITIVE_PRO_D_TAG_RD_ACS_V << SENSITIVE_PRO_D_TAG_RD_ACS_S) 147 #define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x00000001U 148 #define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 149 /** SENSITIVE_PRO_D_TAG_WR_ACS : R/W; bitpos: [3]; default: 1; 150 * Need add description 151 */ 152 #define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) 153 #define SENSITIVE_PRO_D_TAG_WR_ACS_M (SENSITIVE_PRO_D_TAG_WR_ACS_V << SENSITIVE_PRO_D_TAG_WR_ACS_S) 154 #define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x00000001U 155 #define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 156 157 /** SENSITIVE_CACHE_MMU_ACCESS_0_REG register 158 * register description 159 */ 160 #define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x24) 161 /** SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; 162 * Need add description 163 */ 164 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) 165 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (SENSITIVE_CACHE_MMU_ACCESS_LOCK_V << SENSITIVE_CACHE_MMU_ACCESS_LOCK_S) 166 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x00000001U 167 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 168 169 /** SENSITIVE_CACHE_MMU_ACCESS_1_REG register 170 * register description 171 */ 172 #define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x28) 173 /** SENSITIVE_PRO_MMU_RD_ACS : R/W; bitpos: [0]; default: 1; 174 * Need add description 175 */ 176 #define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) 177 #define SENSITIVE_PRO_MMU_RD_ACS_M (SENSITIVE_PRO_MMU_RD_ACS_V << SENSITIVE_PRO_MMU_RD_ACS_S) 178 #define SENSITIVE_PRO_MMU_RD_ACS_V 0x00000001U 179 #define SENSITIVE_PRO_MMU_RD_ACS_S 0 180 /** SENSITIVE_PRO_MMU_WR_ACS : R/W; bitpos: [1]; default: 1; 181 * Need add description 182 */ 183 #define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) 184 #define SENSITIVE_PRO_MMU_WR_ACS_M (SENSITIVE_PRO_MMU_WR_ACS_V << SENSITIVE_PRO_MMU_WR_ACS_S) 185 #define SENSITIVE_PRO_MMU_WR_ACS_V 0x00000001U 186 #define SENSITIVE_PRO_MMU_WR_ACS_S 1 187 188 /** SENSITIVE_PIF_ACCESS_MONITOR_0_REG register 189 * register description 190 */ 191 #define SENSITIVE_PIF_ACCESS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x2c) 192 /** SENSITIVE_PIF_ACCESS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; 193 * Need add description 194 */ 195 #define SENSITIVE_PIF_ACCESS_MONITOR_LOCK (BIT(0)) 196 #define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_M (SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V << SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S) 197 #define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V 0x00000001U 198 #define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S 0 199 200 /** SENSITIVE_PIF_ACCESS_MONITOR_1_REG register 201 * register description 202 */ 203 #define SENSITIVE_PIF_ACCESS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x30) 204 /** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; 205 * Need add description 206 */ 207 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) 208 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S) 209 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V 0x00000001U 210 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S 0 211 /** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN : R/W; bitpos: [1]; default: 1; 212 * Need add description 213 */ 214 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) 215 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S) 216 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V 0x00000001U 217 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S 1 218 219 /** SENSITIVE_PIF_ACCESS_MONITOR_2_REG register 220 * register description 221 */ 222 #define SENSITIVE_PIF_ACCESS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x34) 223 /** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR : RO; bitpos: [0]; default: 0; 224 * Need add description 225 */ 226 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) 227 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S) 228 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V 0x00000001U 229 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S 0 230 /** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO; bitpos: [2:1]; 231 * default: 0; 232 * Need add description 233 */ 234 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003U 235 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S) 236 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x00000003U 237 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 238 239 /** SENSITIVE_PIF_ACCESS_MONITOR_3_REG register 240 * register description 241 */ 242 #define SENSITIVE_PIF_ACCESS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x38) 243 /** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO; bitpos: [31:0]; 244 * default: 0; 245 * Need add description 246 */ 247 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFFU 248 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S) 249 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFFU 250 #define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 251 252 /** SENSITIVE_XTS_AES_KEY_UPDATE_REG register 253 * register description 254 */ 255 #define SENSITIVE_XTS_AES_KEY_UPDATE_REG (DR_REG_SENSITIVE_BASE + 0x3c) 256 /** SENSITIVE_XTS_AES_KEY_UPDATE : R/W; bitpos: [0]; default: 0; 257 * Set this bit to update xts_aes key 258 */ 259 #define SENSITIVE_XTS_AES_KEY_UPDATE (BIT(0)) 260 #define SENSITIVE_XTS_AES_KEY_UPDATE_M (SENSITIVE_XTS_AES_KEY_UPDATE_V << SENSITIVE_XTS_AES_KEY_UPDATE_S) 261 #define SENSITIVE_XTS_AES_KEY_UPDATE_V 0x00000001U 262 #define SENSITIVE_XTS_AES_KEY_UPDATE_S 0 263 264 /** SENSITIVE_CLOCK_GATE_REG register 265 * register description 266 */ 267 #define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x40) 268 /** SENSITIVE_CLK_EN : R/W; bitpos: [0]; default: 1; 269 * Need add description 270 */ 271 #define SENSITIVE_CLK_EN (BIT(0)) 272 #define SENSITIVE_CLK_EN_M (SENSITIVE_CLK_EN_V << SENSITIVE_CLK_EN_S) 273 #define SENSITIVE_CLK_EN_V 0x00000001U 274 #define SENSITIVE_CLK_EN_S 0 275 276 /** SENSITIVE_SENSITIVE_REG_DATE_REG register 277 * register description 278 */ 279 #define SENSITIVE_SENSITIVE_REG_DATE_REG (DR_REG_SENSITIVE_BASE + 0xffc) 280 /** SENSITIVE_SENSITIVE_REG_DATE : R/W; bitpos: [27:0]; default: 34628353; 281 * Need add description 282 */ 283 #define SENSITIVE_SENSITIVE_REG_DATE 0x0FFFFFFFU 284 #define SENSITIVE_SENSITIVE_REG_DATE_M (SENSITIVE_SENSITIVE_REG_DATE_V << SENSITIVE_SENSITIVE_REG_DATE_S) 285 #define SENSITIVE_SENSITIVE_REG_DATE_V 0x0FFFFFFFU 286 #define SENSITIVE_SENSITIVE_REG_DATE_S 0 287 288 #ifdef __cplusplus 289 } 290 #endif 291
