Searched refs:RTC_CNTL_WDTCONFIG0_REG (Results 1 – 13 of 13) sorted by relevance
| /hal_espressif-latest/components/esp_hw_support/ |
| D | rtc_wdt.c | 32 SET_PERI_REG_MASK(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN | RTC_CNTL_WDT_PAUSE_IN_SLP); in rtc_wdt_enable()
37 REG_SET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); in rtc_wdt_flashboot_mode_enable()
51 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); in rtc_wdt_disable()
52 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN); in rtc_wdt_disable()
122 REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, stage_sel); in rtc_wdt_set_stage()
124 REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG1, stage_sel); in rtc_wdt_set_stage()
126 REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG2, stage_sel); in rtc_wdt_set_stage()
128 REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG3, stage_sel); in rtc_wdt_set_stage()
140 REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_SYS_RESET_LENGTH, reset_signal_length); in rtc_wdt_set_length_of_reset_signal()
142 REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_CPU_RESET_LENGTH, reset_signal_length); in rtc_wdt_set_length_of_reset_signal()
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| /hal_espressif-latest/tools/esptool_py/flasher_stub/include/ |
| D | soc_support.h | 389 #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0098) // RTC_CNTL_RTC_WDTCONFIG0_REG macro
398 #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0090) macro
407 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG macro
416 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG macro
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| /hal_espressif-latest/tools/esptool_py/esptool/targets/ |
| D | esp32c3.py | 85 RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090 variable in ESP32C3ROM
239 self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0)
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| D | esp32h2.py | 20 RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0 # LP_WDT_RWDT_CONFIG0_REG variable in ESP32H2ROM
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| D | esp32s3.py | 93 RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0098 variable in ESP32S3ROM
330 self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0)
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| D | esp32c6.py | 74 RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0 # LP_WDT_RWDT_CONFIG0_REG variable in ESP32C6ROM
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| /hal_espressif-latest/tools/esptool_py/flasher_stub/ |
| D | stub_flasher.c | 116 WRITE_REG(RTC_CNTL_WDTCONFIG0_REG, 0x0); // Disable RTC watchdog in disable_watchdogs()
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| /hal_espressif-latest/tools/esptool_py/test/ |
| D | test_esptool.py | 732 reg_mod.write_reg(reg_mod.RTC_CNTL_WDTCONFIG0_REG, RTC_WDT_ENABLE)
757 output = reg_mod.read_reg(reg_mod.RTC_CNTL_WDTCONFIG0_REG)
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | rtc_cntl_reg.h | 1024 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x84) macro
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| /hal_espressif-latest/components/soc/esp32/include/soc/ |
| D | rtc_cntl_reg.h | 1628 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) macro
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | rtc_cntl_reg.h | 1587 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0090) macro
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| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | rtc_cntl_reg.h | 2074 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0094) macro
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | rtc_cntl_reg.h | 1988 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x98) macro
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