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Searched refs:RTC_CNTL_TIMER3_REG (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_init.c55 … REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles); in rtc_init()
56 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles); in rtc_init()
57 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles); in rtc_init()
58 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_sleep.c127 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_CYCLES); in rtc_sleep_init()
128 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES); in rtc_sleep_init()
130 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, WIFI_POWERUP_CYCLES); in rtc_sleep_init()
131 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, WIFI_WAIT_CYCLES); in rtc_sleep_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_init.c71 … REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles); in rtc_init()
72 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles); in rtc_init()
74 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles); in rtc_init()
75 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_init.c57 … REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles); in rtc_init()
58 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles); in rtc_init()
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h364 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h324 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h320 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h313 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) macro