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Searched refs:RTC_CNTL_SLP_TIMER0_REG (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-latest/components/hal/esp32c2/include/hal/
Drtc_cntl_ll.h21 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h21 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Drtc_cntl_ll.h21 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/hal/esp32/include/hal/
Drtc_cntl_ll.h22 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Drtc_cntl_ll.h25 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h137 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h207 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h174 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h165 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h158 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) macro