1 /*
2  * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _SOC_RTC_CNTL_REG_H_
7 #define _SOC_RTC_CNTL_REG_H_
8 
9 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
10 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
11 /* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
12 #define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
13 
14 /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
15 #define RTC_WDT_RESET_LENGTH_100_NS    0
16 #define RTC_WDT_RESET_LENGTH_200_NS    1
17 #define RTC_WDT_RESET_LENGTH_300_NS    2
18 #define RTC_WDT_RESET_LENGTH_400_NS    3
19 #define RTC_WDT_RESET_LENGTH_500_NS    4
20 #define RTC_WDT_RESET_LENGTH_800_NS    5
21 #define RTC_WDT_RESET_LENGTH_1600_NS   6
22 #define RTC_WDT_RESET_LENGTH_3200_NS   7
23 
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 #include "soc.h"
29 #define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
30 #define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
31 
32 #define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
33 /* RTC_CNTL_SW_SYS_RST :  ;bitpos:[31] ;default: 1'd0 ; */
34 /*description: SW system reset.*/
35 #define RTC_CNTL_SW_SYS_RST    (BIT(31))
36 #define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
37 #define RTC_CNTL_SW_SYS_RST_V  0x1
38 #define RTC_CNTL_SW_SYS_RST_S  31
39 /* RTC_CNTL_DG_WRAP_FORCE_NORST :  ;bitpos:[30] ;default: 1'd0 ; */
40 /*description: digital core force no reset in deep sleep.*/
41 #define RTC_CNTL_DG_WRAP_FORCE_NORST    (BIT(30))
42 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
43 #define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
44 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
45 /* RTC_CNTL_DG_WRAP_FORCE_RST :  ;bitpos:[29] ;default: 1'd0 ; */
46 /*description: digital wrap force reset in deep sleep.*/
47 #define RTC_CNTL_DG_WRAP_FORCE_RST    (BIT(29))
48 #define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
49 #define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
50 #define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
51 /* RTC_CNTL_ANALOG_FORCE_NOISO :  ;bitpos:[28] ;default: 1'd1 ; */
52 /*description: Need add desc.*/
53 #define RTC_CNTL_ANALOG_FORCE_NOISO    (BIT(28))
54 #define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
55 #define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
56 #define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
57 /* RTC_CNTL_ANALOG_FORCE_ISO :  ;bitpos:[25] ;default: 1'd0 ; */
58 /*description: Need add desc.*/
59 #define RTC_CNTL_ANALOG_FORCE_ISO    (BIT(25))
60 #define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
61 #define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
62 #define RTC_CNTL_ANALOG_FORCE_ISO_S  25
63 /* RTC_CNTL_XTL_EXT_CTR_SEL :  ;bitpos:[22:20] ;default: 3'd0 ; */
64 /*description: Need add desc.*/
65 #define RTC_CNTL_XTL_EXT_CTR_SEL    0x00000007
66 #define RTC_CNTL_XTL_EXT_CTR_SEL_M  ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S))
67 #define RTC_CNTL_XTL_EXT_CTR_SEL_V  0x7
68 #define RTC_CNTL_XTL_EXT_CTR_SEL_S  20
69 /* RTC_CNTL_XTL_EN_WAIT :  ;bitpos:[17:14] ;default: 4'd2 ; */
70 /*description: wait bias_sleep and current source wakeup.*/
71 #define RTC_CNTL_XTL_EN_WAIT    0x0000000F
72 #define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
73 #define RTC_CNTL_XTL_EN_WAIT_V  0xF
74 #define RTC_CNTL_XTL_EN_WAIT_S  14
75 /* RTC_CNTL_XTL_FORCE_PU :  ;bitpos:[13] ;default: 1'd1 ; */
76 /*description: crystall force power up.*/
77 #define RTC_CNTL_XTL_FORCE_PU    (BIT(13))
78 #define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
79 #define RTC_CNTL_XTL_FORCE_PU_V  0x1
80 #define RTC_CNTL_XTL_FORCE_PU_S  13
81 /* RTC_CNTL_XTL_FORCE_PD :  ;bitpos:[12] ;default: 1'b0 ; */
82 /*description: crystall force power down.*/
83 #define RTC_CNTL_XTL_FORCE_PD    (BIT(12))
84 #define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
85 #define RTC_CNTL_XTL_FORCE_PD_V  0x1
86 #define RTC_CNTL_XTL_FORCE_PD_S  12
87 /* RTC_CNTL_BBPLL_FORCE_PU :  ;bitpos:[11] ;default: 1'd0 ; */
88 /*description: BB_PLL force power up.*/
89 #define RTC_CNTL_BBPLL_FORCE_PU    (BIT(11))
90 #define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
91 #define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
92 #define RTC_CNTL_BBPLL_FORCE_PU_S  11
93 /* RTC_CNTL_BBPLL_FORCE_PD :  ;bitpos:[10] ;default: 1'b0 ; */
94 /*description: BB_PLL force power down.*/
95 #define RTC_CNTL_BBPLL_FORCE_PD    (BIT(10))
96 #define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
97 #define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
98 #define RTC_CNTL_BBPLL_FORCE_PD_S  10
99 /* RTC_CNTL_BBPLL_I2C_FORCE_PU :  ;bitpos:[9] ;default: 1'd0 ; */
100 /*description: BB_PLL_I2C force power up.*/
101 #define RTC_CNTL_BBPLL_I2C_FORCE_PU    (BIT(9))
102 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
103 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
104 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
105 /* RTC_CNTL_BBPLL_I2C_FORCE_PD :  ;bitpos:[8] ;default: 1'b0 ; */
106 /*description: BB_PLL _I2C force power down.*/
107 #define RTC_CNTL_BBPLL_I2C_FORCE_PD    (BIT(8))
108 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
109 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
110 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
111 /* RTC_CNTL_BB_I2C_FORCE_PU :  ;bitpos:[7] ;default: 1'd0 ; */
112 /*description: BB_I2C force power up.*/
113 #define RTC_CNTL_BB_I2C_FORCE_PU    (BIT(7))
114 #define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
115 #define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
116 #define RTC_CNTL_BB_I2C_FORCE_PU_S  7
117 /* RTC_CNTL_BB_I2C_FORCE_PD :  ;bitpos:[6] ;default: 1'b0 ; */
118 /*description: BB_I2C force power down.*/
119 #define RTC_CNTL_BB_I2C_FORCE_PD    (BIT(6))
120 #define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
121 #define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
122 #define RTC_CNTL_BB_I2C_FORCE_PD_S  6
123 /* RTC_CNTL_SW_PROCPU_RST :  ;bitpos:[5] ;default: 1'b0 ; */
124 /*description: PRO CPU SW reset.*/
125 #define RTC_CNTL_SW_PROCPU_RST    (BIT(5))
126 #define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
127 #define RTC_CNTL_SW_PROCPU_RST_V  0x1
128 #define RTC_CNTL_SW_PROCPU_RST_S  5
129 /* RTC_CNTL_SW_STALL_PROCPU_C0 :  ;bitpos:[3:2] ;default: 2'b0 ; */
130 /*description: {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P
131 RO CPU.*/
132 #define RTC_CNTL_SW_STALL_PROCPU_C0    0x00000003
133 #define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
134 #define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
135 #define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
136 
137 #define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
138 /* RTC_CNTL_SLP_VAL_LO :  ;bitpos:[31:0] ;default: 32'h0 ; */
139 /*description: Need add desc.*/
140 #define RTC_CNTL_SLP_VAL_LO    0xFFFFFFFF
141 #define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
142 #define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
143 #define RTC_CNTL_SLP_VAL_LO_S  0
144 
145 #define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
146 /* RTC_CNTL_MAIN_TIMER_ALARM_EN :  ;bitpos:[16] ;default: 1'h0 ; */
147 /*description: timer alarm enable bit.*/
148 #define RTC_CNTL_MAIN_TIMER_ALARM_EN    (BIT(16))
149 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
150 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
151 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
152 /* RTC_CNTL_SLP_VAL_HI :  ;bitpos:[15:0] ;default: 16'h0 ; */
153 /*description: RTC sleep timer high 16 bits.*/
154 #define RTC_CNTL_SLP_VAL_HI    0x0000FFFF
155 #define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
156 #define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
157 #define RTC_CNTL_SLP_VAL_HI_S  0
158 
159 #define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xC)
160 /* RTC_CNTL_TIME_UPDATE :  ;bitpos:[31] ;default: 1'h0 ; */
161 /*description: Set 1: to update register with RTC timer.*/
162 #define RTC_CNTL_TIME_UPDATE    (BIT(31))
163 #define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
164 #define RTC_CNTL_TIME_UPDATE_V  0x1
165 #define RTC_CNTL_TIME_UPDATE_S  31
166 /* RTC_CNTL_TIMER_SYS_RST :  ;bitpos:[29] ;default: 1'b0 ; */
167 /*description: enable to record system reset time.*/
168 #define RTC_CNTL_TIMER_SYS_RST    (BIT(29))
169 #define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
170 #define RTC_CNTL_TIMER_SYS_RST_V  0x1
171 #define RTC_CNTL_TIMER_SYS_RST_S  29
172 /* RTC_CNTL_TIMER_XTL_OFF :  ;bitpos:[28] ;default: 1'b0 ; */
173 /*description: Enable to record 40M XTAL OFF time.*/
174 #define RTC_CNTL_TIMER_XTL_OFF    (BIT(28))
175 #define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
176 #define RTC_CNTL_TIMER_XTL_OFF_V  0x1
177 #define RTC_CNTL_TIMER_XTL_OFF_S  28
178 /* RTC_CNTL_TIMER_SYS_STALL :  ;bitpos:[27] ;default: 1'b0 ; */
179 /*description: Enable to record system stall time.*/
180 #define RTC_CNTL_TIMER_SYS_STALL    (BIT(27))
181 #define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
182 #define RTC_CNTL_TIMER_SYS_STALL_V  0x1
183 #define RTC_CNTL_TIMER_SYS_STALL_S  27
184 
185 #define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
186 /* RTC_CNTL_TIMER_VALUE0_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
187 /*description: RTC timer low 32 bits.*/
188 #define RTC_CNTL_TIMER_VALUE0_LOW    0xFFFFFFFF
189 #define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
190 #define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
191 #define RTC_CNTL_TIMER_VALUE0_LOW_S  0
192 
193 #define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x14)
194 /* RTC_CNTL_TIMER_VALUE0_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
195 /*description: RTC timer high 16 bits.*/
196 #define RTC_CNTL_TIMER_VALUE0_HIGH    0x0000FFFF
197 #define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
198 #define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
199 #define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
200 
201 #define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
202 /* RTC_CNTL_SLEEP_EN :  ;bitpos:[31] ;default: 1'd0 ; */
203 /*description: sleep enable bit.*/
204 #define RTC_CNTL_SLEEP_EN    (BIT(31))
205 #define RTC_CNTL_SLEEP_EN_M  (BIT(31))
206 #define RTC_CNTL_SLEEP_EN_V  0x1
207 #define RTC_CNTL_SLEEP_EN_S  31
208 /* RTC_CNTL_SLP_REJECT :  ;bitpos:[30] ;default: 1'd0 ; */
209 /*description: leep reject bit.*/
210 #define RTC_CNTL_SLP_REJECT    (BIT(30))
211 #define RTC_CNTL_SLP_REJECT_M  (BIT(30))
212 #define RTC_CNTL_SLP_REJECT_V  0x1
213 #define RTC_CNTL_SLP_REJECT_S  30
214 /* RTC_CNTL_SLP_WAKEUP :  ;bitpos:[29] ;default: 1'd0 ; */
215 /*description: leep wakeup bit.*/
216 #define RTC_CNTL_SLP_WAKEUP    (BIT(29))
217 #define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
218 #define RTC_CNTL_SLP_WAKEUP_V  0x1
219 #define RTC_CNTL_SLP_WAKEUP_S  29
220 /* RTC_CNTL_SDIO_ACTIVE_IND :  ;bitpos:[28] ;default: 1'd0 ; */
221 /*description: SDIO active indication.*/
222 #define RTC_CNTL_SDIO_ACTIVE_IND    (BIT(28))
223 #define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
224 #define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
225 #define RTC_CNTL_SDIO_ACTIVE_IND_S  28
226 /* RTC_CNTL_APB2RTC_BRIDGE_SEL :  ;bitpos:[22] ;default: 1'd0 ; */
227 /*description: 1: APB to RTC using bridge.*/
228 #define RTC_CNTL_APB2RTC_BRIDGE_SEL    (BIT(22))
229 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
230 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
231 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
232 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
233 /*description: clear rtc sleep reject cause.*/
234 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR    (BIT(1))
235 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
236 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
237 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
238 /* RTC_CNTL_SW_CPU_INT :  ;bitpos:[0] ;default: 1'b0 ; */
239 /*description: rtc software interrupt to main cpu.*/
240 #define RTC_CNTL_SW_CPU_INT    (BIT(0))
241 #define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
242 #define RTC_CNTL_SW_CPU_INT_V  0x1
243 #define RTC_CNTL_SW_CPU_INT_S  0
244 
245 #define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1C)
246 /* RTC_CNTL_PLL_BUF_WAIT :  ;bitpos:[31:24] ;default: 8'd40 ; */
247 /*description: PLL wait cycles in slow_clk_rtc.*/
248 #define RTC_CNTL_PLL_BUF_WAIT    0x000000FF
249 #define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
250 #define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
251 #define RTC_CNTL_PLL_BUF_WAIT_S  24
252 /* RTC_CNTL_XTL_BUF_WAIT :  ;bitpos:[23:14] ;default: 10'd80 ; */
253 /*description: XTAL wait cycles in slow_clk_rtc.*/
254 #define RTC_CNTL_XTL_BUF_WAIT    0x000003FF
255 #define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
256 #define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
257 #define RTC_CNTL_XTL_BUF_WAIT_S  14
258 /* RTC_CNTL_CK8M_WAIT :  ;bitpos:[13:6] ;default: 8'h10 ; */
259 /*description: CK8M wait cycles in slow_clk_rtc.*/
260 #define RTC_CNTL_CK8M_WAIT    0x000000FF
261 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
262 #define RTC_CNTL_CK8M_WAIT_V  0xFF
263 #define RTC_CNTL_CK8M_WAIT_S  6
264 /* RTC_CNTL_CPU_STALL_WAIT :  ;bitpos:[5:1] ;default: 5'd1 ; */
265 /*description: CPU stall wait cycles in fast_clk_rtc.*/
266 #define RTC_CNTL_CPU_STALL_WAIT    0x0000001F
267 #define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
268 #define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
269 #define RTC_CNTL_CPU_STALL_WAIT_S  1
270 /* RTC_CNTL_CPU_STALL_EN :  ;bitpos:[0] ;default: 1'd1 ; */
271 /*description: CPU stall enable bit.*/
272 #define RTC_CNTL_CPU_STALL_EN    (BIT(0))
273 #define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
274 #define RTC_CNTL_CPU_STALL_EN_V  0x1
275 #define RTC_CNTL_CPU_STALL_EN_S  0
276 
277 #define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
278 /* RTC_CNTL_MIN_TIME_CK8M_OFF :  ;bitpos:[31:24] ;default: 8'h1 ; */
279 /*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/
280 #define RTC_CNTL_MIN_TIME_CK8M_OFF    0x000000FF
281 #define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
282 #define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
283 #define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
284 
285 #define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x24)
286 /* RTC_CNTL_DG_WRAP_POWERUP_TIMER :  ;bitpos:[31:25] ;default: 7'h8 ; */
287 /*description: Need add desc.*/
288 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER    0x0000007F
289 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
290 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
291 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
292 /* RTC_CNTL_DG_WRAP_WAIT_TIMER :  ;bitpos:[24:16] ;default: 9'h20 ; */
293 /*description: Need add desc.*/
294 #define RTC_CNTL_DG_WRAP_WAIT_TIMER    0x000001FF
295 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
296 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
297 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
298 
299 #define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x28)
300 /* RTC_CNTL_MIN_SLP_VAL :  ;bitpos:[15:8] ;default: 8'h80 ; */
301 /*description: minimal sleep cycles in slow_clk_rtc.*/
302 #define RTC_CNTL_MIN_SLP_VAL    0x000000FF
303 #define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
304 #define RTC_CNTL_MIN_SLP_VAL_V  0xFF
305 #define RTC_CNTL_MIN_SLP_VAL_S  8
306 
307 #define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x2C)
308 /* RTC_CNTL_PLL_I2C_PU :  ;bitpos:[31] ;default: 1'd0 ; */
309 /*description: Need add desc.*/
310 #define RTC_CNTL_PLL_I2C_PU    (BIT(31))
311 #define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
312 #define RTC_CNTL_PLL_I2C_PU_V  0x1
313 #define RTC_CNTL_PLL_I2C_PU_S  31
314 /* RTC_CNTL_CKGEN_I2C_PU :  ;bitpos:[30] ;default: 1'd0 ; */
315 /*description: 1: CKGEN_I2C power up.*/
316 #define RTC_CNTL_CKGEN_I2C_PU    (BIT(30))
317 #define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
318 #define RTC_CNTL_CKGEN_I2C_PU_V  0x1
319 #define RTC_CNTL_CKGEN_I2C_PU_S  30
320 /* RTC_CNTL_RFRX_PBUS_PU :  ;bitpos:[28] ;default: 1'd0 ; */
321 /*description: 1: RFRX_PBUS power up.*/
322 #define RTC_CNTL_RFRX_PBUS_PU    (BIT(28))
323 #define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
324 #define RTC_CNTL_RFRX_PBUS_PU_V  0x1
325 #define RTC_CNTL_RFRX_PBUS_PU_S  28
326 /* RTC_CNTL_TXRF_I2C_PU :  ;bitpos:[27] ;default: 1'd0 ; */
327 /*description: 1: TXRF_I2C power up.*/
328 #define RTC_CNTL_TXRF_I2C_PU    (BIT(27))
329 #define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
330 #define RTC_CNTL_TXRF_I2C_PU_V  0x1
331 #define RTC_CNTL_TXRF_I2C_PU_S  27
332 /* RTC_CNTL_BBPLL_CAL_SLP_START :  ;bitpos:[25] ;default: 1'b0 ; */
333 /*description: start BBPLL calibration during sleep.*/
334 #define RTC_CNTL_BBPLL_CAL_SLP_START    (BIT(25))
335 #define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
336 #define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
337 #define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
338 /* RTC_CNTL_SAR_I2C_PU :  ;bitpos:[22] ;default: 1'b1 ; */
339 /*description: PLLA force power up.*/
340 #define RTC_CNTL_SAR_I2C_PU    (BIT(22))
341 #define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
342 #define RTC_CNTL_SAR_I2C_PU_V  0x1
343 #define RTC_CNTL_SAR_I2C_PU_S  22
344 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU :  ;bitpos:[19] ;default: 1'b0 ; */
345 /*description: Need add desc.*/
346 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU    (BIT(19))
347 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
348 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
349 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
350 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD :  ;bitpos:[18] ;default: 1'b1 ; */
351 /*description: Need add desc.*/
352 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD    (BIT(18))
353 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
354 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
355 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
356 
357 #define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x30)
358 /* RTC_CNTL_DRESET_MASK_PROCPU :  ;bitpos:[20] ;default: 1'b0 ; */
359 /*description: Need add desc.*/
360 #define RTC_CNTL_DRESET_MASK_PROCPU    (BIT(20))
361 #define RTC_CNTL_DRESET_MASK_PROCPU_M  (BIT(20))
362 #define RTC_CNTL_DRESET_MASK_PROCPU_V  0x1
363 #define RTC_CNTL_DRESET_MASK_PROCPU_S  20
364 /* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU :  ;bitpos:[19] ;default: 1'b0 ; */
365 /*description: PROCPU OcdHaltOnReset.*/
366 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU    (BIT(19))
367 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M  (BIT(19))
368 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V  0x1
369 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S  19
370 /* RTC_CNTL_STAT_VECTOR_SEL_PROCPU :  ;bitpos:[13] ;default: 1'b1 ; */
371 /*description: PRO CPU state vector sel.*/
372 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU    (BIT(13))
373 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M  (BIT(13))
374 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V  0x1
375 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S  13
376 /* RTC_CNTL_RESET_CAUSE_PROCPU :  ;bitpos:[5:0] ;default: 0 ; */
377 /*description: reset cause of PRO CPU.*/
378 #define RTC_CNTL_RESET_CAUSE_PROCPU    0x0000003F
379 #define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
380 #define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
381 #define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
382 
383 #define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x34)
384 /* RTC_CNTL_WAKEUP_ENA :  ;bitpos:[31:15] ;default: 17'b1100 ; */
385 /*description: wakeup enable bitmap.*/
386 #define RTC_CNTL_WAKEUP_ENA    0x0001FFFF
387 #define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
388 #define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
389 #define RTC_CNTL_WAKEUP_ENA_S  15
390 
391 #define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x38)
392 /* RTC_CNTL_BBPLL_CAL_INT_ENA : BIT ;bitpos:[20] ;default: 1'b0 ; */
393 /*description: Need add desc.*/
394 #define RTC_CNTL_BBPLL_CAL_INT_ENA    (BIT(20))
395 #define RTC_CNTL_BBPLL_CAL_INT_ENA_M  (BIT(20))
396 #define RTC_CNTL_BBPLL_CAL_INT_ENA_V  0x1
397 #define RTC_CNTL_BBPLL_CAL_INT_ENA_S  20
398 /* RTC_CNTL_SWD_INT_ENA : BIT ;bitpos:[15] ;default: 1'b0 ; */
399 /*description: enable super watch dog interrupt.*/
400 #define RTC_CNTL_SWD_INT_ENA    (BIT(15))
401 #define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
402 #define RTC_CNTL_SWD_INT_ENA_V  0x1
403 #define RTC_CNTL_SWD_INT_ENA_S  15
404 /* RTC_CNTL_MAIN_TIMER_INT_ENA : BIT ;bitpos:[10] ;default: 1'b0 ; */
405 /*description: enable RTC main timer interrupt.*/
406 #define RTC_CNTL_MAIN_TIMER_INT_ENA    (BIT(10))
407 #define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
408 #define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
409 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
410 /* RTC_CNTL_BROWN_OUT_INT_ENA : BIT ;bitpos:[9] ;default: 1'b0 ; */
411 /*description: enable brown out interrupt.*/
412 #define RTC_CNTL_BROWN_OUT_INT_ENA    (BIT(9))
413 #define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
414 #define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
415 #define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
416 /* RTC_CNTL_WDT_INT_ENA : BIT ;bitpos:[3] ;default: 1'b0 ; */
417 /*description: enable RTC WDT interrupt.*/
418 #define RTC_CNTL_WDT_INT_ENA    (BIT(3))
419 #define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
420 #define RTC_CNTL_WDT_INT_ENA_V  0x1
421 #define RTC_CNTL_WDT_INT_ENA_S  3
422 /* RTC_CNTL_SLP_REJECT_INT_ENA : BIT ;bitpos:[1] ;default: 1'b0 ; */
423 /*description: enable sleep reject interrupt.*/
424 #define RTC_CNTL_SLP_REJECT_INT_ENA    (BIT(1))
425 #define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
426 #define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
427 #define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
428 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : BIT ;bitpos:[0] ;default: 1'b0 ; */
429 /*description: enable sleep wakeup interrupt.*/
430 #define RTC_CNTL_SLP_WAKEUP_INT_ENA    (BIT(0))
431 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
432 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
433 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
434 
435 #define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x3C)
436 /* RTC_CNTL_BBPLL_CAL_INT_RAW :  ;bitpos:[20] ;default: 1'b0 ; */
437 /*description: Need add desc.*/
438 #define RTC_CNTL_BBPLL_CAL_INT_RAW    (BIT(20))
439 #define RTC_CNTL_BBPLL_CAL_INT_RAW_M  (BIT(20))
440 #define RTC_CNTL_BBPLL_CAL_INT_RAW_V  0x1
441 #define RTC_CNTL_BBPLL_CAL_INT_RAW_S  20
442 /* RTC_CNTL_SWD_INT_RAW :  ;bitpos:[15] ;default: 1'b0 ; */
443 /*description: super watch dog interrupt raw.*/
444 #define RTC_CNTL_SWD_INT_RAW    (BIT(15))
445 #define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
446 #define RTC_CNTL_SWD_INT_RAW_V  0x1
447 #define RTC_CNTL_SWD_INT_RAW_S  15
448 /* RTC_CNTL_MAIN_TIMER_INT_RAW :  ;bitpos:[10] ;default: 1'b0 ; */
449 /*description: RTC main timer interrupt raw.*/
450 #define RTC_CNTL_MAIN_TIMER_INT_RAW    (BIT(10))
451 #define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
452 #define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
453 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
454 /* RTC_CNTL_BROWN_OUT_INT_RAW :  ;bitpos:[9] ;default: 1'b0 ; */
455 /*description: brown out interrupt raw.*/
456 #define RTC_CNTL_BROWN_OUT_INT_RAW    (BIT(9))
457 #define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
458 #define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
459 #define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
460 /* RTC_CNTL_WDT_INT_RAW :  ;bitpos:[3] ;default: 1'b0 ; */
461 /*description: RTC WDT interrupt raw.*/
462 #define RTC_CNTL_WDT_INT_RAW    (BIT(3))
463 #define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
464 #define RTC_CNTL_WDT_INT_RAW_V  0x1
465 #define RTC_CNTL_WDT_INT_RAW_S  3
466 /* RTC_CNTL_SLP_REJECT_INT_RAW :  ;bitpos:[1] ;default: 1'b0 ; */
467 /*description: sleep reject interrupt raw.*/
468 #define RTC_CNTL_SLP_REJECT_INT_RAW    (BIT(1))
469 #define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
470 #define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
471 #define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
472 /* RTC_CNTL_SLP_WAKEUP_INT_RAW :  ;bitpos:[0] ;default: 1'b0 ; */
473 /*description: sleep wakeup interrupt raw.*/
474 #define RTC_CNTL_SLP_WAKEUP_INT_RAW    (BIT(0))
475 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
476 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
477 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
478 
479 #define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x40)
480 /* RTC_CNTL_BBPLL_CAL_INT_ST :  ;bitpos:[20] ;default: 1'b0 ; */
481 /*description: Need add desc.*/
482 #define RTC_CNTL_BBPLL_CAL_INT_ST    (BIT(20))
483 #define RTC_CNTL_BBPLL_CAL_INT_ST_M  (BIT(20))
484 #define RTC_CNTL_BBPLL_CAL_INT_ST_V  0x1
485 #define RTC_CNTL_BBPLL_CAL_INT_ST_S  20
486 /* RTC_CNTL_SWD_INT_ST :  ;bitpos:[15] ;default: 1'b0 ; */
487 /*description: super watch dog interrupt state.*/
488 #define RTC_CNTL_SWD_INT_ST    (BIT(15))
489 #define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
490 #define RTC_CNTL_SWD_INT_ST_V  0x1
491 #define RTC_CNTL_SWD_INT_ST_S  15
492 /* RTC_CNTL_MAIN_TIMER_INT_ST :  ;bitpos:[10] ;default: 1'b0 ; */
493 /*description: RTC main timer interrupt state.*/
494 #define RTC_CNTL_MAIN_TIMER_INT_ST    (BIT(10))
495 #define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
496 #define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
497 #define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
498 /* RTC_CNTL_BROWN_OUT_INT_ST :  ;bitpos:[9] ;default: 1'b0 ; */
499 /*description: brown out interrupt state.*/
500 #define RTC_CNTL_BROWN_OUT_INT_ST    (BIT(9))
501 #define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
502 #define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
503 #define RTC_CNTL_BROWN_OUT_INT_ST_S  9
504 /* RTC_CNTL_WDT_INT_ST :  ;bitpos:[3] ;default: 1'b0 ; */
505 /*description: RTC WDT interrupt state.*/
506 #define RTC_CNTL_WDT_INT_ST    (BIT(3))
507 #define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
508 #define RTC_CNTL_WDT_INT_ST_V  0x1
509 #define RTC_CNTL_WDT_INT_ST_S  3
510 /* RTC_CNTL_SLP_REJECT_INT_ST :  ;bitpos:[1] ;default: 1'b0 ; */
511 /*description: sleep reject interrupt state.*/
512 #define RTC_CNTL_SLP_REJECT_INT_ST    (BIT(1))
513 #define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
514 #define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
515 #define RTC_CNTL_SLP_REJECT_INT_ST_S  1
516 /* RTC_CNTL_SLP_WAKEUP_INT_ST :  ;bitpos:[0] ;default: 1'b0 ; */
517 /*description: sleep wakeup interrupt state.*/
518 #define RTC_CNTL_SLP_WAKEUP_INT_ST    (BIT(0))
519 #define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
520 #define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
521 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
522 
523 #define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x44)
524 /* RTC_CNTL_BBPLL_CAL_INT_CLR :  ;bitpos:[20] ;default: 1'b0 ; */
525 /*description: Need add desc.*/
526 #define RTC_CNTL_BBPLL_CAL_INT_CLR    (BIT(20))
527 #define RTC_CNTL_BBPLL_CAL_INT_CLR_M  (BIT(20))
528 #define RTC_CNTL_BBPLL_CAL_INT_CLR_V  0x1
529 #define RTC_CNTL_BBPLL_CAL_INT_CLR_S  20
530 /* RTC_CNTL_SWD_INT_CLR :  ;bitpos:[15] ;default: 1'b0 ; */
531 /*description: Clear super watch dog interrupt state.*/
532 #define RTC_CNTL_SWD_INT_CLR    (BIT(15))
533 #define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
534 #define RTC_CNTL_SWD_INT_CLR_V  0x1
535 #define RTC_CNTL_SWD_INT_CLR_S  15
536 /* RTC_CNTL_MAIN_TIMER_INT_CLR :  ;bitpos:[10] ;default: 1'b0 ; */
537 /*description: Clear RTC main timer interrupt state.*/
538 #define RTC_CNTL_MAIN_TIMER_INT_CLR    (BIT(10))
539 #define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
540 #define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
541 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
542 /* RTC_CNTL_BROWN_OUT_INT_CLR :  ;bitpos:[9] ;default: 1'b0 ; */
543 /*description: Clear brown out interrupt state.*/
544 #define RTC_CNTL_BROWN_OUT_INT_CLR    (BIT(9))
545 #define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
546 #define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
547 #define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
548 /* RTC_CNTL_WDT_INT_CLR :  ;bitpos:[3] ;default: 1'b0 ; */
549 /*description: Clear RTC WDT interrupt state.*/
550 #define RTC_CNTL_WDT_INT_CLR    (BIT(3))
551 #define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
552 #define RTC_CNTL_WDT_INT_CLR_V  0x1
553 #define RTC_CNTL_WDT_INT_CLR_S  3
554 /* RTC_CNTL_SLP_REJECT_INT_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
555 /*description: Clear sleep reject interrupt state.*/
556 #define RTC_CNTL_SLP_REJECT_INT_CLR    (BIT(1))
557 #define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
558 #define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
559 #define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
560 /* RTC_CNTL_SLP_WAKEUP_INT_CLR :  ;bitpos:[0] ;default: 1'b0 ; */
561 /*description: Clear sleep wakeup interrupt state.*/
562 #define RTC_CNTL_SLP_WAKEUP_INT_CLR    (BIT(0))
563 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
564 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
565 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
566 
567 #define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x48)
568 /* RTC_CNTL_SCRATCH0 :  ;bitpos:[31:0] ;default: 0 ; */
569 /*description: Need add desc.*/
570 #define RTC_CNTL_SCRATCH0    0xFFFFFFFF
571 #define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
572 #define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
573 #define RTC_CNTL_SCRATCH0_S  0
574 
575 #define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x4C)
576 /* RTC_CNTL_SCRATCH1 :  ;bitpos:[31:0] ;default: 0 ; */
577 /*description: Need add desc.*/
578 #define RTC_CNTL_SCRATCH1    0xFFFFFFFF
579 #define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
580 #define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
581 #define RTC_CNTL_SCRATCH1_S  0
582 
583 #define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x50)
584 /* RTC_CNTL_SCRATCH2 :  ;bitpos:[31:0] ;default: 0 ; */
585 /*description: Need add desc.*/
586 #define RTC_CNTL_SCRATCH2    0xFFFFFFFF
587 #define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
588 #define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
589 #define RTC_CNTL_SCRATCH2_S  0
590 
591 #define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x54)
592 /* RTC_CNTL_SCRATCH3 :  ;bitpos:[31:0] ;default: 0 ; */
593 /*description: Need add desc.*/
594 #define RTC_CNTL_SCRATCH3    0xFFFFFFFF
595 #define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
596 #define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
597 #define RTC_CNTL_SCRATCH3_S  0
598 
599 #define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x58)
600 /* RTC_CNTL_XTL_EXT_CTR_EN :  ;bitpos:[31] ;default: 1'b0 ; */
601 /*description: Need add desc.*/
602 #define RTC_CNTL_XTL_EXT_CTR_EN    (BIT(31))
603 #define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
604 #define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
605 #define RTC_CNTL_XTL_EXT_CTR_EN_S  31
606 /* RTC_CNTL_XTL_EXT_CTR_LV :  ;bitpos:[30] ;default: 1'b0 ; */
607 /*description: 0: power down XTAL at high level.*/
608 #define RTC_CNTL_XTL_EXT_CTR_LV    (BIT(30))
609 #define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
610 #define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
611 #define RTC_CNTL_XTL_EXT_CTR_LV_S  30
612 
613 #define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x5C)
614 /* RTC_CNTL_GPIO_WAKEUP_FILTER :  ;bitpos:[31] ;default: 1'b0 ; */
615 /*description: enable filter for gpio wakeup event.*/
616 #define RTC_CNTL_GPIO_WAKEUP_FILTER    (BIT(31))
617 #define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(31))
618 #define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
619 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S  31
620 
621 #define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
622 /* RTC_CNTL_DEEP_SLP_REJECT_EN :  ;bitpos:[31] ;default: 1'b0 ; */
623 /*description: enable reject for deep sleep.*/
624 #define RTC_CNTL_DEEP_SLP_REJECT_EN    (BIT(31))
625 #define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
626 #define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
627 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
628 /* RTC_CNTL_LIGHT_SLP_REJECT_EN :  ;bitpos:[30] ;default: 1'b0 ; */
629 /*description: enable reject for light sleep.*/
630 #define RTC_CNTL_LIGHT_SLP_REJECT_EN    (BIT(30))
631 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
632 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
633 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
634 /* RTC_CNTL_SLEEP_REJECT_ENA :  ;bitpos:[29:12] ;default: 17'd0 ; */
635 /*description: sleep reject enable.*/
636 #define RTC_CNTL_SLEEP_REJECT_ENA    0x0003FFFF
637 #define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
638 #define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
639 #define RTC_CNTL_SLEEP_REJECT_ENA_S  12
640 
641 #define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
642 /* RTC_CNTL_CPUPERIOD_SEL :  ;bitpos:[31:30] ;default: 2'b00 ; */
643 /*description: Need add desc.*/
644 #define RTC_CNTL_CPUPERIOD_SEL    0x00000003
645 #define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
646 #define RTC_CNTL_CPUPERIOD_SEL_V  0x3
647 #define RTC_CNTL_CPUPERIOD_SEL_S  30
648 /* RTC_CNTL_CPUSEL_CONF :  ;bitpos:[29] ;default: 1'b0 ; */
649 /*description: CPU sel option.*/
650 #define RTC_CNTL_CPUSEL_CONF    (BIT(29))
651 #define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
652 #define RTC_CNTL_CPUSEL_CONF_V  0x1
653 #define RTC_CNTL_CPUSEL_CONF_S  29
654 
655 #define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
656 /* RTC_CNTL_ANA_CLK_RTC_SEL :  ;bitpos:[31:30] ;default: 2'd0 ; */
657 /*description: Need add desc.*/
658 #define RTC_CNTL_ANA_CLK_RTC_SEL    0x00000003
659 #define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
660 #define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
661 #define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
662 /* RTC_CNTL_FAST_CLK_RTC_SEL :  ;bitpos:[29] ;default: 1'b0 ; */
663 /*description: fast_clk_rtc sel. 0: XTAL div 2.*/
664 #define RTC_CNTL_FAST_CLK_RTC_SEL    (BIT(29))
665 #define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
666 #define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
667 #define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
668 /* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING :  ;bitpos:[28] ;default: 1'b1 ; */
669 /*description: Need add desc.*/
670 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING    (BIT(28))
671 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
672 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
673 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
674 /* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING :  ;bitpos:[27] ;default: 1'b0 ; */
675 /*description: Need add desc.*/
676 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING    (BIT(27))
677 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
678 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
679 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
680 /* RTC_CNTL_CK8M_FORCE_PU :  ;bitpos:[26] ;default: 1'd0 ; */
681 /*description: CK8M force power up.*/
682 #define RTC_CNTL_CK8M_FORCE_PU    (BIT(26))
683 #define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
684 #define RTC_CNTL_CK8M_FORCE_PU_V  0x1
685 #define RTC_CNTL_CK8M_FORCE_PU_S  26
686 /* RTC_CNTL_CK8M_FORCE_PD :  ;bitpos:[25] ;default: 1'd0 ; */
687 /*description: CK8M force power down.*/
688 #define RTC_CNTL_CK8M_FORCE_PD    (BIT(25))
689 #define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
690 #define RTC_CNTL_CK8M_FORCE_PD_V  0x1
691 #define RTC_CNTL_CK8M_FORCE_PD_S  25
692 /* RTC_CNTL_CK8M_DFREQ :  ;bitpos:[24:17] ;default: 8'd172 ; */
693 /*description: CK8M_DFREQ.*/
694 #define RTC_CNTL_CK8M_DFREQ    0x000000FF
695 #define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
696 #define RTC_CNTL_CK8M_DFREQ_V  0xFF
697 #define RTC_CNTL_CK8M_DFREQ_S  17
698 /* RTC_CNTL_CK8M_FORCE_NOGATING :  ;bitpos:[16] ;default: 1'd0 ; */
699 /*description: CK8M force no gating during sleep.*/
700 #define RTC_CNTL_CK8M_FORCE_NOGATING    (BIT(16))
701 #define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
702 #define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
703 #define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
704 /* RTC_CNTL_XTAL_FORCE_NOGATING :  ;bitpos:[15] ;default: 1'd0 ; */
705 /*description: XTAL force no gating during sleep.*/
706 #define RTC_CNTL_XTAL_FORCE_NOGATING    (BIT(15))
707 #define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
708 #define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
709 #define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
710 /* RTC_CNTL_CK8M_DIV_SEL :  ;bitpos:[14:12] ;default: 3'd3 ; */
711 /*description: divider = reg_ck8m_div_sel + 1.*/
712 #define RTC_CNTL_CK8M_DIV_SEL    0x00000007
713 #define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
714 #define RTC_CNTL_CK8M_DIV_SEL_V  0x7
715 #define RTC_CNTL_CK8M_DIV_SEL_S  12
716 /* RTC_CNTL_DIG_CLK8M_EN :  ;bitpos:[10] ;default: 1'd0 ; */
717 /*description: enable CK8M for digital core (no relationship with RTC core).*/
718 #define RTC_CNTL_DIG_CLK8M_EN    (BIT(10))
719 #define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
720 #define RTC_CNTL_DIG_CLK8M_EN_V  0x1
721 #define RTC_CNTL_DIG_CLK8M_EN_S  10
722 /* RTC_CNTL_DIG_CLK8M_D256_EN :  ;bitpos:[9] ;default: 1'd1 ; */
723 /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/
724 #define RTC_CNTL_DIG_CLK8M_D256_EN    (BIT(9))
725 #define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
726 #define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
727 #define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
728 /* RTC_CNTL_DIG_XTAL32K_EN :  ;bitpos:[8] ;default: 1'd0 ; */
729 /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/
730 #define RTC_CNTL_DIG_XTAL32K_EN    (BIT(8))
731 #define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
732 #define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
733 #define RTC_CNTL_DIG_XTAL32K_EN_S  8
734 /* RTC_CNTL_ENB_CK8M_DIV :  ;bitpos:[7] ;default: 1'd0 ; */
735 /*description: 1: CK8M_D256_OUT is actually CK8M.*/
736 #define RTC_CNTL_ENB_CK8M_DIV    (BIT(7))
737 #define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
738 #define RTC_CNTL_ENB_CK8M_DIV_V  0x1
739 #define RTC_CNTL_ENB_CK8M_DIV_S  7
740 /* RTC_CNTL_ENB_CK8M :  ;bitpos:[6] ;default: 1'd0 ; */
741 /*description: disable CK8M and CK8M_D256_OUT.*/
742 #define RTC_CNTL_ENB_CK8M    (BIT(6))
743 #define RTC_CNTL_ENB_CK8M_M  (BIT(6))
744 #define RTC_CNTL_ENB_CK8M_V  0x1
745 #define RTC_CNTL_ENB_CK8M_S  6
746 /* RTC_CNTL_CK8M_DIV :  ;bitpos:[5:4] ;default: 2'b01 ; */
747 /*description: CK8M_D256_OUT divider. 00: div128.*/
748 #define RTC_CNTL_CK8M_DIV    0x00000003
749 #define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
750 #define RTC_CNTL_CK8M_DIV_V  0x3
751 #define RTC_CNTL_CK8M_DIV_S  4
752 /* RTC_CNTL_CK8M_DIV_SEL_VLD :  ;bitpos:[3] ;default: 1'b1 ; */
753 /*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/
754 #define RTC_CNTL_CK8M_DIV_SEL_VLD    (BIT(3))
755 #define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
756 #define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
757 #define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
758 /* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING :  ;bitpos:[2] ;default: 1'b0 ; */
759 /*description: Need add desc.*/
760 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING    (BIT(2))
761 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
762 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
763 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
764 /* RTC_CNTL_EFUSE_CLK_FORCE_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
765 /*description: Need add desc.*/
766 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING    (BIT(1))
767 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
768 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
769 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
770 
771 #define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6C)
772 /* RTC_CNTL_SLOW_CLK_NEXT_EDGE :  ;bitpos:[31] ;default: 1'b0 ; */
773 /*description: Need add desc.*/
774 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE    (BIT(31))
775 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
776 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
777 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
778 /* RTC_CNTL_ANA_CLK_DIV :  ;bitpos:[30:23] ;default: 8'd0 ; */
779 /*description: Need add desc.*/
780 #define RTC_CNTL_ANA_CLK_DIV    0x000000FF
781 #define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
782 #define RTC_CNTL_ANA_CLK_DIV_V  0xFF
783 #define RTC_CNTL_ANA_CLK_DIV_S  23
784 /* RTC_CNTL_ANA_CLK_DIV_VLD :  ;bitpos:[22] ;default: 1'b1 ; */
785 /*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/
786 #define RTC_CNTL_ANA_CLK_DIV_VLD    (BIT(22))
787 #define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
788 #define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
789 #define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
790 
791 #define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
792 /* RTC_CNTL_DBG_ATTEN_ACTIVE :  ;bitpos:[29:26] ;default: 4'd0 ; */
793 /*description: Need add desc.*/
794 #define RTC_CNTL_DBG_ATTEN_ACTIVE    0x0000000F
795 #define RTC_CNTL_DBG_ATTEN_ACTIVE_M  ((RTC_CNTL_DBG_ATTEN_ACTIVE_V)<<(RTC_CNTL_DBG_ATTEN_ACTIVE_S))
796 #define RTC_CNTL_DBG_ATTEN_ACTIVE_V  0xF
797 #define RTC_CNTL_DBG_ATTEN_ACTIVE_S  26
798 /* RTC_CNTL_DBG_ATTEN_MONITOR :  ;bitpos:[25:22] ;default: 4'd0 ; */
799 /*description: DBG_ATTEN when rtc in active state.*/
800 #define RTC_CNTL_DBG_ATTEN_MONITOR    0x0000000F
801 #define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
802 #define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
803 #define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
804 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP :  ;bitpos:[21:18] ;default: 4'd0 ; */
805 /*description: DBG_ATTEN when rtc in sleep state.*/
806 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP    0x0000000F
807 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
808 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
809 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
810 /* RTC_CNTL_BIAS_SLEEP_MONITOR :  ;bitpos:[17] ;default: 1'b0 ; */
811 /*description: bias_sleep when rtc in monitor state.*/
812 #define RTC_CNTL_BIAS_SLEEP_MONITOR    (BIT(17))
813 #define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
814 #define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
815 #define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
816 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP :  ;bitpos:[16] ;default: 1'b1 ; */
817 /*description: bias_sleep when rtc in sleep_state.*/
818 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP    (BIT(16))
819 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
820 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
821 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
822 /* RTC_CNTL_PD_CUR_MONITOR :  ;bitpos:[15] ;default: 1'b0 ; */
823 /*description: xpd cur when rtc in monitor state.*/
824 #define RTC_CNTL_PD_CUR_MONITOR    (BIT(15))
825 #define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
826 #define RTC_CNTL_PD_CUR_MONITOR_V  0x1
827 #define RTC_CNTL_PD_CUR_MONITOR_S  15
828 /* RTC_CNTL_PD_CUR_DEEP_SLP :  ;bitpos:[14] ;default: 1'b0 ; */
829 /*description: xpd cur when rtc in sleep_state.*/
830 #define RTC_CNTL_PD_CUR_DEEP_SLP    (BIT(14))
831 #define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
832 #define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
833 #define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
834 /* RTC_CNTL_BIAS_BUF_MONITOR :  ;bitpos:[13] ;default: 1'b0 ; */
835 /*description: Need add desc.*/
836 #define RTC_CNTL_BIAS_BUF_MONITOR    (BIT(13))
837 #define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
838 #define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
839 #define RTC_CNTL_BIAS_BUF_MONITOR_S  13
840 /* RTC_CNTL_BIAS_BUF_DEEP_SLP :  ;bitpos:[12] ;default: 1'b0 ; */
841 /*description: Need add desc.*/
842 #define RTC_CNTL_BIAS_BUF_DEEP_SLP    (BIT(12))
843 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
844 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
845 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
846 /* RTC_CNTL_BIAS_BUF_WAKE :  ;bitpos:[11] ;default: 1'b1 ; */
847 /*description: Need add desc.*/
848 #define RTC_CNTL_BIAS_BUF_WAKE    (BIT(11))
849 #define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
850 #define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
851 #define RTC_CNTL_BIAS_BUF_WAKE_S  11
852 /* RTC_CNTL_BIAS_BUF_IDLE :  ;bitpos:[10] ;default: 1'b0 ; */
853 /*description: Need add desc.*/
854 #define RTC_CNTL_BIAS_BUF_IDLE    (BIT(10))
855 #define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
856 #define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
857 #define RTC_CNTL_BIAS_BUF_IDLE_S  10
858 /* RTC_CNTL_DG_VDD_DRV_B_SLP_EN :  ;bitpos:[8] ;default: 1'b0 ; */
859 /*description: Need add desc.*/
860 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN    (BIT(8))
861 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M  (BIT(8))
862 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V  0x1
863 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S  8
864 /* RTC_CNTL_DG_VDD_DRV_B_SLP :  ;bitpos:[7:0] ;default: 8'h0 ; */
865 /*description: Need add desc.*/
866 #define RTC_CNTL_DG_VDD_DRV_B_SLP    0x000000FF
867 #define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
868 #define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
869 #define RTC_CNTL_DG_VDD_DRV_B_SLP_S  0
870 
871 #define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x74)
872 /* RTC_CNTL_REGULATOR_FORCE_PU :  ;bitpos:[31] ;default: 1'd1 ; */
873 /*description: Need add desc.*/
874 #define RTC_CNTL_REGULATOR_FORCE_PU    (BIT(31))
875 #define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
876 #define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
877 #define RTC_CNTL_REGULATOR_FORCE_PU_S  31
878 /* RTC_CNTL_REGULATOR_FORCE_PD :  ;bitpos:[30] ;default: 1'd0 ; */
879 /*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0
880 .8v or lower ).*/
881 #define RTC_CNTL_REGULATOR_FORCE_PD    (BIT(30))
882 #define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
883 #define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
884 #define RTC_CNTL_REGULATOR_FORCE_PD_S  30
885 /* RTC_CNTL_SCK_DCAP :  ;bitpos:[21:14] ;default: 8'd0 ; */
886 /*description: SCK_DCAP.*/
887 #define RTC_CNTL_SCK_DCAP    0x000000FF
888 #define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
889 #define RTC_CNTL_SCK_DCAP_V  0xFF
890 #define RTC_CNTL_SCK_DCAP_S  14
891 /* RTC_CNTL_DIG_REG_CAL_EN :  ;bitpos:[7] ;default: 1'b0 ; */
892 /*description: Need add desc.*/
893 #define RTC_CNTL_DIG_REG_CAL_EN    (BIT(7))
894 #define RTC_CNTL_DIG_REG_CAL_EN_M  (BIT(7))
895 #define RTC_CNTL_DIG_REG_CAL_EN_V  0x1
896 #define RTC_CNTL_DIG_REG_CAL_EN_S  7
897 
898 #define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x78)
899 /* RTC_CNTL_PAD_FORCE_HOLD :  ;bitpos:[21] ;default: 1'd0 ; */
900 /*description: rtc pad force hold.*/
901 #define RTC_CNTL_PAD_FORCE_HOLD    (BIT(21))
902 #define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
903 #define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
904 #define RTC_CNTL_PAD_FORCE_HOLD_S  21
905 
906 #define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x7C)
907 /* RTC_CNTL_DG_WRAP_PD_EN :  ;bitpos:[31] ;default: 1'b0 ; */
908 /*description: Need add desc.*/
909 #define RTC_CNTL_DG_WRAP_PD_EN    (BIT(31))
910 #define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
911 #define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
912 #define RTC_CNTL_DG_WRAP_PD_EN_S  31
913 /* RTC_CNTL_DG_WRAP_FORCE_PU :  ;bitpos:[20] ;default: 1'd1 ; */
914 /*description: digital core force power up.*/
915 #define RTC_CNTL_DG_WRAP_FORCE_PU    (BIT(20))
916 #define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
917 #define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
918 #define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
919 /* RTC_CNTL_DG_WRAP_FORCE_PD :  ;bitpos:[19] ;default: 1'b0 ; */
920 /*description: digital core force power down.*/
921 #define RTC_CNTL_DG_WRAP_FORCE_PD    (BIT(19))
922 #define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
923 #define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
924 #define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
925 /* RTC_CNTL_LSLP_MEM_FORCE_PU :  ;bitpos:[5] ;default: 1'b1 ; */
926 /*description: memories in digital core force no PD in sleep.*/
927 #define RTC_CNTL_LSLP_MEM_FORCE_PU    (BIT(5))
928 #define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(5))
929 #define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
930 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S  5
931 /* RTC_CNTL_LSLP_MEM_FORCE_PD :  ;bitpos:[4] ;default: 1'b0 ; */
932 /*description: memories in digital core force PD in sleep.*/
933 #define RTC_CNTL_LSLP_MEM_FORCE_PD    (BIT(4))
934 #define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(4))
935 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
936 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S  4
937 /* RTC_CNTL_VDD_SPI_PD_EN :  ;bitpos:[3] ;default: 1'b0 ; */
938 /*description: Need add desc.*/
939 #define RTC_CNTL_VDD_SPI_PD_EN    (BIT(3))
940 #define RTC_CNTL_VDD_SPI_PD_EN_M  (BIT(3))
941 #define RTC_CNTL_VDD_SPI_PD_EN_V  0x1
942 #define RTC_CNTL_VDD_SPI_PD_EN_S  3
943 /* RTC_CNTL_VDD_SPI_PWR_FORCE :  ;bitpos:[2] ;default: 1'b0 ; */
944 /*description: Need add desc.*/
945 #define RTC_CNTL_VDD_SPI_PWR_FORCE    (BIT(2))
946 #define RTC_CNTL_VDD_SPI_PWR_FORCE_M  (BIT(2))
947 #define RTC_CNTL_VDD_SPI_PWR_FORCE_V  0x1
948 #define RTC_CNTL_VDD_SPI_PWR_FORCE_S  2
949 /* RTC_CNTL_VDD_SPI_PWR_DRV :  ;bitpos:[1:0] ;default: 2'b0 ; */
950 /*description: Need add desc.*/
951 #define RTC_CNTL_VDD_SPI_PWR_DRV    0x00000003
952 #define RTC_CNTL_VDD_SPI_PWR_DRV_M  ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S))
953 #define RTC_CNTL_VDD_SPI_PWR_DRV_V  0x3
954 #define RTC_CNTL_VDD_SPI_PWR_DRV_S  0
955 
956 #define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x80)
957 /* RTC_CNTL_DG_WRAP_FORCE_NOISO :  ;bitpos:[31] ;default: 1'd1 ; */
958 /*description: Need add desc.*/
959 #define RTC_CNTL_DG_WRAP_FORCE_NOISO    (BIT(31))
960 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
961 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
962 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
963 /* RTC_CNTL_DG_WRAP_FORCE_ISO :  ;bitpos:[30] ;default: 1'd0 ; */
964 /*description: digital core force ISO.*/
965 #define RTC_CNTL_DG_WRAP_FORCE_ISO    (BIT(30))
966 #define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
967 #define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
968 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
969 /* RTC_CNTL_DG_PAD_FORCE_HOLD :  ;bitpos:[15] ;default: 1'd0 ; */
970 /*description: digital pad force hold.*/
971 #define RTC_CNTL_DG_PAD_FORCE_HOLD    (BIT(15))
972 #define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
973 #define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
974 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
975 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD :  ;bitpos:[14] ;default: 1'd1 ; */
976 /*description: digital pad force un-hold.*/
977 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD    (BIT(14))
978 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
979 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
980 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
981 /* RTC_CNTL_DG_PAD_FORCE_ISO :  ;bitpos:[13] ;default: 1'd0 ; */
982 /*description: digital pad force ISO.*/
983 #define RTC_CNTL_DG_PAD_FORCE_ISO    (BIT(13))
984 #define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
985 #define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
986 #define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
987 /* RTC_CNTL_DG_PAD_FORCE_NOISO :  ;bitpos:[12] ;default: 1'd1 ; */
988 /*description: digital pad force no ISO.*/
989 #define RTC_CNTL_DG_PAD_FORCE_NOISO    (BIT(12))
990 #define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
991 #define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
992 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
993 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN :  ;bitpos:[11] ;default: 1'd0 ; */
994 /*description: digital pad enable auto-hold.*/
995 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN    (BIT(11))
996 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
997 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
998 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
999 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD :  ;bitpos:[10] ;default: 1'd0 ; */
1000 /*description: wtite only register to clear digital pad auto-hold.*/
1001 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD    (BIT(10))
1002 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
1003 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
1004 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
1005 /* RTC_CNTL_DG_PAD_AUTOHOLD :  ;bitpos:[9] ;default: 1'd0 ; */
1006 /*description: read only register to indicate digital pad auto-hold status.*/
1007 #define RTC_CNTL_DG_PAD_AUTOHOLD    (BIT(9))
1008 #define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
1009 #define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
1010 #define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
1011 /* RTC_CNTL_DIG_ISO_FORCE_ON :  ;bitpos:[8] ;default: 1'd0 ; */
1012 /*description: Need add desc.*/
1013 #define RTC_CNTL_DIG_ISO_FORCE_ON    (BIT(8))
1014 #define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
1015 #define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
1016 #define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
1017 /* RTC_CNTL_DIG_ISO_FORCE_OFF :  ;bitpos:[7] ;default: 1'd1 ; */
1018 /*description: Need add desc.*/
1019 #define RTC_CNTL_DIG_ISO_FORCE_OFF    (BIT(7))
1020 #define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
1021 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
1022 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
1023 
1024 #define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x84)
1025 /* RTC_CNTL_WDT_EN :  ;bitpos:[31] ;default: 1'h0 ; */
1026 /*description: Need add desc.*/
1027 #define RTC_CNTL_WDT_EN    (BIT(31))
1028 #define RTC_CNTL_WDT_EN_M  (BIT(31))
1029 #define RTC_CNTL_WDT_EN_V  0x1
1030 #define RTC_CNTL_WDT_EN_S  31
1031 /* RTC_CNTL_WDT_STG0 :  ;bitpos:[30:28] ;default: 3'h0 ; */
1032 /*description: 1: interrupt stage en.*/
1033 #define RTC_CNTL_WDT_STG0    0x00000007
1034 #define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
1035 #define RTC_CNTL_WDT_STG0_V  0x7
1036 #define RTC_CNTL_WDT_STG0_S  28
1037 /* RTC_CNTL_WDT_STG1 :  ;bitpos:[27:25] ;default: 3'h0 ; */
1038 /*description: 1: interrupt stage en.*/
1039 #define RTC_CNTL_WDT_STG1    0x00000007
1040 #define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
1041 #define RTC_CNTL_WDT_STG1_V  0x7
1042 #define RTC_CNTL_WDT_STG1_S  25
1043 /* RTC_CNTL_WDT_STG2 :  ;bitpos:[24:22] ;default: 3'h0 ; */
1044 /*description: 1: interrupt stage en.*/
1045 #define RTC_CNTL_WDT_STG2    0x00000007
1046 #define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
1047 #define RTC_CNTL_WDT_STG2_V  0x7
1048 #define RTC_CNTL_WDT_STG2_S  22
1049 /* RTC_CNTL_WDT_STG3 :  ;bitpos:[21:19] ;default: 3'h0 ; */
1050 /*description: 1: interrupt stage en.*/
1051 #define RTC_CNTL_WDT_STG3    0x00000007
1052 #define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
1053 #define RTC_CNTL_WDT_STG3_V  0x7
1054 #define RTC_CNTL_WDT_STG3_S  19
1055 
1056 /* RTC_CNTL_WDT_STGX : */
1057 /*description: stage action selection values */
1058 #define RTC_WDT_STG_SEL_OFF             0
1059 #define RTC_WDT_STG_SEL_INT             1
1060 #define RTC_WDT_STG_SEL_RESET_CPU       2
1061 #define RTC_WDT_STG_SEL_RESET_SYSTEM    3
1062 #define RTC_WDT_STG_SEL_RESET_RTC       4
1063 
1064 /* RTC_CNTL_WDT_CPU_RESET_LENGTH :  ;bitpos:[18:16] ;default: 3'h1 ; */
1065 /*description: CPU reset counter length.*/
1066 #define RTC_CNTL_WDT_CPU_RESET_LENGTH    0x00000007
1067 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
1068 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
1069 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
1070 /* RTC_CNTL_WDT_SYS_RESET_LENGTH :  ;bitpos:[15:13] ;default: 3'h1 ; */
1071 /*description: system reset counter length.*/
1072 #define RTC_CNTL_WDT_SYS_RESET_LENGTH    0x00000007
1073 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
1074 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
1075 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
1076 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN :  ;bitpos:[12] ;default: 1'h1 ; */
1077 /*description: enable WDT in flash boot.*/
1078 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN    (BIT(12))
1079 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
1080 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
1081 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
1082 /* RTC_CNTL_WDT_PROCPU_RESET_EN :  ;bitpos:[11] ;default: 1'd0 ; */
1083 /*description: enable WDT reset PRO CPU.*/
1084 #define RTC_CNTL_WDT_PROCPU_RESET_EN    (BIT(11))
1085 #define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
1086 #define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
1087 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
1088 /* RTC_CNTL_WDT_PAUSE_IN_SLP :  ;bitpos:[9] ;default: 1'd1 ; */
1089 /*description: pause WDT in sleep.*/
1090 #define RTC_CNTL_WDT_PAUSE_IN_SLP    (BIT(9))
1091 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
1092 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
1093 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
1094 /* RTC_CNTL_WDT_CHIP_RESET_EN :  ;bitpos:[8] ;default: 1'b0 ; */
1095 /*description: wdt reset whole chip enable.*/
1096 #define RTC_CNTL_WDT_CHIP_RESET_EN    (BIT(8))
1097 #define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
1098 #define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
1099 #define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
1100 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH :  ;bitpos:[7:0] ;default: 8'd20 ; */
1101 /*description: chip reset siginal pulse width.*/
1102 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH    0x000000FF
1103 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
1104 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
1105 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
1106 
1107 #define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x88)
1108 /* RTC_CNTL_WDT_STG0_HOLD :  ;bitpos:[31:0] ;default: 32'd200000 ; */
1109 /*description: Need add desc.*/
1110 #define RTC_CNTL_WDT_STG0_HOLD    0xFFFFFFFF
1111 #define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
1112 #define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
1113 #define RTC_CNTL_WDT_STG0_HOLD_S  0
1114 
1115 #define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x8C)
1116 /* RTC_CNTL_WDT_STG1_HOLD :  ;bitpos:[31:0] ;default: 32'd80000 ; */
1117 /*description: Need add desc.*/
1118 #define RTC_CNTL_WDT_STG1_HOLD    0xFFFFFFFF
1119 #define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
1120 #define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
1121 #define RTC_CNTL_WDT_STG1_HOLD_S  0
1122 
1123 #define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x90)
1124 /* RTC_CNTL_WDT_STG2_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
1125 /*description: Need add desc.*/
1126 #define RTC_CNTL_WDT_STG2_HOLD    0xFFFFFFFF
1127 #define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
1128 #define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
1129 #define RTC_CNTL_WDT_STG2_HOLD_S  0
1130 
1131 #define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x94)
1132 /* RTC_CNTL_WDT_STG3_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
1133 /*description: Need add desc.*/
1134 #define RTC_CNTL_WDT_STG3_HOLD    0xFFFFFFFF
1135 #define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
1136 #define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
1137 #define RTC_CNTL_WDT_STG3_HOLD_S  0
1138 
1139 #define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x98)
1140 /* RTC_CNTL_WDT_FEED :  ;bitpos:[31] ;default: 1'd0 ; */
1141 /*description: Need add desc.*/
1142 #define RTC_CNTL_WDT_FEED    (BIT(31))
1143 #define RTC_CNTL_WDT_FEED_M  (BIT(31))
1144 #define RTC_CNTL_WDT_FEED_V  0x1
1145 #define RTC_CNTL_WDT_FEED_S  31
1146 
1147 #define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x9C)
1148 /* RTC_CNTL_WDT_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
1149 /*description: Need add desc.*/
1150 #define RTC_CNTL_WDT_WKEY    0xFFFFFFFF
1151 #define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
1152 #define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
1153 #define RTC_CNTL_WDT_WKEY_S  0
1154 
1155 #define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xA0)
1156 /* RTC_CNTL_SWD_AUTO_FEED_EN :  ;bitpos:[31] ;default: 1'b0 ; */
1157 /*description: automatically feed swd when int comes.*/
1158 #define RTC_CNTL_SWD_AUTO_FEED_EN    (BIT(31))
1159 #define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
1160 #define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
1161 #define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
1162 /* RTC_CNTL_SWD_DISABLE :  ;bitpos:[30] ;default: 1'b0 ; */
1163 /*description: disabel SWD.*/
1164 #define RTC_CNTL_SWD_DISABLE    (BIT(30))
1165 #define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
1166 #define RTC_CNTL_SWD_DISABLE_V  0x1
1167 #define RTC_CNTL_SWD_DISABLE_S  30
1168 /* RTC_CNTL_SWD_FEED :  ;bitpos:[29] ;default: 1'b0 ; */
1169 /*description: Sw feed swd.*/
1170 #define RTC_CNTL_SWD_FEED    (BIT(29))
1171 #define RTC_CNTL_SWD_FEED_M  (BIT(29))
1172 #define RTC_CNTL_SWD_FEED_V  0x1
1173 #define RTC_CNTL_SWD_FEED_S  29
1174 /* RTC_CNTL_SWD_RST_FLAG_CLR :  ;bitpos:[28] ;default: 1'b0 ; */
1175 /*description: reset swd reset flag.*/
1176 #define RTC_CNTL_SWD_RST_FLAG_CLR    (BIT(28))
1177 #define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
1178 #define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
1179 #define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
1180 /* RTC_CNTL_SWD_SIGNAL_WIDTH :  ;bitpos:[27:18] ;default: 10'd300 ; */
1181 /*description: adjust signal width send to swd.*/
1182 #define RTC_CNTL_SWD_SIGNAL_WIDTH    0x000003FF
1183 #define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
1184 #define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
1185 #define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
1186 /* RTC_CNTL_SWD_BYPASS_RST :  ;bitpos:[17] ;default: 1'b0 ; */
1187 /*description: Need add desc.*/
1188 #define RTC_CNTL_SWD_BYPASS_RST    (BIT(17))
1189 #define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
1190 #define RTC_CNTL_SWD_BYPASS_RST_V  0x1
1191 #define RTC_CNTL_SWD_BYPASS_RST_S  17
1192 /* RTC_CNTL_SWD_FEED_INT :  ;bitpos:[1] ;default: 1'b0 ; */
1193 /*description: swd interrupt for feeding.*/
1194 #define RTC_CNTL_SWD_FEED_INT    (BIT(1))
1195 #define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
1196 #define RTC_CNTL_SWD_FEED_INT_V  0x1
1197 #define RTC_CNTL_SWD_FEED_INT_S  1
1198 /* RTC_CNTL_SWD_RESET_FLAG :  ;bitpos:[0] ;default: 1'b0 ; */
1199 /*description: swd reset flag.*/
1200 #define RTC_CNTL_SWD_RESET_FLAG    (BIT(0))
1201 #define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
1202 #define RTC_CNTL_SWD_RESET_FLAG_V  0x1
1203 #define RTC_CNTL_SWD_RESET_FLAG_S  0
1204 
1205 #define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xA4)
1206 /* RTC_CNTL_SWD_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
1207 /*description: Need add desc.*/
1208 #define RTC_CNTL_SWD_WKEY    0xFFFFFFFF
1209 #define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
1210 #define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
1211 #define RTC_CNTL_SWD_WKEY_S  0
1212 
1213 #define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xA8)
1214 /* RTC_CNTL_SW_STALL_PROCPU_C1 :  ;bitpos:[31:26] ;default: 6'b0 ; */
1215 /*description: Need add desc.*/
1216 #define RTC_CNTL_SW_STALL_PROCPU_C1    0x0000003F
1217 #define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
1218 #define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
1219 #define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
1220 
1221 #define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xAC)
1222 /* RTC_CNTL_SCRATCH4 :  ;bitpos:[31:0] ;default: 0 ; */
1223 /*description: Need add desc.*/
1224 #define RTC_CNTL_SCRATCH4    0xFFFFFFFF
1225 #define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
1226 #define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
1227 #define RTC_CNTL_SCRATCH4_S  0
1228 
1229 #define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xB0)
1230 /* RTC_CNTL_SCRATCH5 :  ;bitpos:[31:0] ;default: 0 ; */
1231 /*description: Need add desc.*/
1232 #define RTC_CNTL_SCRATCH5    0xFFFFFFFF
1233 #define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
1234 #define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
1235 #define RTC_CNTL_SCRATCH5_S  0
1236 
1237 #define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xB4)
1238 /* RTC_CNTL_SCRATCH6 :  ;bitpos:[31:0] ;default: 0 ; */
1239 /*description: Need add desc.*/
1240 #define RTC_CNTL_SCRATCH6    0xFFFFFFFF
1241 #define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
1242 #define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
1243 #define RTC_CNTL_SCRATCH6_S  0
1244 
1245 #define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xB8)
1246 /* RTC_CNTL_SCRATCH7 :  ;bitpos:[31:0] ;default: 0 ; */
1247 /*description: Need add desc.*/
1248 #define RTC_CNTL_SCRATCH7    0xFFFFFFFF
1249 #define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
1250 #define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
1251 #define RTC_CNTL_SCRATCH7_S  0
1252 
1253 #define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xBC)
1254 /* RTC_CNTL_MAIN_STATE :  ;bitpos:[31:28] ;default: 4'd0 ; */
1255 /*description: rtc main state machine status.*/
1256 #define RTC_CNTL_MAIN_STATE    0x0000000F
1257 #define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
1258 #define RTC_CNTL_MAIN_STATE_V  0xF
1259 #define RTC_CNTL_MAIN_STATE_S  28
1260 /* RTC_CNTL_MAIN_STATE_IN_IDLE :  ;bitpos:[27] ;default: 1'b0 ; */
1261 /*description: rtc main state machine is in idle state.*/
1262 #define RTC_CNTL_MAIN_STATE_IN_IDLE    (BIT(27))
1263 #define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
1264 #define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
1265 #define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
1266 /* RTC_CNTL_MAIN_STATE_IN_SLP :  ;bitpos:[26] ;default: 1'b0 ; */
1267 /*description: rtc main state machine is in sleep state.*/
1268 #define RTC_CNTL_MAIN_STATE_IN_SLP    (BIT(26))
1269 #define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
1270 #define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
1271 #define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
1272 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL :  ;bitpos:[25] ;default: 1'b0 ; */
1273 /*description: rtc main state machine is in wait xtal state.*/
1274 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL    (BIT(25))
1275 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
1276 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
1277 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
1278 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL :  ;bitpos:[24] ;default: 1'b0 ; */
1279 /*description: rtc main state machine is in wait pll state.*/
1280 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL    (BIT(24))
1281 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
1282 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
1283 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
1284 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M :  ;bitpos:[23] ;default: 1'b0 ; */
1285 /*description: rtc main state machine is in wait 8m state.*/
1286 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M    (BIT(23))
1287 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
1288 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
1289 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
1290 /* RTC_CNTL_IN_LOW_POWER_STATE :  ;bitpos:[22] ;default: 1'b0 ; */
1291 /*description: rtc main state machine is in the states of low power.*/
1292 #define RTC_CNTL_IN_LOW_POWER_STATE    (BIT(22))
1293 #define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
1294 #define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
1295 #define RTC_CNTL_IN_LOW_POWER_STATE_S  22
1296 /* RTC_CNTL_IN_WAKEUP_STATE :  ;bitpos:[21] ;default: 1'b0 ; */
1297 /*description: rtc main state machine is in the states of wakeup process.*/
1298 #define RTC_CNTL_IN_WAKEUP_STATE    (BIT(21))
1299 #define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
1300 #define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
1301 #define RTC_CNTL_IN_WAKEUP_STATE_S  21
1302 /* RTC_CNTL_MAIN_STATE_WAIT_END :  ;bitpos:[20] ;default: 1'b0 ; */
1303 /*description: rtc main state machine has been waited for some cycles.*/
1304 #define RTC_CNTL_MAIN_STATE_WAIT_END    (BIT(20))
1305 #define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
1306 #define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
1307 #define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
1308 /* RTC_CNTL_RDY_FOR_WAKEUP :  ;bitpos:[19] ;default: 1'b0 ; */
1309 /*description: rtc is ready to receive wake up trigger from wake up source.*/
1310 #define RTC_CNTL_RDY_FOR_WAKEUP    (BIT(19))
1311 #define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
1312 #define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
1313 #define RTC_CNTL_RDY_FOR_WAKEUP_S  19
1314 /* RTC_CNTL_MAIN_STATE_PLL_ON :  ;bitpos:[18] ;default: 1'b0 ; */
1315 /*description: rtc main state machine is in states that pll should be running.*/
1316 #define RTC_CNTL_MAIN_STATE_PLL_ON    (BIT(18))
1317 #define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
1318 #define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
1319 #define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
1320 /* RTC_CNTL_MAIN_STATE_XTAL_ISO :  ;bitpos:[17] ;default: 1'b0 ; */
1321 /*description: no use any more.*/
1322 #define RTC_CNTL_MAIN_STATE_XTAL_ISO    (BIT(17))
1323 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
1324 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
1325 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
1326 /* RTC_CNTL_COCPU_STATE_DONE :  ;bitpos:[16] ;default: 1'b0 ; */
1327 /*description: ulp/cocpu is done.*/
1328 #define RTC_CNTL_COCPU_STATE_DONE    (BIT(16))
1329 #define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
1330 #define RTC_CNTL_COCPU_STATE_DONE_V  0x1
1331 #define RTC_CNTL_COCPU_STATE_DONE_S  16
1332 /* RTC_CNTL_COCPU_STATE_SLP :  ;bitpos:[15] ;default: 1'b0 ; */
1333 /*description: ulp/cocpu is in sleep state.*/
1334 #define RTC_CNTL_COCPU_STATE_SLP    (BIT(15))
1335 #define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
1336 #define RTC_CNTL_COCPU_STATE_SLP_V  0x1
1337 #define RTC_CNTL_COCPU_STATE_SLP_S  15
1338 /* RTC_CNTL_COCPU_STATE_SWITCH :  ;bitpos:[14] ;default: 1'b0 ; */
1339 /*description: ulp/cocpu is about to working. Switch rtc main state.*/
1340 #define RTC_CNTL_COCPU_STATE_SWITCH    (BIT(14))
1341 #define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
1342 #define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
1343 #define RTC_CNTL_COCPU_STATE_SWITCH_S  14
1344 /* RTC_CNTL_COCPU_STATE_START :  ;bitpos:[13] ;default: 1'b0 ; */
1345 /*description: ulp/cocpu should start to work.*/
1346 #define RTC_CNTL_COCPU_STATE_START    (BIT(13))
1347 #define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
1348 #define RTC_CNTL_COCPU_STATE_START_V  0x1
1349 #define RTC_CNTL_COCPU_STATE_START_S  13
1350 /* RTC_CNTL_TOUCH_STATE_DONE :  ;bitpos:[12] ;default: 1'b0 ; */
1351 /*description: touch is done.*/
1352 #define RTC_CNTL_TOUCH_STATE_DONE    (BIT(12))
1353 #define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
1354 #define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
1355 #define RTC_CNTL_TOUCH_STATE_DONE_S  12
1356 /* RTC_CNTL_TOUCH_STATE_SLP :  ;bitpos:[11] ;default: 1'b0 ; */
1357 /*description: touch is in sleep state.*/
1358 #define RTC_CNTL_TOUCH_STATE_SLP    (BIT(11))
1359 #define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
1360 #define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
1361 #define RTC_CNTL_TOUCH_STATE_SLP_S  11
1362 /* RTC_CNTL_TOUCH_STATE_SWITCH :  ;bitpos:[10] ;default: 1'b0 ; */
1363 /*description: touch is about to working. Switch rtc main state.*/
1364 #define RTC_CNTL_TOUCH_STATE_SWITCH    (BIT(10))
1365 #define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
1366 #define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
1367 #define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
1368 /* RTC_CNTL_TOUCH_STATE_START :  ;bitpos:[9] ;default: 1'b0 ; */
1369 /*description: touch should start to work.*/
1370 #define RTC_CNTL_TOUCH_STATE_START    (BIT(9))
1371 #define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
1372 #define RTC_CNTL_TOUCH_STATE_START_V  0x1
1373 #define RTC_CNTL_TOUCH_STATE_START_S  9
1374 /* RTC_CNTL_XPD_DIG :  ;bitpos:[8] ;default: 1'b0 ; */
1375 /*description: digital wrap power down.*/
1376 #define RTC_CNTL_XPD_DIG    (BIT(8))
1377 #define RTC_CNTL_XPD_DIG_M  (BIT(8))
1378 #define RTC_CNTL_XPD_DIG_V  0x1
1379 #define RTC_CNTL_XPD_DIG_S  8
1380 
1381 #define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0xC0)
1382 /* RTC_CNTL_LOW_POWER_DIAG1 :  ;bitpos:[31:0] ;default: 0 ; */
1383 /*description: Need add desc.*/
1384 #define RTC_CNTL_LOW_POWER_DIAG1    0xFFFFFFFF
1385 #define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
1386 #define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
1387 #define RTC_CNTL_LOW_POWER_DIAG1_S  0
1388 
1389 #define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC4)
1390 /* RTC_CNTL_GPIO_PIN5_HOLD :  ;bitpos:[5] ;default: 1'b0 ; */
1391 /*description: Need add desc.*/
1392 #define RTC_CNTL_GPIO_PIN5_HOLD    (BIT(5))
1393 #define RTC_CNTL_GPIO_PIN5_HOLD_M  (BIT(5))
1394 #define RTC_CNTL_GPIO_PIN5_HOLD_V  0x1
1395 #define RTC_CNTL_GPIO_PIN5_HOLD_S  5
1396 /* RTC_CNTL_GPIO_PIN4_HOLD :  ;bitpos:[4] ;default: 1'b0 ; */
1397 /*description: Need add desc.*/
1398 #define RTC_CNTL_GPIO_PIN4_HOLD    (BIT(4))
1399 #define RTC_CNTL_GPIO_PIN4_HOLD_M  (BIT(4))
1400 #define RTC_CNTL_GPIO_PIN4_HOLD_V  0x1
1401 #define RTC_CNTL_GPIO_PIN4_HOLD_S  4
1402 /* RTC_CNTL_GPIO_PIN3_HOLD :  ;bitpos:[3] ;default: 1'b0 ; */
1403 /*description: Need add desc.*/
1404 #define RTC_CNTL_GPIO_PIN3_HOLD    (BIT(3))
1405 #define RTC_CNTL_GPIO_PIN3_HOLD_M  (BIT(3))
1406 #define RTC_CNTL_GPIO_PIN3_HOLD_V  0x1
1407 #define RTC_CNTL_GPIO_PIN3_HOLD_S  3
1408 /* RTC_CNTL_GPIO_PIN2_HOLD :  ;bitpos:[2] ;default: 1'b0 ; */
1409 /*description: Need add desc.*/
1410 #define RTC_CNTL_GPIO_PIN2_HOLD    (BIT(2))
1411 #define RTC_CNTL_GPIO_PIN2_HOLD_M  (BIT(2))
1412 #define RTC_CNTL_GPIO_PIN2_HOLD_V  0x1
1413 #define RTC_CNTL_GPIO_PIN2_HOLD_S  2
1414 /* RTC_CNTL_GPIO_PIN1_HOLD :  ;bitpos:[1] ;default: 1'b0 ; */
1415 /*description: Need add desc.*/
1416 #define RTC_CNTL_GPIO_PIN1_HOLD    (BIT(1))
1417 #define RTC_CNTL_GPIO_PIN1_HOLD_M  (BIT(1))
1418 #define RTC_CNTL_GPIO_PIN1_HOLD_V  0x1
1419 #define RTC_CNTL_GPIO_PIN1_HOLD_S  1
1420 /* RTC_CNTL_GPIO_PIN0_HOLD :  ;bitpos:[0] ;default: 1'b0 ; */
1421 /*description: Need add desc.*/
1422 #define RTC_CNTL_GPIO_PIN0_HOLD    (BIT(0))
1423 #define RTC_CNTL_GPIO_PIN0_HOLD_M  (BIT(0))
1424 #define RTC_CNTL_GPIO_PIN0_HOLD_V  0x1
1425 #define RTC_CNTL_GPIO_PIN0_HOLD_S  0
1426 
1427 #define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC8)
1428 /* RTC_CNTL_DIG_PAD_HOLD :  ;bitpos:[31:0] ;default: 32'b0 ; */
1429 /*description: Need add desc.*/
1430 #define RTC_CNTL_DIG_PAD_HOLD    0xFFFFFFFF
1431 #define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
1432 #define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
1433 #define RTC_CNTL_DIG_PAD_HOLD_S  0
1434 
1435 #define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xCC)
1436 /* RTC_CNTL_BROWN_OUT_DET :  ;bitpos:[31] ;default: 1'b0 ; */
1437 /*description: Need add desc.*/
1438 #define RTC_CNTL_BROWN_OUT_DET    (BIT(31))
1439 #define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
1440 #define RTC_CNTL_BROWN_OUT_DET_V  0x1
1441 #define RTC_CNTL_BROWN_OUT_DET_S  31
1442 /* RTC_CNTL_BROWN_OUT_ENA :  ;bitpos:[30] ;default: 1'b1 ; */
1443 /*description: enable brown out.*/
1444 #define RTC_CNTL_BROWN_OUT_ENA    (BIT(30))
1445 #define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
1446 #define RTC_CNTL_BROWN_OUT_ENA_V  0x1
1447 #define RTC_CNTL_BROWN_OUT_ENA_S  30
1448 /* RTC_CNTL_BROWN_OUT_CNT_CLR :  ;bitpos:[29] ;default: 1'b0 ; */
1449 /*description: clear brown out counter.*/
1450 #define RTC_CNTL_BROWN_OUT_CNT_CLR    (BIT(29))
1451 #define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
1452 #define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
1453 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
1454 /* RTC_CNTL_BROWN_OUT_ANA_RST_EN :  ;bitpos:[28] ;default: 1'b0 ; */
1455 /*description: Need add desc.*/
1456 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN    (BIT(28))
1457 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
1458 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
1459 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
1460 /* RTC_CNTL_BROWN_OUT_RST_SEL :  ;bitpos:[27] ;default: 1'b0 ; */
1461 /*description: 1:  4-pos reset.*/
1462 #define RTC_CNTL_BROWN_OUT_RST_SEL    (BIT(27))
1463 #define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
1464 #define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
1465 #define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
1466 /* RTC_CNTL_BROWN_OUT_RST_ENA :  ;bitpos:[26] ;default: 1'b0 ; */
1467 /*description: enable brown out reset.*/
1468 #define RTC_CNTL_BROWN_OUT_RST_ENA    (BIT(26))
1469 #define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
1470 #define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
1471 #define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
1472 /* RTC_CNTL_BROWN_OUT_RST_WAIT :  ;bitpos:[25:16] ;default: 10'h3ff ; */
1473 /*description: brown out reset wait cycles.*/
1474 #define RTC_CNTL_BROWN_OUT_RST_WAIT    0x000003FF
1475 #define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
1476 #define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
1477 #define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
1478 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA :  ;bitpos:[15] ;default: 1'b0 ; */
1479 /*description: enable power down RF when brown out happens.*/
1480 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA    (BIT(15))
1481 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
1482 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
1483 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
1484 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA :  ;bitpos:[14] ;default: 1'b0 ; */
1485 /*description: enable close flash when brown out happens.*/
1486 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA    (BIT(14))
1487 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
1488 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
1489 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
1490 /* RTC_CNTL_BROWN_OUT_INT_WAIT :  ;bitpos:[13:4] ;default: 10'h1 ; */
1491 /*description: brown out interrupt wait cycles.*/
1492 #define RTC_CNTL_BROWN_OUT_INT_WAIT    0x000003FF
1493 #define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
1494 #define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
1495 #define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
1496 
1497 #define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0xD0)
1498 /* RTC_CNTL_TIMER_VALUE1_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
1499 /*description: RTC timer low 32 bits.*/
1500 #define RTC_CNTL_TIMER_VALUE1_LOW    0xFFFFFFFF
1501 #define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
1502 #define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
1503 #define RTC_CNTL_TIMER_VALUE1_LOW_S  0
1504 
1505 #define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0xD4)
1506 /* RTC_CNTL_TIMER_VALUE1_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
1507 /*description: RTC timer high 16 bits.*/
1508 #define RTC_CNTL_TIMER_VALUE1_HIGH    0x0000FFFF
1509 #define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
1510 #define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
1511 #define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
1512 
1513 #define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xD8)
1514 /* RTC_CNTL_IO_MUX_RESET_DISABLE :  ;bitpos:[18] ;default: 1'd0 ; */
1515 /*description: Need add desc.*/
1516 #define RTC_CNTL_IO_MUX_RESET_DISABLE    (BIT(18))
1517 #define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
1518 #define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
1519 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
1520 
1521 #define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xDC)
1522 /* RTC_CNTL_REJECT_CAUSE :  ;bitpos:[17:0] ;default: 18'd0 ; */
1523 /*description: sleep reject cause.*/
1524 #define RTC_CNTL_REJECT_CAUSE    0x0003FFFF
1525 #define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
1526 #define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
1527 #define RTC_CNTL_REJECT_CAUSE_S  0
1528 
1529 #define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0xE0)
1530 /* RTC_CNTL_FORCE_DOWNLOAD_BOOT :  ;bitpos:[0] ;default: 1'd0 ; */
1531 /*description: Need add desc.*/
1532 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT    (BIT(0))
1533 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
1534 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
1535 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
1536 
1537 #define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xE4)
1538 /* RTC_CNTL_WAKEUP_CAUSE :  ;bitpos:[16:0] ;default: 17'd0 ; */
1539 /*description: sleep wakeup cause.*/
1540 #define RTC_CNTL_WAKEUP_CAUSE    0x0001FFFF
1541 #define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
1542 #define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
1543 #define RTC_CNTL_WAKEUP_CAUSE_S  0
1544 
1545 #define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0xE8)
1546 /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE :  ;bitpos:[31:8] ;default: 24'd200 ; */
1547 /*description: sleep cycles for ULP-coprocessor timer.*/
1548 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE    0x00FFFFFF
1549 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
1550 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
1551 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
1552 
1553 #define RTC_CNTL_INT_ENA_RTC_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0xEC)
1554 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS :  ;bitpos:[20] ;default: 1'b0 ; */
1555 /*description: Need add desc.*/
1556 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS    (BIT(20))
1557 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M  (BIT(20))
1558 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V  0x1
1559 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S  20
1560 /* RTC_CNTL_SWD_INT_ENA_W1TS :  ;bitpos:[15] ;default: 1'b0 ; */
1561 /*description: enable super watch dog interrupt.*/
1562 #define RTC_CNTL_SWD_INT_ENA_W1TS    (BIT(15))
1563 #define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
1564 #define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
1565 #define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
1566 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS :  ;bitpos:[10] ;default: 1'b0 ; */
1567 /*description: enable RTC main timer interrupt.*/
1568 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS    (BIT(10))
1569 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
1570 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
1571 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
1572 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS :  ;bitpos:[9] ;default: 1'b0 ; */
1573 /*description: enable brown out interrupt.*/
1574 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS    (BIT(9))
1575 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
1576 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
1577 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
1578 /* RTC_CNTL_WDT_INT_ENA_W1TS :  ;bitpos:[3] ;default: 1'b0 ; */
1579 /*description: enable RTC WDT interrupt.*/
1580 #define RTC_CNTL_WDT_INT_ENA_W1TS    (BIT(3))
1581 #define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
1582 #define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
1583 #define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
1584 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS :  ;bitpos:[1] ;default: 1'b0 ; */
1585 /*description: enable sleep reject interrupt.*/
1586 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS    (BIT(1))
1587 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
1588 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
1589 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
1590 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS :  ;bitpos:[0] ;default: 1'b0 ; */
1591 /*description: enable sleep wakeup interrupt.*/
1592 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS    (BIT(0))
1593 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
1594 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
1595 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
1596 
1597 #define RTC_CNTL_INT_ENA_RTC_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0xF0)
1598 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC :  ;bitpos:[20] ;default: 1'b0 ; */
1599 /*description: Need add desc.*/
1600 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC    (BIT(20))
1601 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M  (BIT(20))
1602 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V  0x1
1603 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S  20
1604 /* RTC_CNTL_SWD_INT_ENA_W1TC :  ;bitpos:[15] ;default: 1'b0 ; */
1605 /*description: enable super watch dog interrupt.*/
1606 #define RTC_CNTL_SWD_INT_ENA_W1TC    (BIT(15))
1607 #define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
1608 #define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
1609 #define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
1610 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC :  ;bitpos:[10] ;default: 1'b0 ; */
1611 /*description: enable RTC main timer interrupt.*/
1612 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC    (BIT(10))
1613 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
1614 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
1615 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
1616 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC :  ;bitpos:[9] ;default: 1'b0 ; */
1617 /*description: enable brown out interrupt.*/
1618 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC    (BIT(9))
1619 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
1620 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
1621 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
1622 /* RTC_CNTL_WDT_INT_ENA_W1TC :  ;bitpos:[3] ;default: 1'b0 ; */
1623 /*description: enable RTC WDT interrupt.*/
1624 #define RTC_CNTL_WDT_INT_ENA_W1TC    (BIT(3))
1625 #define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
1626 #define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
1627 #define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
1628 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC :  ;bitpos:[1] ;default: 1'b0 ; */
1629 /*description: enable sleep reject interrupt.*/
1630 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC    (BIT(1))
1631 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
1632 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
1633 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
1634 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC :  ;bitpos:[0] ;default: 1'b0 ; */
1635 /*description: enable sleep wakeup interrupt.*/
1636 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC    (BIT(0))
1637 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
1638 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
1639 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
1640 
1641 #define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0xF4)
1642 /* RTC_CNTL_RETENTION_WAIT :  ;bitpos:[31:27] ;default: 5'd20 ; */
1643 /*description: wait cycles for rention operation.*/
1644 #define RTC_CNTL_RETENTION_WAIT    0x0000001F
1645 #define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
1646 #define RTC_CNTL_RETENTION_WAIT_V  0x1F
1647 #define RTC_CNTL_RETENTION_WAIT_S  27
1648 /* RTC_CNTL_RETENTION_EN :  ;bitpos:[26] ;default: 1'd0 ; */
1649 /*description: Need add desc.*/
1650 #define RTC_CNTL_RETENTION_EN    (BIT(26))
1651 #define RTC_CNTL_RETENTION_EN_M  (BIT(26))
1652 #define RTC_CNTL_RETENTION_EN_V  0x1
1653 #define RTC_CNTL_RETENTION_EN_S  26
1654 /* RTC_CNTL_RETENTION_CLKOFF_WAIT :  ;bitpos:[25:22] ;default: 4'd3 ; */
1655 /*description: Need add desc.*/
1656 #define RTC_CNTL_RETENTION_CLKOFF_WAIT    0x0000000F
1657 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
1658 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
1659 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  22
1660 /* RTC_CNTL_RETENTION_DONE_WAIT :  ;bitpos:[21:19] ;default: 3'd2 ; */
1661 /*description: Need add desc.*/
1662 #define RTC_CNTL_RETENTION_DONE_WAIT    0x00000007
1663 #define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
1664 #define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
1665 #define RTC_CNTL_RETENTION_DONE_WAIT_S  19
1666 /* RTC_CNTL_RETENTION_CLK_SEL :  ;bitpos:[18] ;default: 1'b0 ; */
1667 /*description: Need add desc.*/
1668 #define RTC_CNTL_RETENTION_CLK_SEL    (BIT(18))
1669 #define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(18))
1670 #define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
1671 #define RTC_CNTL_RETENTION_CLK_SEL_S  18
1672 
1673 #define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0xF8)
1674 /* RTC_CNTL_FIB_SEL :  ;bitpos:[2:0] ;default: 3'd7 ; */
1675 /*description: select use analog fib signal.*/
1676 #define RTC_CNTL_FIB_SEL    0x00000007
1677 #define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
1678 #define RTC_CNTL_FIB_SEL_V  0x7
1679 #define RTC_CNTL_FIB_SEL_S  0
1680 
1681 #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
1682 #define RTC_CNTL_FIB_BOD_RST BIT(1)
1683 #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
1684 
1685 #define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0xFC)
1686 /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE :  ;bitpos:[31] ;default: 1'b0 ; */
1687 /*description: Need add desc.*/
1688 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE    (BIT(31))
1689 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(31))
1690 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
1691 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S  31
1692 /* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE :  ;bitpos:[30] ;default: 1'b0 ; */
1693 /*description: Need add desc.*/
1694 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE    (BIT(30))
1695 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(30))
1696 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
1697 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S  30
1698 /* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE :  ;bitpos:[29] ;default: 1'b0 ; */
1699 /*description: Need add desc.*/
1700 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE    (BIT(29))
1701 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(29))
1702 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
1703 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S  29
1704 /* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE :  ;bitpos:[28] ;default: 1'b0 ; */
1705 /*description: Need add desc.*/
1706 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE    (BIT(28))
1707 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(28))
1708 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
1709 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S  28
1710 /* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE :  ;bitpos:[27] ;default: 1'b0 ; */
1711 /*description: Need add desc.*/
1712 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE    (BIT(27))
1713 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(27))
1714 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
1715 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S  27
1716 /* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE :  ;bitpos:[26] ;default: 1'b0 ; */
1717 /*description: Need add desc.*/
1718 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE    (BIT(26))
1719 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(26))
1720 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
1721 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S  26
1722 /* RTC_CNTL_GPIO_PIN0_INT_TYPE :  ;bitpos:[25:23] ;default: 3'd0 ; */
1723 /*description: Need add desc.*/
1724 #define RTC_CNTL_GPIO_PIN0_INT_TYPE    0x00000007
1725 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S))
1726 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_V  0x7
1727 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_S  23
1728 /* RTC_CNTL_GPIO_PIN1_INT_TYPE :  ;bitpos:[22:20] ;default: 3'd0 ; */
1729 /*description: Need add desc.*/
1730 #define RTC_CNTL_GPIO_PIN1_INT_TYPE    0x00000007
1731 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S))
1732 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_V  0x7
1733 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_S  20
1734 /* RTC_CNTL_GPIO_PIN2_INT_TYPE :  ;bitpos:[19:17] ;default: 3'd0 ; */
1735 /*description: Need add desc.*/
1736 #define RTC_CNTL_GPIO_PIN2_INT_TYPE    0x00000007
1737 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S))
1738 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_V  0x7
1739 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_S  17
1740 /* RTC_CNTL_GPIO_PIN3_INT_TYPE :  ;bitpos:[16:14] ;default: 3'd0 ; */
1741 /*description: Need add desc.*/
1742 #define RTC_CNTL_GPIO_PIN3_INT_TYPE    0x00000007
1743 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
1744 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_V  0x7
1745 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_S  14
1746 /* RTC_CNTL_GPIO_PIN4_INT_TYPE :  ;bitpos:[13:11] ;default: 3'd0 ; */
1747 /*description: Need add desc.*/
1748 #define RTC_CNTL_GPIO_PIN4_INT_TYPE    0x00000007
1749 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S))
1750 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_V  0x7
1751 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_S  11
1752 /* RTC_CNTL_GPIO_PIN5_INT_TYPE :  ;bitpos:[10:8] ;default: 3'd0 ; */
1753 /*description: Need add desc.*/
1754 #define RTC_CNTL_GPIO_PIN5_INT_TYPE    0x00000007
1755 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S))
1756 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_V  0x7
1757 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_S  8
1758 /* RTC_CNTL_GPIO_PIN_CLK_GATE :  ;bitpos:[7] ;default: 1'b0 ; */
1759 /*description: Need add desc.*/
1760 #define RTC_CNTL_GPIO_PIN_CLK_GATE    (BIT(7))
1761 #define RTC_CNTL_GPIO_PIN_CLK_GATE_M  (BIT(7))
1762 #define RTC_CNTL_GPIO_PIN_CLK_GATE_V  0x1
1763 #define RTC_CNTL_GPIO_PIN_CLK_GATE_S  7
1764 /* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR :  ;bitpos:[6] ;default: 1'b0 ; */
1765 /*description: Need add desc.*/
1766 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR    (BIT(6))
1767 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M  (BIT(6))
1768 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V  0x1
1769 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S  6
1770 /* RTC_CNTL_GPIO_WAKEUP_STATUS :  ;bitpos:[5:0] ;default: 6'b0 ; */
1771 /*description: Need add desc.*/
1772 #define RTC_CNTL_GPIO_WAKEUP_STATUS    0x0000003F
1773 #define RTC_CNTL_GPIO_WAKEUP_STATUS_M  ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S))
1774 #define RTC_CNTL_GPIO_WAKEUP_STATUS_V  0x3F
1775 #define RTC_CNTL_GPIO_WAKEUP_STATUS_S  0
1776 
1777 #define RTC_CNTL_DBG_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x100)
1778 /* RTC_CNTL_DEBUG_SEL4 :  ;bitpos:[31:27] ;default: 5'd0 ; */
1779 /*description: Need add desc.*/
1780 #define RTC_CNTL_DEBUG_SEL4    0x0000001F
1781 #define RTC_CNTL_DEBUG_SEL4_M  ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S))
1782 #define RTC_CNTL_DEBUG_SEL4_V  0x1F
1783 #define RTC_CNTL_DEBUG_SEL4_S  27
1784 /* RTC_CNTL_DEBUG_SEL3 :  ;bitpos:[26:22] ;default: 5'd0 ; */
1785 /*description: Need add desc.*/
1786 #define RTC_CNTL_DEBUG_SEL3    0x0000001F
1787 #define RTC_CNTL_DEBUG_SEL3_M  ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
1788 #define RTC_CNTL_DEBUG_SEL3_V  0x1F
1789 #define RTC_CNTL_DEBUG_SEL3_S  22
1790 /* RTC_CNTL_DEBUG_SEL2 :  ;bitpos:[21:17] ;default: 5'd0 ; */
1791 /*description: Need add desc.*/
1792 #define RTC_CNTL_DEBUG_SEL2    0x0000001F
1793 #define RTC_CNTL_DEBUG_SEL2_M  ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S))
1794 #define RTC_CNTL_DEBUG_SEL2_V  0x1F
1795 #define RTC_CNTL_DEBUG_SEL2_S  17
1796 /* RTC_CNTL_DEBUG_SEL1 :  ;bitpos:[16:12] ;default: 5'd0 ; */
1797 /*description: Need add desc.*/
1798 #define RTC_CNTL_DEBUG_SEL1    0x0000001F
1799 #define RTC_CNTL_DEBUG_SEL1_M  ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S))
1800 #define RTC_CNTL_DEBUG_SEL1_V  0x1F
1801 #define RTC_CNTL_DEBUG_SEL1_S  12
1802 /* RTC_CNTL_DEBUG_SEL0 :  ;bitpos:[11:7] ;default: 5'd0 ; */
1803 /*description: Need add desc.*/
1804 #define RTC_CNTL_DEBUG_SEL0    0x0000001F
1805 #define RTC_CNTL_DEBUG_SEL0_M  ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S))
1806 #define RTC_CNTL_DEBUG_SEL0_V  0x1F
1807 #define RTC_CNTL_DEBUG_SEL0_S  7
1808 /* RTC_CNTL_DEBUG_BIT_SEL :  ;bitpos:[6:2] ;default: 5'd0 ; */
1809 /*description: Need add desc.*/
1810 #define RTC_CNTL_DEBUG_BIT_SEL    0x0000001F
1811 #define RTC_CNTL_DEBUG_BIT_SEL_M  ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
1812 #define RTC_CNTL_DEBUG_BIT_SEL_V  0x1F
1813 #define RTC_CNTL_DEBUG_BIT_SEL_S  2
1814 /* RTC_CNTL_DEBUG_12M_NO_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
1815 /*description: Need add desc.*/
1816 #define RTC_CNTL_DEBUG_12M_NO_GATING    (BIT(1))
1817 #define RTC_CNTL_DEBUG_12M_NO_GATING_M  (BIT(1))
1818 #define RTC_CNTL_DEBUG_12M_NO_GATING_V  0x1
1819 #define RTC_CNTL_DEBUG_12M_NO_GATING_S  1
1820 
1821 #define RTC_CNTL_DBG_MAP_REG          (DR_REG_RTCCNTL_BASE + 0x104)
1822 /* RTC_CNTL_GPIO_PIN0_FUN_SEL :  ;bitpos:[31:28] ;default: 4'd0 ; */
1823 /*description: Need add desc.*/
1824 #define RTC_CNTL_GPIO_PIN0_FUN_SEL    0x0000000F
1825 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S))
1826 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_V  0xF
1827 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_S  28
1828 /* RTC_CNTL_GPIO_PIN1_FUN_SEL :  ;bitpos:[27:24] ;default: 4'd0 ; */
1829 /*description: Need add desc.*/
1830 #define RTC_CNTL_GPIO_PIN1_FUN_SEL    0x0000000F
1831 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
1832 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_V  0xF
1833 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_S  24
1834 /* RTC_CNTL_GPIO_PIN2_FUN_SEL :  ;bitpos:[23:20] ;default: 4'd0 ; */
1835 /*description: Need add desc.*/
1836 #define RTC_CNTL_GPIO_PIN2_FUN_SEL    0x0000000F
1837 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S))
1838 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_V  0xF
1839 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_S  20
1840 /* RTC_CNTL_GPIO_PIN3_FUN_SEL :  ;bitpos:[19:16] ;default: 4'd0 ; */
1841 /*description: Need add desc.*/
1842 #define RTC_CNTL_GPIO_PIN3_FUN_SEL    0x0000000F
1843 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S))
1844 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_V  0xF
1845 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_S  16
1846 /* RTC_CNTL_GPIO_PIN4_FUN_SEL :  ;bitpos:[15:12] ;default: 4'd0 ; */
1847 /*description: Need add desc.*/
1848 #define RTC_CNTL_GPIO_PIN4_FUN_SEL    0x0000000F
1849 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
1850 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_V  0xF
1851 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_S  12
1852 /* RTC_CNTL_GPIO_PIN5_FUN_SEL :  ;bitpos:[11:8] ;default: 4'd0 ; */
1853 /*description: Need add desc.*/
1854 #define RTC_CNTL_GPIO_PIN5_FUN_SEL    0x0000000F
1855 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S))
1856 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_V  0xF
1857 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_S  8
1858 /* RTC_CNTL_GPIO_PIN0_MUX_SEL :  ;bitpos:[7] ;default: 1'b0 ; */
1859 /*description: Need add desc.*/
1860 #define RTC_CNTL_GPIO_PIN0_MUX_SEL    (BIT(7))
1861 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_M  (BIT(7))
1862 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_V  0x1
1863 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_S  7
1864 /* RTC_CNTL_GPIO_PIN1_MUX_SEL :  ;bitpos:[6] ;default: 1'b0 ; */
1865 /*description: Need add desc.*/
1866 #define RTC_CNTL_GPIO_PIN1_MUX_SEL    (BIT(6))
1867 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_M  (BIT(6))
1868 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_V  0x1
1869 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_S  6
1870 /* RTC_CNTL_GPIO_PIN2_MUX_SEL :  ;bitpos:[5] ;default: 1'b0 ; */
1871 /*description: Need add desc.*/
1872 #define RTC_CNTL_GPIO_PIN2_MUX_SEL    (BIT(5))
1873 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_M  (BIT(5))
1874 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_V  0x1
1875 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_S  5
1876 /* RTC_CNTL_GPIO_PIN3_MUX_SEL :  ;bitpos:[4] ;default: 1'b0 ; */
1877 /*description: Need add desc.*/
1878 #define RTC_CNTL_GPIO_PIN3_MUX_SEL    (BIT(4))
1879 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_M  (BIT(4))
1880 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_V  0x1
1881 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_S  4
1882 /* RTC_CNTL_GPIO_PIN4_MUX_SEL :  ;bitpos:[3] ;default: 1'b0 ; */
1883 /*description: Need add desc.*/
1884 #define RTC_CNTL_GPIO_PIN4_MUX_SEL    (BIT(3))
1885 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_M  (BIT(3))
1886 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_V  0x1
1887 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_S  3
1888 /* RTC_CNTL_GPIO_PIN5_MUX_SEL :  ;bitpos:[2] ;default: 1'b0 ; */
1889 /*description: Need add desc.*/
1890 #define RTC_CNTL_GPIO_PIN5_MUX_SEL    (BIT(2))
1891 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_M  (BIT(2))
1892 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_V  0x1
1893 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_S  2
1894 
1895 #define RTC_CNTL_SENSOR_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x108)
1896 /* RTC_CNTL_FORCE_XPD_SAR :  ;bitpos:[31:30] ;default: 2'b0 ; */
1897 /*description: Need add desc.*/
1898 #define RTC_CNTL_FORCE_XPD_SAR    0x00000003
1899 #define RTC_CNTL_FORCE_XPD_SAR_M  ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
1900 #define RTC_CNTL_FORCE_XPD_SAR_V  0x3
1901 #define RTC_CNTL_FORCE_XPD_SAR_S  30
1902 /* RTC_CNTL_SAR2_PWDET_CCT :  ;bitpos:[29:27] ;default: 3'd0 ; */
1903 /*description: Need add desc.*/
1904 #define RTC_CNTL_SAR2_PWDET_CCT    0x00000007
1905 #define RTC_CNTL_SAR2_PWDET_CCT_M  ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S))
1906 #define RTC_CNTL_SAR2_PWDET_CCT_V  0x7
1907 #define RTC_CNTL_SAR2_PWDET_CCT_S  27
1908 
1909 #define RTC_CNTL_DBG_SAR_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x10C)
1910 /* RTC_CNTL_SAR_DEBUG_SEL :  ;bitpos:[31:27] ;default: 5'd0 ; */
1911 /*description: Need add desc.*/
1912 #define RTC_CNTL_SAR_DEBUG_SEL    0x0000001F
1913 #define RTC_CNTL_SAR_DEBUG_SEL_M  ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S))
1914 #define RTC_CNTL_SAR_DEBUG_SEL_V  0x1F
1915 #define RTC_CNTL_SAR_DEBUG_SEL_S  27
1916 
1917 #define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x1FC)
1918 /* RTC_CNTL_DATE :  ;bitpos:[27:0] ;default: 28'h2107190 ; */
1919 /*description: Need add desc.*/
1920 #define RTC_CNTL_DATE    0x0FFFFFFF
1921 #define RTC_CNTL_DATE_M  ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
1922 #define RTC_CNTL_DATE_V  0xFFFFFFF
1923 #define RTC_CNTL_DATE_S  0
1924 
1925 
1926 #ifdef __cplusplus
1927 }
1928 #endif
1929 
1930 
1931 
1932 #endif /*_SOC_RTC_CNTL_REG_H_ */
1933