Searched refs:RTC_CNTL_DIG_PAD_HOLD_REG (Results 1 – 8 of 8) sorted by relevance
| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | gpio_ll.h | 480 SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_en()
491 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_dis()
509 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - 21)); in gpio_ll_is_digital_io_hold()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | gpio_ll.h | 433 SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_en()
448 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_dis()
467 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num)); in gpio_ll_is_digital_io_hold()
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| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | gpio_ll.h | 454 SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_en()
465 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_dis()
483 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - 21)); in gpio_ll_is_digital_io_hold()
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | gpio_ll.h | 456 SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_en()
471 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); in gpio_ll_hold_dis()
490 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num)); in gpio_ll_is_digital_io_hold()
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | rtc_cntl_reg.h | 1427 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xC8) macro
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | rtc_cntl_reg.h | 2043 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) macro
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| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | rtc_cntl_reg.h | 2625 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) macro
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | rtc_cntl_reg.h | 2533 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xDC) macro
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