Home
last modified time | relevance | path

Searched refs:RTC_CNTL_DIG_CLK8M_EN (Results 1 – 12 of 12) sorted by relevance

/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c31 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in soc_random_enable()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Drtc_cntl_ll.h44 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in rtc_cntl_ll_enable_cpu_retention()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32s2.c36 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in bootloader_random_enable()
Dbootloader_random_esp32s3.c23 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in bootloader_random_enable()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h46 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in rtc_cntl_ll_enable_cpu_retention_clock()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c24 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in soc_random_enable()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Drtc_cntl_ll.h118 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable internal 20 MHz clock */ in rtc_cntl_ll_enable_cpu_retention_clock()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h718 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h940 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h1049 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h1264 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h1358 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) macro