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Searched refs:RTC_CNTL_CK8M_DIV_SEL (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dclk_tree_ll.h478 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
489 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dclk_tree_ll.h588 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
599 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dclk_tree_ll.h586 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
597 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dclk_tree_ll.h701 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
712 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dclk_tree_ll.h784 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
794 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h712 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h928 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h1043 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h1258 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h1352 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 macro