Searched refs:REG_SPI_BASE (Results 1 – 12 of 12) sorted by relevance
19 #define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1… macro21 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)135 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)139 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)226 #define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC)240 #define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10)260 #define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14)328 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18)364 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C)533 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20)[all …]
15 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000)30 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x004)38 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008)152 #define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x00C)188 #define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x010)218 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x014)255 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x018)467 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x01C)483 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x020)498 #define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x024)[all …]
28 #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2… macro
15 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)38 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)46 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)139 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC)176 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)312 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)350 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)373 #define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C)384 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)468 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)[all …]
26 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one… macro
15 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)38 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)46 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)160 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC)197 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)347 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)385 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)408 #define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C)419 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)540 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)[all …]
34 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one… macro
23 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)46 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)54 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)168 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC)205 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)355 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)393 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)416 #define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C)427 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)548 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)[all …]
37 #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2… macro
17 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)46 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)58 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)191 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)235 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)406 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)452 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)481 #define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)496 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)637 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)[all …]
26 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only on… macro
