1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** PMU_HP_ACTIVE_DIG_POWER_REG register 15 * need_des 16 */ 17 #define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) 18 /** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; 19 * need_des 20 */ 21 #define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) 22 #define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) 23 #define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U 24 #define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 25 /** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; 26 * need_des 27 */ 28 #define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) 29 #define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) 30 #define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U 31 #define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 32 /** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; 33 * need_des 34 */ 35 #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN 0x0000000FU 36 #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) 37 #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU 38 #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 39 /** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; 40 * need_des 41 */ 42 #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) 43 #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) 44 #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U 45 #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 46 /** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; 47 * need_des 48 */ 49 #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) 50 #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) 51 #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U 52 #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 53 /** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; 54 * need_des 55 */ 56 #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) 57 #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) 58 #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U 59 #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 60 /** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; 61 * need_des 62 */ 63 #define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) 64 #define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) 65 #define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U 66 #define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 67 68 /** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register 69 * need_des 70 */ 71 #define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) 72 /** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; 73 * need_des 74 */ 75 #define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU 76 #define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) 77 #define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU 78 #define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 79 80 /** PMU_HP_ACTIVE_ICG_HP_APB_REG register 81 * need_des 82 */ 83 #define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) 84 /** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; 85 * need_des 86 */ 87 #define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU 88 #define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) 89 #define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU 90 #define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 91 92 /** PMU_HP_ACTIVE_ICG_MODEM_REG register 93 * need_des 94 */ 95 #define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) 96 /** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; 97 * need_des 98 */ 99 #define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U 100 #define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) 101 #define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U 102 #define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 103 104 /** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register 105 * need_des 106 */ 107 #define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) 108 /** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; 109 * need_des 110 */ 111 #define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) 112 #define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) 113 #define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U 114 #define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 115 /** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; 116 * need_des 117 */ 118 #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) 119 #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) 120 #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U 121 #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 122 /** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; 123 * need_des 124 */ 125 #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) 126 #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) 127 #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U 128 #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 129 /** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; 130 * need_des 131 */ 132 #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) 133 #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) 134 #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U 135 #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 136 /** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; 137 * need_des 138 */ 139 #define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) 140 #define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) 141 #define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U 142 #define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 143 /** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; 144 * need_des 145 */ 146 #define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) 147 #define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) 148 #define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U 149 #define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 150 151 /** PMU_HP_ACTIVE_HP_CK_POWER_REG register 152 * need_des 153 */ 154 #define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) 155 /** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; 156 * need_des 157 */ 158 #define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) 159 #define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) 160 #define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U 161 #define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 162 /** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; 163 * need_des 164 */ 165 #define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) 166 #define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) 167 #define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U 168 #define PMU_HP_ACTIVE_I2C_RETENTION_S 27 169 /** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; 170 * need_des 171 */ 172 #define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) 173 #define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) 174 #define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U 175 #define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 176 /** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; 177 * need_des 178 */ 179 #define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) 180 #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) 181 #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U 182 #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 183 /** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; 184 * need_des 185 */ 186 #define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) 187 #define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) 188 #define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U 189 #define PMU_HP_ACTIVE_XPD_BBPLL_S 30 190 191 /** PMU_HP_ACTIVE_BIAS_REG register 192 * need_des 193 */ 194 #define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) 195 /** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; 196 * need_des 197 */ 198 #define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) 199 #define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) 200 #define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U 201 #define PMU_HP_ACTIVE_XPD_BIAS_S 25 202 /** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; 203 * need_des 204 */ 205 #define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU 206 #define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) 207 #define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU 208 #define PMU_HP_ACTIVE_DBG_ATTEN_S 26 209 /** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; 210 * need_des 211 */ 212 #define PMU_HP_ACTIVE_PD_CUR (BIT(30)) 213 #define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) 214 #define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U 215 #define PMU_HP_ACTIVE_PD_CUR_S 30 216 /** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; 217 * need_des 218 */ 219 #define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) 220 #define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) 221 #define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U 222 #define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 223 224 /** PMU_HP_ACTIVE_BACKUP_REG register 225 * need_des 226 */ 227 #define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) 228 /** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; 229 * need_des 230 */ 231 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U 232 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) 233 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U 234 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 235 /** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; 236 * need_des 237 */ 238 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U 239 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) 240 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U 241 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 242 /** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; 243 * need_des 244 */ 245 #define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) 246 #define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) 247 #define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U 248 #define PMU_HP_ACTIVE_RETENTION_MODE_S 10 249 /** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; 250 * need_des 251 */ 252 #define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) 253 #define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) 254 #define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U 255 #define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 256 /** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; 257 * need_des 258 */ 259 #define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) 260 #define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) 261 #define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U 262 #define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 263 /** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; 264 * need_des 265 */ 266 #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U 267 #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) 268 #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U 269 #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 270 /** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; 271 * need_des 272 */ 273 #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U 274 #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) 275 #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U 276 #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 277 /** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; 278 * need_des 279 */ 280 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U 281 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) 282 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U 283 #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 284 /** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; 285 * need_des 286 */ 287 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U 288 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) 289 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U 290 #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 291 /** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; 292 * need_des 293 */ 294 #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) 295 #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) 296 #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U 297 #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 298 /** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; 299 * need_des 300 */ 301 #define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) 302 #define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) 303 #define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U 304 #define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 305 306 /** PMU_HP_ACTIVE_BACKUP_CLK_REG register 307 * need_des 308 */ 309 #define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) 310 /** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; 311 * need_des 312 */ 313 #define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU 314 #define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) 315 #define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU 316 #define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 317 318 /** PMU_HP_ACTIVE_SYSCLK_REG register 319 * need_des 320 */ 321 #define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) 322 /** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; 323 * need_des 324 */ 325 #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) 326 #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) 327 #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U 328 #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 329 /** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; 330 * need_des 331 */ 332 #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) 333 #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) 334 #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U 335 #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 336 /** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; 337 * need_des 338 */ 339 #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) 340 #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) 341 #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U 342 #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 343 /** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; 344 * need_des 345 */ 346 #define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) 347 #define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) 348 #define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U 349 #define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 350 /** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; 351 * need_des 352 */ 353 #define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U 354 #define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) 355 #define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U 356 #define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 357 358 /** PMU_HP_ACTIVE_HP_REGULATOR0_REG register 359 * need_des 360 */ 361 #define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) 362 /** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; 363 * need_des 364 */ 365 #define PMU_LP_DBIAS_VOL 0x0000001FU 366 #define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) 367 #define PMU_LP_DBIAS_VOL_V 0x0000001FU 368 #define PMU_LP_DBIAS_VOL_S 4 369 /** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; 370 * need_des 371 */ 372 #define PMU_HP_DBIAS_VOL 0x0000001FU 373 #define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) 374 #define PMU_HP_DBIAS_VOL_V 0x0000001FU 375 #define PMU_HP_DBIAS_VOL_S 9 376 /** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; 377 * need_des 378 */ 379 #define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) 380 #define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) 381 #define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U 382 #define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 383 /** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; 384 * need_des 385 */ 386 #define PMU_DIG_DBIAS_INIT (BIT(15)) 387 #define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) 388 #define PMU_DIG_DBIAS_INIT_V 0x00000001U 389 #define PMU_DIG_DBIAS_INIT_S 15 390 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; 391 * need_des 392 */ 393 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) 394 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) 395 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U 396 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 397 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; 398 * need_des 399 */ 400 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) 401 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) 402 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U 403 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 404 /** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; 405 * need_des 406 */ 407 #define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) 408 #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) 409 #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U 410 #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 411 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; 412 * need_des 413 */ 414 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU 415 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) 416 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU 417 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 418 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; 419 * need_des 420 */ 421 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU 422 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) 423 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU 424 #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 425 /** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; 426 * need_des 427 */ 428 #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU 429 #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) 430 #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU 431 #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 432 433 /** PMU_HP_ACTIVE_HP_REGULATOR1_REG register 434 * need_des 435 */ 436 #define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) 437 /** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; 438 * need_des 439 */ 440 #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU 441 #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) 442 #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x00FFFFFFU 443 #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 444 445 /** PMU_HP_ACTIVE_XTAL_REG register 446 * need_des 447 */ 448 #define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) 449 /** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; 450 * need_des 451 */ 452 #define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) 453 #define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) 454 #define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U 455 #define PMU_HP_ACTIVE_XPD_XTAL_S 31 456 457 /** PMU_HP_MODEM_DIG_POWER_REG register 458 * need_des 459 */ 460 #define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) 461 /** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; 462 * need_des 463 */ 464 #define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) 465 #define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) 466 #define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U 467 #define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 468 /** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; 469 * need_des 470 */ 471 #define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) 472 #define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) 473 #define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U 474 #define PMU_HP_MODEM_HP_MEM_DSLP_S 22 475 /** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; 476 * need_des 477 */ 478 #define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU 479 #define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) 480 #define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU 481 #define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 482 /** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; 483 * need_des 484 */ 485 #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) 486 #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) 487 #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U 488 #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 489 /** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; 490 * need_des 491 */ 492 #define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) 493 #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) 494 #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U 495 #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 496 /** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; 497 * need_des 498 */ 499 #define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) 500 #define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) 501 #define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U 502 #define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 503 /** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; 504 * need_des 505 */ 506 #define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) 507 #define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) 508 #define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U 509 #define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 510 511 /** PMU_HP_MODEM_ICG_HP_FUNC_REG register 512 * need_des 513 */ 514 #define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) 515 /** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; 516 * need_des 517 */ 518 #define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU 519 #define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) 520 #define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU 521 #define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 522 523 /** PMU_HP_MODEM_ICG_HP_APB_REG register 524 * need_des 525 */ 526 #define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) 527 /** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; 528 * need_des 529 */ 530 #define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU 531 #define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) 532 #define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU 533 #define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 534 535 /** PMU_HP_MODEM_ICG_MODEM_REG register 536 * need_des 537 */ 538 #define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) 539 /** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; 540 * need_des 541 */ 542 #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U 543 #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) 544 #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U 545 #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 546 547 /** PMU_HP_MODEM_HP_SYS_CNTL_REG register 548 * need_des 549 */ 550 #define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) 551 /** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; 552 * need_des 553 */ 554 #define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) 555 #define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) 556 #define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U 557 #define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 558 /** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; 559 * need_des 560 */ 561 #define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) 562 #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) 563 #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U 564 #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 565 /** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; 566 * need_des 567 */ 568 #define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) 569 #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) 570 #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U 571 #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 572 /** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; 573 * need_des 574 */ 575 #define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) 576 #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) 577 #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U 578 #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 579 /** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; 580 * need_des 581 */ 582 #define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) 583 #define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) 584 #define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U 585 #define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 586 /** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; 587 * need_des 588 */ 589 #define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) 590 #define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) 591 #define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U 592 #define PMU_HP_MODEM_DIG_CPU_STALL_S 29 593 594 /** PMU_HP_MODEM_HP_CK_POWER_REG register 595 * need_des 596 */ 597 #define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) 598 /** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; 599 * need_des 600 */ 601 #define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) 602 #define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) 603 #define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U 604 #define PMU_HP_MODEM_I2C_ISO_EN_S 26 605 /** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; 606 * need_des 607 */ 608 #define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) 609 #define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) 610 #define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U 611 #define PMU_HP_MODEM_I2C_RETENTION_S 27 612 /** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; 613 * need_des 614 */ 615 #define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) 616 #define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) 617 #define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U 618 #define PMU_HP_MODEM_XPD_BB_I2C_S 28 619 /** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; 620 * need_des 621 */ 622 #define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) 623 #define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) 624 #define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U 625 #define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 626 /** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; 627 * need_des 628 */ 629 #define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) 630 #define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) 631 #define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U 632 #define PMU_HP_MODEM_XPD_BBPLL_S 30 633 634 /** PMU_HP_MODEM_BIAS_REG register 635 * need_des 636 */ 637 #define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) 638 /** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; 639 * need_des 640 */ 641 #define PMU_HP_MODEM_XPD_BIAS (BIT(25)) 642 #define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) 643 #define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U 644 #define PMU_HP_MODEM_XPD_BIAS_S 25 645 /** PMU_HP_MODEM_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; 646 * need_des 647 */ 648 #define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU 649 #define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) 650 #define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU 651 #define PMU_HP_MODEM_DBG_ATTEN_S 26 652 /** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; 653 * need_des 654 */ 655 #define PMU_HP_MODEM_PD_CUR (BIT(30)) 656 #define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) 657 #define PMU_HP_MODEM_PD_CUR_V 0x00000001U 658 #define PMU_HP_MODEM_PD_CUR_S 30 659 /** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; 660 * need_des 661 */ 662 #define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) 663 #define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) 664 #define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U 665 #define PMU_HP_MODEM_BIAS_SLEEP_S 31 666 667 /** PMU_HP_MODEM_BACKUP_REG register 668 * need_des 669 */ 670 #define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) 671 /** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; 672 * need_des 673 */ 674 #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U 675 #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) 676 #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U 677 #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 678 /** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; 679 * need_des 680 */ 681 #define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) 682 #define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) 683 #define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U 684 #define PMU_HP_MODEM_RETENTION_MODE_S 10 685 /** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; 686 * need_des 687 */ 688 #define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) 689 #define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) 690 #define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U 691 #define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 692 /** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; 693 * need_des 694 */ 695 #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U 696 #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) 697 #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U 698 #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 699 /** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; 700 * need_des 701 */ 702 #define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U 703 #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) 704 #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U 705 #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 706 /** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; 707 * need_des 708 */ 709 #define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) 710 #define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) 711 #define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U 712 #define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 713 714 /** PMU_HP_MODEM_BACKUP_CLK_REG register 715 * need_des 716 */ 717 #define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) 718 /** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; 719 * need_des 720 */ 721 #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU 722 #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) 723 #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU 724 #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 725 726 /** PMU_HP_MODEM_SYSCLK_REG register 727 * need_des 728 */ 729 #define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) 730 /** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; 731 * need_des 732 */ 733 #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) 734 #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) 735 #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U 736 #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 737 /** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; 738 * need_des 739 */ 740 #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) 741 #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) 742 #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U 743 #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 744 /** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; 745 * need_des 746 */ 747 #define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) 748 #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) 749 #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U 750 #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 751 /** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; 752 * need_des 753 */ 754 #define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) 755 #define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) 756 #define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U 757 #define PMU_HP_MODEM_ICG_SLP_SEL_S 29 758 /** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; 759 * need_des 760 */ 761 #define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U 762 #define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) 763 #define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U 764 #define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 765 766 /** PMU_HP_MODEM_HP_REGULATOR0_REG register 767 * need_des 768 */ 769 #define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) 770 /** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; 771 * need_des 772 */ 773 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) 774 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) 775 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U 776 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 777 /** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; 778 * need_des 779 */ 780 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) 781 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) 782 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U 783 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 784 /** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; 785 * need_des 786 */ 787 #define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) 788 #define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) 789 #define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U 790 #define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 791 /** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; 792 * need_des 793 */ 794 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU 795 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) 796 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU 797 #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 798 /** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; 799 * need_des 800 */ 801 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU 802 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) 803 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU 804 #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 805 /** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; 806 * need_des 807 */ 808 #define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU 809 #define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) 810 #define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU 811 #define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 812 813 /** PMU_HP_MODEM_HP_REGULATOR1_REG register 814 * need_des 815 */ 816 #define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) 817 /** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; 818 * need_des 819 */ 820 #define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU 821 #define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) 822 #define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU 823 #define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 824 825 /** PMU_HP_MODEM_XTAL_REG register 826 * need_des 827 */ 828 #define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) 829 /** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; 830 * need_des 831 */ 832 #define PMU_HP_MODEM_XPD_XTAL (BIT(31)) 833 #define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) 834 #define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U 835 #define PMU_HP_MODEM_XPD_XTAL_S 31 836 837 /** PMU_HP_SLEEP_DIG_POWER_REG register 838 * need_des 839 */ 840 #define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) 841 /** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; 842 * need_des 843 */ 844 #define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) 845 #define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) 846 #define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U 847 #define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 848 /** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; 849 * need_des 850 */ 851 #define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) 852 #define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) 853 #define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U 854 #define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 855 /** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; 856 * need_des 857 */ 858 #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN 0x0000000FU 859 #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) 860 #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU 861 #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 862 /** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; 863 * need_des 864 */ 865 #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) 866 #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) 867 #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U 868 #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 869 /** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; 870 * need_des 871 */ 872 #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) 873 #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) 874 #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U 875 #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 876 /** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; 877 * need_des 878 */ 879 #define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) 880 #define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) 881 #define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U 882 #define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 883 /** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; 884 * need_des 885 */ 886 #define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) 887 #define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) 888 #define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U 889 #define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 890 891 /** PMU_HP_SLEEP_ICG_HP_FUNC_REG register 892 * need_des 893 */ 894 #define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) 895 /** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; 896 * need_des 897 */ 898 #define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU 899 #define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) 900 #define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU 901 #define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 902 903 /** PMU_HP_SLEEP_ICG_HP_APB_REG register 904 * need_des 905 */ 906 #define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) 907 /** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; 908 * need_des 909 */ 910 #define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU 911 #define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) 912 #define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU 913 #define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 914 915 /** PMU_HP_SLEEP_ICG_MODEM_REG register 916 * need_des 917 */ 918 #define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) 919 /** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; 920 * need_des 921 */ 922 #define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U 923 #define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) 924 #define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U 925 #define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 926 927 /** PMU_HP_SLEEP_HP_SYS_CNTL_REG register 928 * need_des 929 */ 930 #define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) 931 /** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; 932 * need_des 933 */ 934 #define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) 935 #define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) 936 #define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U 937 #define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 938 /** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; 939 * need_des 940 */ 941 #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) 942 #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) 943 #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U 944 #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 945 /** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; 946 * need_des 947 */ 948 #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) 949 #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) 950 #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U 951 #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 952 /** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; 953 * need_des 954 */ 955 #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) 956 #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) 957 #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U 958 #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 959 /** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; 960 * need_des 961 */ 962 #define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) 963 #define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) 964 #define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U 965 #define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 966 /** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; 967 * need_des 968 */ 969 #define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) 970 #define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) 971 #define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U 972 #define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 973 974 /** PMU_HP_SLEEP_HP_CK_POWER_REG register 975 * need_des 976 */ 977 #define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) 978 /** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; 979 * need_des 980 */ 981 #define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) 982 #define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) 983 #define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U 984 #define PMU_HP_SLEEP_I2C_ISO_EN_S 26 985 /** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0; 986 * need_des 987 */ 988 #define PMU_HP_SLEEP_I2C_RETENTION (BIT(27)) 989 #define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) 990 #define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U 991 #define PMU_HP_SLEEP_I2C_RETENTION_S 27 992 /** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; 993 * need_des 994 */ 995 #define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) 996 #define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) 997 #define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U 998 #define PMU_HP_SLEEP_XPD_BB_I2C_S 28 999 /** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; 1000 * need_des 1001 */ 1002 #define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) 1003 #define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) 1004 #define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U 1005 #define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 1006 /** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; 1007 * need_des 1008 */ 1009 #define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) 1010 #define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) 1011 #define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U 1012 #define PMU_HP_SLEEP_XPD_BBPLL_S 30 1013 1014 /** PMU_HP_SLEEP_BIAS_REG register 1015 * need_des 1016 */ 1017 #define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) 1018 /** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; 1019 * need_des 1020 */ 1021 #define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) 1022 #define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) 1023 #define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U 1024 #define PMU_HP_SLEEP_XPD_BIAS_S 25 1025 /** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; 1026 * need_des 1027 */ 1028 #define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU 1029 #define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) 1030 #define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU 1031 #define PMU_HP_SLEEP_DBG_ATTEN_S 26 1032 /** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; 1033 * need_des 1034 */ 1035 #define PMU_HP_SLEEP_PD_CUR (BIT(30)) 1036 #define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) 1037 #define PMU_HP_SLEEP_PD_CUR_V 0x00000001U 1038 #define PMU_HP_SLEEP_PD_CUR_S 30 1039 /** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; 1040 * need_des 1041 */ 1042 #define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) 1043 #define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) 1044 #define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U 1045 #define PMU_HP_SLEEP_BIAS_SLEEP_S 31 1046 1047 /** PMU_HP_SLEEP_BACKUP_REG register 1048 * need_des 1049 */ 1050 #define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) 1051 /** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; 1052 * need_des 1053 */ 1054 #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U 1055 #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) 1056 #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U 1057 #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 1058 /** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; 1059 * need_des 1060 */ 1061 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U 1062 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) 1063 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U 1064 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 1065 /** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; 1066 * need_des 1067 */ 1068 #define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) 1069 #define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) 1070 #define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U 1071 #define PMU_HP_SLEEP_RETENTION_MODE_S 10 1072 /** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; 1073 * need_des 1074 */ 1075 #define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) 1076 #define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) 1077 #define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U 1078 #define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 1079 /** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; 1080 * need_des 1081 */ 1082 #define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) 1083 #define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) 1084 #define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U 1085 #define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 1086 /** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; 1087 * need_des 1088 */ 1089 #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U 1090 #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) 1091 #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U 1092 #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 1093 /** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; 1094 * need_des 1095 */ 1096 #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U 1097 #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) 1098 #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U 1099 #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 1100 /** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; 1101 * need_des 1102 */ 1103 #define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U 1104 #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) 1105 #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U 1106 #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 1107 /** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; 1108 * need_des 1109 */ 1110 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U 1111 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) 1112 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U 1113 #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 1114 /** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; 1115 * need_des 1116 */ 1117 #define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) 1118 #define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) 1119 #define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U 1120 #define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 1121 /** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; 1122 * need_des 1123 */ 1124 #define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) 1125 #define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) 1126 #define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U 1127 #define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 1128 1129 /** PMU_HP_SLEEP_BACKUP_CLK_REG register 1130 * need_des 1131 */ 1132 #define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) 1133 /** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; 1134 * need_des 1135 */ 1136 #define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU 1137 #define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) 1138 #define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU 1139 #define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 1140 1141 /** PMU_HP_SLEEP_SYSCLK_REG register 1142 * need_des 1143 */ 1144 #define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) 1145 /** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; 1146 * need_des 1147 */ 1148 #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) 1149 #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) 1150 #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U 1151 #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 1152 /** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; 1153 * need_des 1154 */ 1155 #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) 1156 #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) 1157 #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U 1158 #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 1159 /** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; 1160 * need_des 1161 */ 1162 #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) 1163 #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) 1164 #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U 1165 #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 1166 /** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; 1167 * need_des 1168 */ 1169 #define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) 1170 #define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) 1171 #define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U 1172 #define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 1173 /** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; 1174 * need_des 1175 */ 1176 #define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U 1177 #define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) 1178 #define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U 1179 #define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 1180 1181 /** PMU_HP_SLEEP_HP_REGULATOR0_REG register 1182 * need_des 1183 */ 1184 #define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) 1185 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; 1186 * need_des 1187 */ 1188 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) 1189 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) 1190 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U 1191 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 1192 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; 1193 * need_des 1194 */ 1195 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) 1196 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) 1197 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U 1198 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 1199 /** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; 1200 * need_des 1201 */ 1202 #define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) 1203 #define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) 1204 #define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U 1205 #define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 1206 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; 1207 * need_des 1208 */ 1209 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU 1210 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) 1211 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU 1212 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 1213 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; 1214 * need_des 1215 */ 1216 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU 1217 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) 1218 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU 1219 #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 1220 /** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; 1221 * need_des 1222 */ 1223 #define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU 1224 #define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) 1225 #define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU 1226 #define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 1227 1228 /** PMU_HP_SLEEP_HP_REGULATOR1_REG register 1229 * need_des 1230 */ 1231 #define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) 1232 /** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; 1233 * need_des 1234 */ 1235 #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU 1236 #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) 1237 #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x00FFFFFFU 1238 #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 1239 1240 /** PMU_HP_SLEEP_XTAL_REG register 1241 * need_des 1242 */ 1243 #define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) 1244 /** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; 1245 * need_des 1246 */ 1247 #define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) 1248 #define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) 1249 #define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U 1250 #define PMU_HP_SLEEP_XPD_XTAL_S 31 1251 1252 /** PMU_HP_SLEEP_LP_REGULATOR0_REG register 1253 * need_des 1254 */ 1255 #define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) 1256 /** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; 1257 * need_des 1258 */ 1259 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) 1260 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) 1261 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U 1262 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 1263 /** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; 1264 * need_des 1265 */ 1266 #define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) 1267 #define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) 1268 #define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U 1269 #define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 1270 /** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; 1271 * need_des 1272 */ 1273 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU 1274 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) 1275 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU 1276 #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 1277 /** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; 1278 * need_des 1279 */ 1280 #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU 1281 #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) 1282 #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU 1283 #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 1284 1285 /** PMU_HP_SLEEP_LP_REGULATOR1_REG register 1286 * need_des 1287 */ 1288 #define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) 1289 /** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; 1290 * need_des 1291 */ 1292 #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU 1293 #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) 1294 #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU 1295 #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 1296 1297 /** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register 1298 * need_des 1299 */ 1300 #define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) 1301 /** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; 1302 * need_des 1303 */ 1304 #define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU 1305 #define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) 1306 #define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU 1307 #define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 1308 1309 /** PMU_HP_SLEEP_LP_DIG_POWER_REG register 1310 * need_des 1311 */ 1312 #define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) 1313 /** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; 1314 * need_des 1315 */ 1316 #define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) 1317 #define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) 1318 #define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U 1319 #define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 1320 /** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; 1321 * need_des 1322 */ 1323 #define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) 1324 #define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) 1325 #define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U 1326 #define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 1327 1328 /** PMU_HP_SLEEP_LP_CK_POWER_REG register 1329 * need_des 1330 */ 1331 #define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) 1332 /** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; 1333 * need_des 1334 */ 1335 #define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) 1336 #define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) 1337 #define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U 1338 #define PMU_HP_SLEEP_XPD_XTAL32K_S 28 1339 /** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; 1340 * need_des 1341 */ 1342 #define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) 1343 #define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) 1344 #define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U 1345 #define PMU_HP_SLEEP_XPD_RC32K_S 29 1346 /** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; 1347 * need_des 1348 */ 1349 #define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) 1350 #define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) 1351 #define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U 1352 #define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 1353 /** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; 1354 * need_des 1355 */ 1356 #define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) 1357 #define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) 1358 #define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U 1359 #define PMU_HP_SLEEP_PD_OSC_CLK_S 31 1360 1361 /** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register 1362 * need_des 1363 */ 1364 #define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) 1365 /** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; 1366 * need_des 1367 */ 1368 #define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU 1369 #define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) 1370 #define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU 1371 #define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 1372 1373 /** PMU_LP_SLEEP_LP_REGULATOR0_REG register 1374 * need_des 1375 */ 1376 #define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) 1377 /** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; 1378 * need_des 1379 */ 1380 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) 1381 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) 1382 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U 1383 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 1384 /** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; 1385 * need_des 1386 */ 1387 #define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) 1388 #define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) 1389 #define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U 1390 #define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 1391 /** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; 1392 * need_des 1393 */ 1394 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU 1395 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) 1396 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU 1397 #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 1398 /** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; 1399 * need_des 1400 */ 1401 #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU 1402 #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) 1403 #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU 1404 #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 1405 1406 /** PMU_LP_SLEEP_LP_REGULATOR1_REG register 1407 * need_des 1408 */ 1409 #define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) 1410 /** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; 1411 * need_des 1412 */ 1413 #define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU 1414 #define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) 1415 #define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU 1416 #define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 1417 1418 /** PMU_LP_SLEEP_XTAL_REG register 1419 * need_des 1420 */ 1421 #define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) 1422 /** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; 1423 * need_des 1424 */ 1425 #define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) 1426 #define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) 1427 #define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U 1428 #define PMU_LP_SLEEP_XPD_XTAL_S 31 1429 1430 /** PMU_LP_SLEEP_LP_DIG_POWER_REG register 1431 * need_des 1432 */ 1433 #define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) 1434 /** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; 1435 * need_des 1436 */ 1437 #define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) 1438 #define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) 1439 #define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U 1440 #define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 1441 /** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; 1442 * need_des 1443 */ 1444 #define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) 1445 #define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) 1446 #define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U 1447 #define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 1448 1449 /** PMU_LP_SLEEP_LP_CK_POWER_REG register 1450 * need_des 1451 */ 1452 #define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) 1453 /** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; 1454 * need_des 1455 */ 1456 #define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) 1457 #define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) 1458 #define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U 1459 #define PMU_LP_SLEEP_XPD_XTAL32K_S 28 1460 /** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; 1461 * need_des 1462 */ 1463 #define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) 1464 #define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) 1465 #define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U 1466 #define PMU_LP_SLEEP_XPD_RC32K_S 29 1467 /** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; 1468 * need_des 1469 */ 1470 #define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) 1471 #define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) 1472 #define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U 1473 #define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 1474 /** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; 1475 * need_des 1476 */ 1477 #define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) 1478 #define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) 1479 #define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U 1480 #define PMU_LP_SLEEP_PD_OSC_CLK_S 31 1481 1482 /** PMU_LP_SLEEP_BIAS_REG register 1483 * need_des 1484 */ 1485 #define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) 1486 /** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; 1487 * need_des 1488 */ 1489 #define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) 1490 #define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) 1491 #define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U 1492 #define PMU_LP_SLEEP_XPD_BIAS_S 25 1493 /** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; 1494 * need_des 1495 */ 1496 #define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU 1497 #define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) 1498 #define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU 1499 #define PMU_LP_SLEEP_DBG_ATTEN_S 26 1500 /** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; 1501 * need_des 1502 */ 1503 #define PMU_LP_SLEEP_PD_CUR (BIT(30)) 1504 #define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) 1505 #define PMU_LP_SLEEP_PD_CUR_V 0x00000001U 1506 #define PMU_LP_SLEEP_PD_CUR_S 30 1507 /** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; 1508 * need_des 1509 */ 1510 #define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) 1511 #define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) 1512 #define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U 1513 #define PMU_LP_SLEEP_BIAS_SLEEP_S 31 1514 1515 /** PMU_IMM_HP_CK_POWER_REG register 1516 * need_des 1517 */ 1518 #define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) 1519 /** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; 1520 * need_des 1521 */ 1522 #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) 1523 #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) 1524 #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U 1525 #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 1526 /** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; 1527 * need_des 1528 */ 1529 #define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) 1530 #define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) 1531 #define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U 1532 #define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 1533 /** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; 1534 * need_des 1535 */ 1536 #define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) 1537 #define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) 1538 #define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U 1539 #define PMU_TIE_LOW_I2C_RETENTION_S 2 1540 /** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; 1541 * need_des 1542 */ 1543 #define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) 1544 #define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) 1545 #define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U 1546 #define PMU_TIE_LOW_XPD_BB_I2C_S 3 1547 /** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; 1548 * need_des 1549 */ 1550 #define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) 1551 #define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) 1552 #define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U 1553 #define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 1554 /** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; 1555 * need_des 1556 */ 1557 #define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) 1558 #define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) 1559 #define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U 1560 #define PMU_TIE_LOW_XPD_BBPLL_S 5 1561 /** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; 1562 * need_des 1563 */ 1564 #define PMU_TIE_LOW_XPD_XTAL (BIT(6)) 1565 #define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) 1566 #define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U 1567 #define PMU_TIE_LOW_XPD_XTAL_S 6 1568 /** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; 1569 * need_des 1570 */ 1571 #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) 1572 #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) 1573 #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U 1574 #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 1575 /** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; 1576 * need_des 1577 */ 1578 #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) 1579 #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) 1580 #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U 1581 #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 1582 /** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; 1583 * need_des 1584 */ 1585 #define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) 1586 #define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) 1587 #define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U 1588 #define PMU_TIE_HIGH_I2C_RETENTION_S 27 1589 /** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; 1590 * need_des 1591 */ 1592 #define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) 1593 #define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) 1594 #define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U 1595 #define PMU_TIE_HIGH_XPD_BB_I2C_S 28 1596 /** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; 1597 * need_des 1598 */ 1599 #define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) 1600 #define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) 1601 #define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U 1602 #define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 1603 /** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; 1604 * need_des 1605 */ 1606 #define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) 1607 #define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) 1608 #define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U 1609 #define PMU_TIE_HIGH_XPD_BBPLL_S 30 1610 /** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; 1611 * need_des 1612 */ 1613 #define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) 1614 #define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) 1615 #define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U 1616 #define PMU_TIE_HIGH_XPD_XTAL_S 31 1617 1618 /** PMU_IMM_SLEEP_SYSCLK_REG register 1619 * need_des 1620 */ 1621 #define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) 1622 /** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; 1623 * need_des 1624 */ 1625 #define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) 1626 #define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) 1627 #define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U 1628 #define PMU_UPDATE_DIG_ICG_SWITCH_S 28 1629 /** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; 1630 * need_des 1631 */ 1632 #define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) 1633 #define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) 1634 #define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U 1635 #define PMU_TIE_LOW_ICG_SLP_SEL_S 29 1636 /** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; 1637 * need_des 1638 */ 1639 #define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) 1640 #define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) 1641 #define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U 1642 #define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 1643 /** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; 1644 * need_des 1645 */ 1646 #define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) 1647 #define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) 1648 #define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U 1649 #define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 1650 1651 /** PMU_IMM_HP_FUNC_ICG_REG register 1652 * need_des 1653 */ 1654 #define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) 1655 /** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; 1656 * need_des 1657 */ 1658 #define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) 1659 #define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) 1660 #define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U 1661 #define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 1662 1663 /** PMU_IMM_HP_APB_ICG_REG register 1664 * need_des 1665 */ 1666 #define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) 1667 /** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; 1668 * need_des 1669 */ 1670 #define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) 1671 #define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) 1672 #define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U 1673 #define PMU_UPDATE_DIG_ICG_APB_EN_S 31 1674 1675 /** PMU_IMM_MODEM_ICG_REG register 1676 * need_des 1677 */ 1678 #define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) 1679 /** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; 1680 * need_des 1681 */ 1682 #define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) 1683 #define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) 1684 #define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U 1685 #define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 1686 1687 /** PMU_IMM_LP_ICG_REG register 1688 * need_des 1689 */ 1690 #define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) 1691 /** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; 1692 * need_des 1693 */ 1694 #define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) 1695 #define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) 1696 #define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U 1697 #define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 1698 /** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; 1699 * need_des 1700 */ 1701 #define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) 1702 #define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) 1703 #define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U 1704 #define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 1705 1706 /** PMU_IMM_PAD_HOLD_ALL_REG register 1707 * need_des 1708 */ 1709 #define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) 1710 /** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; 1711 * need_des 1712 */ 1713 #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) 1714 #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) 1715 #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U 1716 #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 1717 /** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; 1718 * need_des 1719 */ 1720 #define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) 1721 #define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) 1722 #define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U 1723 #define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 1724 /** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; 1725 * need_des 1726 */ 1727 #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) 1728 #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) 1729 #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U 1730 #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 1731 /** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; 1732 * need_des 1733 */ 1734 #define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) 1735 #define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) 1736 #define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U 1737 #define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 1738 1739 /** PMU_IMM_I2C_ISO_REG register 1740 * need_des 1741 */ 1742 #define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) 1743 /** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; 1744 * need_des 1745 */ 1746 #define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) 1747 #define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) 1748 #define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U 1749 #define PMU_TIE_HIGH_I2C_ISO_EN_S 30 1750 /** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; 1751 * need_des 1752 */ 1753 #define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) 1754 #define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) 1755 #define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U 1756 #define PMU_TIE_LOW_I2C_ISO_EN_S 31 1757 1758 /** PMU_POWER_WAIT_TIMER0_REG register 1759 * need_des 1760 */ 1761 #define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) 1762 /** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; 1763 * need_des 1764 */ 1765 #define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU 1766 #define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) 1767 #define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU 1768 #define PMU_DG_HP_POWERDOWN_TIMER_S 5 1769 /** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; 1770 * need_des 1771 */ 1772 #define PMU_DG_HP_POWERUP_TIMER 0x000001FFU 1773 #define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) 1774 #define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU 1775 #define PMU_DG_HP_POWERUP_TIMER_S 14 1776 /** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; 1777 * need_des 1778 */ 1779 #define PMU_DG_HP_WAIT_TIMER 0x000001FFU 1780 #define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) 1781 #define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU 1782 #define PMU_DG_HP_WAIT_TIMER_S 23 1783 1784 /** PMU_POWER_WAIT_TIMER1_REG register 1785 * need_des 1786 */ 1787 #define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) 1788 /** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; 1789 * need_des 1790 */ 1791 #define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU 1792 #define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) 1793 #define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU 1794 #define PMU_DG_LP_POWERDOWN_TIMER_S 9 1795 /** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; 1796 * need_des 1797 */ 1798 #define PMU_DG_LP_POWERUP_TIMER 0x0000007FU 1799 #define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) 1800 #define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU 1801 #define PMU_DG_LP_POWERUP_TIMER_S 16 1802 /** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; 1803 * need_des 1804 */ 1805 #define PMU_DG_LP_WAIT_TIMER 0x000001FFU 1806 #define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) 1807 #define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU 1808 #define PMU_DG_LP_WAIT_TIMER_S 23 1809 1810 /** PMU_POWER_PD_TOP_CNTL_REG register 1811 * need_des 1812 */ 1813 #define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) 1814 /** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; 1815 * need_des 1816 */ 1817 #define PMU_FORCE_TOP_RESET (BIT(0)) 1818 #define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) 1819 #define PMU_FORCE_TOP_RESET_V 0x00000001U 1820 #define PMU_FORCE_TOP_RESET_S 0 1821 /** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; 1822 * need_des 1823 */ 1824 #define PMU_FORCE_TOP_ISO (BIT(1)) 1825 #define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) 1826 #define PMU_FORCE_TOP_ISO_V 0x00000001U 1827 #define PMU_FORCE_TOP_ISO_S 1 1828 /** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; 1829 * need_des 1830 */ 1831 #define PMU_FORCE_TOP_PU (BIT(2)) 1832 #define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) 1833 #define PMU_FORCE_TOP_PU_V 0x00000001U 1834 #define PMU_FORCE_TOP_PU_S 2 1835 /** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; 1836 * need_des 1837 */ 1838 #define PMU_FORCE_TOP_NO_RESET (BIT(3)) 1839 #define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) 1840 #define PMU_FORCE_TOP_NO_RESET_V 0x00000001U 1841 #define PMU_FORCE_TOP_NO_RESET_S 3 1842 /** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; 1843 * need_des 1844 */ 1845 #define PMU_FORCE_TOP_NO_ISO (BIT(4)) 1846 #define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) 1847 #define PMU_FORCE_TOP_NO_ISO_V 0x00000001U 1848 #define PMU_FORCE_TOP_NO_ISO_S 4 1849 /** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; 1850 * need_des 1851 */ 1852 #define PMU_FORCE_TOP_PD (BIT(5)) 1853 #define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) 1854 #define PMU_FORCE_TOP_PD_V 0x00000001U 1855 #define PMU_FORCE_TOP_PD_S 5 1856 /** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; 1857 * need_des 1858 */ 1859 #define PMU_PD_TOP_MASK 0x0000001FU 1860 #define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) 1861 #define PMU_PD_TOP_MASK_V 0x0000001FU 1862 #define PMU_PD_TOP_MASK_S 6 1863 /** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; 1864 * need_des 1865 */ 1866 #define PMU_PD_TOP_PD_MASK 0x0000001FU 1867 #define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) 1868 #define PMU_PD_TOP_PD_MASK_V 0x0000001FU 1869 #define PMU_PD_TOP_PD_MASK_S 27 1870 1871 /** PMU_POWER_PD_HPAON_CNTL_REG register 1872 * need_des 1873 */ 1874 #define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) 1875 /** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; 1876 * need_des 1877 */ 1878 #define PMU_FORCE_HP_AON_RESET (BIT(0)) 1879 #define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) 1880 #define PMU_FORCE_HP_AON_RESET_V 0x00000001U 1881 #define PMU_FORCE_HP_AON_RESET_S 0 1882 /** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; 1883 * need_des 1884 */ 1885 #define PMU_FORCE_HP_AON_ISO (BIT(1)) 1886 #define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) 1887 #define PMU_FORCE_HP_AON_ISO_V 0x00000001U 1888 #define PMU_FORCE_HP_AON_ISO_S 1 1889 /** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; 1890 * need_des 1891 */ 1892 #define PMU_FORCE_HP_AON_PU (BIT(2)) 1893 #define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) 1894 #define PMU_FORCE_HP_AON_PU_V 0x00000001U 1895 #define PMU_FORCE_HP_AON_PU_S 2 1896 /** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; 1897 * need_des 1898 */ 1899 #define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) 1900 #define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) 1901 #define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U 1902 #define PMU_FORCE_HP_AON_NO_RESET_S 3 1903 /** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; 1904 * need_des 1905 */ 1906 #define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) 1907 #define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) 1908 #define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U 1909 #define PMU_FORCE_HP_AON_NO_ISO_S 4 1910 /** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; 1911 * need_des 1912 */ 1913 #define PMU_FORCE_HP_AON_PD (BIT(5)) 1914 #define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) 1915 #define PMU_FORCE_HP_AON_PD_V 0x00000001U 1916 #define PMU_FORCE_HP_AON_PD_S 5 1917 /** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; 1918 * need_des 1919 */ 1920 #define PMU_PD_HP_AON_MASK 0x0000001FU 1921 #define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) 1922 #define PMU_PD_HP_AON_MASK_V 0x0000001FU 1923 #define PMU_PD_HP_AON_MASK_S 6 1924 /** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; 1925 * need_des 1926 */ 1927 #define PMU_PD_HP_AON_PD_MASK 0x0000001FU 1928 #define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) 1929 #define PMU_PD_HP_AON_PD_MASK_V 0x0000001FU 1930 #define PMU_PD_HP_AON_PD_MASK_S 27 1931 1932 /** PMU_POWER_PD_HPCPU_CNTL_REG register 1933 * need_des 1934 */ 1935 #define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) 1936 /** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; 1937 * need_des 1938 */ 1939 #define PMU_FORCE_HP_CPU_RESET (BIT(0)) 1940 #define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) 1941 #define PMU_FORCE_HP_CPU_RESET_V 0x00000001U 1942 #define PMU_FORCE_HP_CPU_RESET_S 0 1943 /** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; 1944 * need_des 1945 */ 1946 #define PMU_FORCE_HP_CPU_ISO (BIT(1)) 1947 #define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) 1948 #define PMU_FORCE_HP_CPU_ISO_V 0x00000001U 1949 #define PMU_FORCE_HP_CPU_ISO_S 1 1950 /** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; 1951 * need_des 1952 */ 1953 #define PMU_FORCE_HP_CPU_PU (BIT(2)) 1954 #define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) 1955 #define PMU_FORCE_HP_CPU_PU_V 0x00000001U 1956 #define PMU_FORCE_HP_CPU_PU_S 2 1957 /** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; 1958 * need_des 1959 */ 1960 #define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) 1961 #define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) 1962 #define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U 1963 #define PMU_FORCE_HP_CPU_NO_RESET_S 3 1964 /** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; 1965 * need_des 1966 */ 1967 #define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) 1968 #define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) 1969 #define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U 1970 #define PMU_FORCE_HP_CPU_NO_ISO_S 4 1971 /** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; 1972 * need_des 1973 */ 1974 #define PMU_FORCE_HP_CPU_PD (BIT(5)) 1975 #define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) 1976 #define PMU_FORCE_HP_CPU_PD_V 0x00000001U 1977 #define PMU_FORCE_HP_CPU_PD_S 5 1978 /** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; 1979 * need_des 1980 */ 1981 #define PMU_PD_HP_CPU_MASK 0x0000001FU 1982 #define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) 1983 #define PMU_PD_HP_CPU_MASK_V 0x0000001FU 1984 #define PMU_PD_HP_CPU_MASK_S 6 1985 /** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; 1986 * need_des 1987 */ 1988 #define PMU_PD_HP_CPU_PD_MASK 0x0000001FU 1989 #define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) 1990 #define PMU_PD_HP_CPU_PD_MASK_V 0x0000001FU 1991 #define PMU_PD_HP_CPU_PD_MASK_S 27 1992 1993 /** PMU_POWER_PD_HPPERI_RESERVE_REG register 1994 * need_des 1995 */ 1996 #define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x100) 1997 /** PMU_HP_PERI_RESERVE : WT; bitpos: [31:0]; default: 0; 1998 * need_des 1999 */ 2000 #define PMU_HP_PERI_RESERVE 0xFFFFFFFFU 2001 #define PMU_HP_PERI_RESERVE_M (PMU_HP_PERI_RESERVE_V << PMU_HP_PERI_RESERVE_S) 2002 #define PMU_HP_PERI_RESERVE_V 0xFFFFFFFFU 2003 #define PMU_HP_PERI_RESERVE_S 0 2004 2005 /** PMU_POWER_PD_HPWIFI_CNTL_REG register 2006 * need_des 2007 */ 2008 #define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) 2009 /** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; 2010 * need_des 2011 */ 2012 #define PMU_FORCE_HP_WIFI_RESET (BIT(0)) 2013 #define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) 2014 #define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U 2015 #define PMU_FORCE_HP_WIFI_RESET_S 0 2016 /** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; 2017 * need_des 2018 */ 2019 #define PMU_FORCE_HP_WIFI_ISO (BIT(1)) 2020 #define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) 2021 #define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U 2022 #define PMU_FORCE_HP_WIFI_ISO_S 1 2023 /** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; 2024 * need_des 2025 */ 2026 #define PMU_FORCE_HP_WIFI_PU (BIT(2)) 2027 #define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) 2028 #define PMU_FORCE_HP_WIFI_PU_V 0x00000001U 2029 #define PMU_FORCE_HP_WIFI_PU_S 2 2030 /** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; 2031 * need_des 2032 */ 2033 #define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) 2034 #define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) 2035 #define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U 2036 #define PMU_FORCE_HP_WIFI_NO_RESET_S 3 2037 /** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; 2038 * need_des 2039 */ 2040 #define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) 2041 #define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) 2042 #define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U 2043 #define PMU_FORCE_HP_WIFI_NO_ISO_S 4 2044 /** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; 2045 * need_des 2046 */ 2047 #define PMU_FORCE_HP_WIFI_PD (BIT(5)) 2048 #define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) 2049 #define PMU_FORCE_HP_WIFI_PD_V 0x00000001U 2050 #define PMU_FORCE_HP_WIFI_PD_S 5 2051 /** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; 2052 * need_des 2053 */ 2054 #define PMU_PD_HP_WIFI_MASK 0x0000001FU 2055 #define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) 2056 #define PMU_PD_HP_WIFI_MASK_V 0x0000001FU 2057 #define PMU_PD_HP_WIFI_MASK_S 6 2058 /** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; 2059 * need_des 2060 */ 2061 #define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU 2062 #define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) 2063 #define PMU_PD_HP_WIFI_PD_MASK_V 0x0000001FU 2064 #define PMU_PD_HP_WIFI_PD_MASK_S 27 2065 2066 /** PMU_POWER_PD_LPPERI_CNTL_REG register 2067 * need_des 2068 */ 2069 #define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) 2070 /** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; 2071 * need_des 2072 */ 2073 #define PMU_FORCE_LP_PERI_RESET (BIT(0)) 2074 #define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) 2075 #define PMU_FORCE_LP_PERI_RESET_V 0x00000001U 2076 #define PMU_FORCE_LP_PERI_RESET_S 0 2077 /** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; 2078 * need_des 2079 */ 2080 #define PMU_FORCE_LP_PERI_ISO (BIT(1)) 2081 #define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) 2082 #define PMU_FORCE_LP_PERI_ISO_V 0x00000001U 2083 #define PMU_FORCE_LP_PERI_ISO_S 1 2084 /** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; 2085 * need_des 2086 */ 2087 #define PMU_FORCE_LP_PERI_PU (BIT(2)) 2088 #define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) 2089 #define PMU_FORCE_LP_PERI_PU_V 0x00000001U 2090 #define PMU_FORCE_LP_PERI_PU_S 2 2091 /** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; 2092 * need_des 2093 */ 2094 #define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) 2095 #define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) 2096 #define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U 2097 #define PMU_FORCE_LP_PERI_NO_RESET_S 3 2098 /** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; 2099 * need_des 2100 */ 2101 #define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) 2102 #define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) 2103 #define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U 2104 #define PMU_FORCE_LP_PERI_NO_ISO_S 4 2105 /** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; 2106 * need_des 2107 */ 2108 #define PMU_FORCE_LP_PERI_PD (BIT(5)) 2109 #define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) 2110 #define PMU_FORCE_LP_PERI_PD_V 0x00000001U 2111 #define PMU_FORCE_LP_PERI_PD_S 5 2112 2113 /** PMU_POWER_PD_MEM_CNTL_REG register 2114 * need_des 2115 */ 2116 #define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) 2117 /** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; 2118 * need_des 2119 */ 2120 #define PMU_FORCE_HP_MEM_ISO 0x0000000FU 2121 #define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) 2122 #define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU 2123 #define PMU_FORCE_HP_MEM_ISO_S 0 2124 /** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; 2125 * need_des 2126 */ 2127 #define PMU_FORCE_HP_MEM_PD 0x0000000FU 2128 #define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) 2129 #define PMU_FORCE_HP_MEM_PD_V 0x0000000FU 2130 #define PMU_FORCE_HP_MEM_PD_S 4 2131 /** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; 2132 * need_des 2133 */ 2134 #define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU 2135 #define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) 2136 #define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU 2137 #define PMU_FORCE_HP_MEM_NO_ISO_S 24 2138 /** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; 2139 * need_des 2140 */ 2141 #define PMU_FORCE_HP_MEM_PU 0x0000000FU 2142 #define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) 2143 #define PMU_FORCE_HP_MEM_PU_V 0x0000000FU 2144 #define PMU_FORCE_HP_MEM_PU_S 28 2145 2146 /** PMU_POWER_PD_MEM_MASK_REG register 2147 * need_des 2148 */ 2149 #define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) 2150 /** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; 2151 * need_des 2152 */ 2153 #define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU 2154 #define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) 2155 #define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU 2156 #define PMU_PD_HP_MEM2_PD_MASK_S 0 2157 /** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; 2158 * need_des 2159 */ 2160 #define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU 2161 #define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) 2162 #define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU 2163 #define PMU_PD_HP_MEM1_PD_MASK_S 5 2164 /** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; 2165 * need_des 2166 */ 2167 #define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU 2168 #define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) 2169 #define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU 2170 #define PMU_PD_HP_MEM0_PD_MASK_S 10 2171 /** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; 2172 * need_des 2173 */ 2174 #define PMU_PD_HP_MEM2_MASK 0x0000001FU 2175 #define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) 2176 #define PMU_PD_HP_MEM2_MASK_V 0x0000001FU 2177 #define PMU_PD_HP_MEM2_MASK_S 17 2178 /** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; 2179 * need_des 2180 */ 2181 #define PMU_PD_HP_MEM1_MASK 0x0000001FU 2182 #define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) 2183 #define PMU_PD_HP_MEM1_MASK_V 0x0000001FU 2184 #define PMU_PD_HP_MEM1_MASK_S 22 2185 /** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; 2186 * need_des 2187 */ 2188 #define PMU_PD_HP_MEM0_MASK 0x0000001FU 2189 #define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) 2190 #define PMU_PD_HP_MEM0_MASK_V 0x0000001FU 2191 #define PMU_PD_HP_MEM0_MASK_S 27 2192 2193 /** PMU_POWER_HP_PAD_REG register 2194 * need_des 2195 */ 2196 #define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) 2197 /** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; 2198 * need_des 2199 */ 2200 #define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) 2201 #define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) 2202 #define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U 2203 #define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 2204 /** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; 2205 * need_des 2206 */ 2207 #define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) 2208 #define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) 2209 #define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U 2210 #define PMU_FORCE_HP_PAD_ISO_ALL_S 1 2211 2212 /** PMU_POWER_VDD_SPI_CNTL_REG register 2213 * need_des 2214 */ 2215 #define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) 2216 /** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; 2217 * need_des 2218 */ 2219 #define PMU_VDD_SPI_PWR_WAIT 0x000007FFU 2220 #define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) 2221 #define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU 2222 #define PMU_VDD_SPI_PWR_WAIT_S 18 2223 /** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; 2224 * need_des 2225 */ 2226 #define PMU_VDD_SPI_PWR_SW 0x00000003U 2227 #define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) 2228 #define PMU_VDD_SPI_PWR_SW_V 0x00000003U 2229 #define PMU_VDD_SPI_PWR_SW_S 29 2230 /** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; 2231 * need_des 2232 */ 2233 #define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) 2234 #define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) 2235 #define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U 2236 #define PMU_VDD_SPI_PWR_SEL_SW_S 31 2237 2238 /** PMU_POWER_CK_WAIT_CNTL_REG register 2239 * need_des 2240 */ 2241 #define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) 2242 /** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; 2243 * need_des 2244 */ 2245 #define PMU_WAIT_XTL_STABLE 0x0000FFFFU 2246 #define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) 2247 #define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU 2248 #define PMU_WAIT_XTL_STABLE_S 0 2249 /** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; 2250 * need_des 2251 */ 2252 #define PMU_WAIT_PLL_STABLE 0x0000FFFFU 2253 #define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) 2254 #define PMU_WAIT_PLL_STABLE_V 0x0000FFFFU 2255 #define PMU_WAIT_PLL_STABLE_S 16 2256 2257 /** PMU_SLP_WAKEUP_CNTL0_REG register 2258 * need_des 2259 */ 2260 #define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) 2261 /** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; 2262 * need_des 2263 */ 2264 #define PMU_SLEEP_REQ (BIT(31)) 2265 #define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) 2266 #define PMU_SLEEP_REQ_V 0x00000001U 2267 #define PMU_SLEEP_REQ_S 31 2268 2269 /** PMU_SLP_WAKEUP_CNTL1_REG register 2270 * need_des 2271 */ 2272 #define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) 2273 /** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; 2274 * need_des 2275 */ 2276 #define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU 2277 #define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) 2278 #define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU 2279 #define PMU_SLEEP_REJECT_ENA_S 0 2280 /** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; 2281 * need_des 2282 */ 2283 #define PMU_SLP_REJECT_EN (BIT(31)) 2284 #define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) 2285 #define PMU_SLP_REJECT_EN_V 0x00000001U 2286 #define PMU_SLP_REJECT_EN_S 31 2287 2288 /** PMU_SLP_WAKEUP_CNTL2_REG register 2289 * need_des 2290 */ 2291 #define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) 2292 /** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; 2293 * need_des 2294 */ 2295 #define PMU_WAKEUP_ENA 0xFFFFFFFFU 2296 #define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) 2297 #define PMU_WAKEUP_ENA_V 0xFFFFFFFFU 2298 #define PMU_WAKEUP_ENA_S 0 2299 2300 /** PMU_SLP_WAKEUP_CNTL3_REG register 2301 * need_des 2302 */ 2303 #define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) 2304 /** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; 2305 * need_des 2306 */ 2307 #define PMU_LP_MIN_SLP_VAL 0x000000FFU 2308 #define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) 2309 #define PMU_LP_MIN_SLP_VAL_V 0x000000FFU 2310 #define PMU_LP_MIN_SLP_VAL_S 0 2311 /** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; 2312 * need_des 2313 */ 2314 #define PMU_HP_MIN_SLP_VAL 0x000000FFU 2315 #define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) 2316 #define PMU_HP_MIN_SLP_VAL_V 0x000000FFU 2317 #define PMU_HP_MIN_SLP_VAL_S 8 2318 /** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; 2319 * need_des 2320 */ 2321 #define PMU_SLEEP_PRT_SEL 0x00000003U 2322 #define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) 2323 #define PMU_SLEEP_PRT_SEL_V 0x00000003U 2324 #define PMU_SLEEP_PRT_SEL_S 16 2325 2326 /** PMU_SLP_WAKEUP_CNTL4_REG register 2327 * need_des 2328 */ 2329 #define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) 2330 /** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; 2331 * need_des 2332 */ 2333 #define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) 2334 #define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) 2335 #define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U 2336 #define PMU_SLP_REJECT_CAUSE_CLR_S 31 2337 2338 /** PMU_SLP_WAKEUP_CNTL5_REG register 2339 * need_des 2340 */ 2341 #define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) 2342 /** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; 2343 * need_des 2344 */ 2345 #define PMU_MODEM_WAIT_TARGET 0x000FFFFFU 2346 #define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) 2347 #define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU 2348 #define PMU_MODEM_WAIT_TARGET_S 0 2349 /** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; 2350 * need_des 2351 */ 2352 #define PMU_LP_ANA_WAIT_TARGET 0x000000FFU 2353 #define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) 2354 #define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU 2355 #define PMU_LP_ANA_WAIT_TARGET_S 24 2356 2357 /** PMU_SLP_WAKEUP_CNTL6_REG register 2358 * need_des 2359 */ 2360 #define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) 2361 /** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; 2362 * need_des 2363 */ 2364 #define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU 2365 #define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) 2366 #define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU 2367 #define PMU_SOC_WAKEUP_WAIT_S 0 2368 /** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; 2369 * need_des 2370 */ 2371 #define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U 2372 #define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) 2373 #define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U 2374 #define PMU_SOC_WAKEUP_WAIT_CFG_S 30 2375 2376 /** PMU_SLP_WAKEUP_CNTL7_REG register 2377 * need_des 2378 */ 2379 #define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) 2380 /** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; 2381 * need_des 2382 */ 2383 #define PMU_ANA_WAIT_TARGET 0x0000FFFFU 2384 #define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) 2385 #define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU 2386 #define PMU_ANA_WAIT_TARGET_S 16 2387 2388 /** PMU_SLP_WAKEUP_STATUS0_REG register 2389 * need_des 2390 */ 2391 #define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) 2392 /** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; 2393 * need_des 2394 */ 2395 #define PMU_WAKEUP_CAUSE 0xFFFFFFFFU 2396 #define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) 2397 #define PMU_WAKEUP_CAUSE_V 0xFFFFFFFFU 2398 #define PMU_WAKEUP_CAUSE_S 0 2399 2400 /** PMU_SLP_WAKEUP_STATUS1_REG register 2401 * need_des 2402 */ 2403 #define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) 2404 /** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; 2405 * need_des 2406 */ 2407 #define PMU_REJECT_CAUSE 0xFFFFFFFFU 2408 #define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) 2409 #define PMU_REJECT_CAUSE_V 0xFFFFFFFFU 2410 #define PMU_REJECT_CAUSE_S 0 2411 2412 /** PMU_HP_CK_POWERON_REG register 2413 * need_des 2414 */ 2415 #define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) 2416 /** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; 2417 * need_des 2418 */ 2419 #define PMU_I2C_POR_WAIT_TARGET 0x000000FFU 2420 #define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) 2421 #define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU 2422 #define PMU_I2C_POR_WAIT_TARGET_S 0 2423 2424 /** PMU_HP_CK_CNTL_REG register 2425 * need_des 2426 */ 2427 #define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) 2428 /** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; 2429 * need_des 2430 */ 2431 #define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU 2432 #define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) 2433 #define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU 2434 #define PMU_MODIFY_ICG_CNTL_WAIT_S 0 2435 /** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; 2436 * need_des 2437 */ 2438 #define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU 2439 #define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) 2440 #define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU 2441 #define PMU_SWITCH_ICG_CNTL_WAIT_S 8 2442 2443 /** PMU_POR_STATUS_REG register 2444 * need_des 2445 */ 2446 #define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) 2447 /** PMU_POR_DONE : RO; bitpos: [31]; default: 1; 2448 * need_des 2449 */ 2450 #define PMU_POR_DONE (BIT(31)) 2451 #define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) 2452 #define PMU_POR_DONE_V 0x00000001U 2453 #define PMU_POR_DONE_S 31 2454 2455 /** PMU_RF_PWC_REG register 2456 * need_des 2457 */ 2458 #define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) 2459 /** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; 2460 * need_des 2461 */ 2462 #define PMU_PERIF_I2C_RSTB (BIT(26)) 2463 #define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) 2464 #define PMU_PERIF_I2C_RSTB_V 0x00000001U 2465 #define PMU_PERIF_I2C_RSTB_S 26 2466 /** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; 2467 * need_des 2468 */ 2469 #define PMU_XPD_PERIF_I2C (BIT(27)) 2470 #define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) 2471 #define PMU_XPD_PERIF_I2C_V 0x00000001U 2472 #define PMU_XPD_PERIF_I2C_S 27 2473 /** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; 2474 * need_des 2475 */ 2476 #define PMU_XPD_TXRF_I2C (BIT(28)) 2477 #define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) 2478 #define PMU_XPD_TXRF_I2C_V 0x00000001U 2479 #define PMU_XPD_TXRF_I2C_S 28 2480 /** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; 2481 * need_des 2482 */ 2483 #define PMU_XPD_RFRX_PBUS (BIT(29)) 2484 #define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) 2485 #define PMU_XPD_RFRX_PBUS_V 0x00000001U 2486 #define PMU_XPD_RFRX_PBUS_S 29 2487 /** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; 2488 * need_des 2489 */ 2490 #define PMU_XPD_CKGEN_I2C (BIT(30)) 2491 #define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) 2492 #define PMU_XPD_CKGEN_I2C_V 0x00000001U 2493 #define PMU_XPD_CKGEN_I2C_S 30 2494 /** PMU_XPD_PLL_I2C : R/W; bitpos: [31]; default: 0; 2495 * need_des 2496 */ 2497 #define PMU_XPD_PLL_I2C (BIT(31)) 2498 #define PMU_XPD_PLL_I2C_M (PMU_XPD_PLL_I2C_V << PMU_XPD_PLL_I2C_S) 2499 #define PMU_XPD_PLL_I2C_V 0x00000001U 2500 #define PMU_XPD_PLL_I2C_S 31 2501 2502 /** PMU_BACKUP_CFG_REG register 2503 * need_des 2504 */ 2505 #define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x158) 2506 /** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; 2507 * need_des 2508 */ 2509 #define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) 2510 #define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) 2511 #define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U 2512 #define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 2513 2514 /** PMU_INT_RAW_REG register 2515 * need_des 2516 */ 2517 #define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x15c) 2518 /** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; 2519 * need_des 2520 */ 2521 #define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) 2522 #define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) 2523 #define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U 2524 #define PMU_LP_CPU_EXC_INT_RAW_S 27 2525 /** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; 2526 * need_des 2527 */ 2528 #define PMU_SDIO_IDLE_INT_RAW (BIT(28)) 2529 #define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) 2530 #define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U 2531 #define PMU_SDIO_IDLE_INT_RAW_S 28 2532 /** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; 2533 * need_des 2534 */ 2535 #define PMU_SW_INT_RAW (BIT(29)) 2536 #define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) 2537 #define PMU_SW_INT_RAW_V 0x00000001U 2538 #define PMU_SW_INT_RAW_S 29 2539 /** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; 2540 * need_des 2541 */ 2542 #define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) 2543 #define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) 2544 #define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U 2545 #define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 2546 /** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; 2547 * need_des 2548 */ 2549 #define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) 2550 #define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) 2551 #define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U 2552 #define PMU_SOC_WAKEUP_INT_RAW_S 31 2553 2554 /** PMU_HP_INT_ST_REG register 2555 * need_des 2556 */ 2557 #define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x160) 2558 /** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; 2559 * need_des 2560 */ 2561 #define PMU_LP_CPU_EXC_INT_ST (BIT(27)) 2562 #define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) 2563 #define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U 2564 #define PMU_LP_CPU_EXC_INT_ST_S 27 2565 /** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; 2566 * need_des 2567 */ 2568 #define PMU_SDIO_IDLE_INT_ST (BIT(28)) 2569 #define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) 2570 #define PMU_SDIO_IDLE_INT_ST_V 0x00000001U 2571 #define PMU_SDIO_IDLE_INT_ST_S 28 2572 /** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; 2573 * need_des 2574 */ 2575 #define PMU_SW_INT_ST (BIT(29)) 2576 #define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) 2577 #define PMU_SW_INT_ST_V 0x00000001U 2578 #define PMU_SW_INT_ST_S 29 2579 /** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; 2580 * need_des 2581 */ 2582 #define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) 2583 #define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) 2584 #define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U 2585 #define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 2586 /** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; 2587 * need_des 2588 */ 2589 #define PMU_SOC_WAKEUP_INT_ST (BIT(31)) 2590 #define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) 2591 #define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U 2592 #define PMU_SOC_WAKEUP_INT_ST_S 31 2593 2594 /** PMU_HP_INT_ENA_REG register 2595 * need_des 2596 */ 2597 #define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x164) 2598 /** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; 2599 * need_des 2600 */ 2601 #define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) 2602 #define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) 2603 #define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U 2604 #define PMU_LP_CPU_EXC_INT_ENA_S 27 2605 /** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; 2606 * need_des 2607 */ 2608 #define PMU_SDIO_IDLE_INT_ENA (BIT(28)) 2609 #define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) 2610 #define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U 2611 #define PMU_SDIO_IDLE_INT_ENA_S 28 2612 /** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; 2613 * need_des 2614 */ 2615 #define PMU_SW_INT_ENA (BIT(29)) 2616 #define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) 2617 #define PMU_SW_INT_ENA_V 0x00000001U 2618 #define PMU_SW_INT_ENA_S 29 2619 /** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; 2620 * need_des 2621 */ 2622 #define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) 2623 #define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) 2624 #define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U 2625 #define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 2626 /** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; 2627 * need_des 2628 */ 2629 #define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) 2630 #define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) 2631 #define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U 2632 #define PMU_SOC_WAKEUP_INT_ENA_S 31 2633 2634 /** PMU_HP_INT_CLR_REG register 2635 * need_des 2636 */ 2637 #define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x168) 2638 /** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; 2639 * need_des 2640 */ 2641 #define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) 2642 #define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) 2643 #define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U 2644 #define PMU_LP_CPU_EXC_INT_CLR_S 27 2645 /** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; 2646 * need_des 2647 */ 2648 #define PMU_SDIO_IDLE_INT_CLR (BIT(28)) 2649 #define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) 2650 #define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U 2651 #define PMU_SDIO_IDLE_INT_CLR_S 28 2652 /** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; 2653 * need_des 2654 */ 2655 #define PMU_SW_INT_CLR (BIT(29)) 2656 #define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) 2657 #define PMU_SW_INT_CLR_V 0x00000001U 2658 #define PMU_SW_INT_CLR_S 29 2659 /** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; 2660 * need_des 2661 */ 2662 #define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) 2663 #define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) 2664 #define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U 2665 #define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 2666 /** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; 2667 * need_des 2668 */ 2669 #define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) 2670 #define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) 2671 #define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U 2672 #define PMU_SOC_WAKEUP_INT_CLR_S 31 2673 2674 /** PMU_LP_INT_RAW_REG register 2675 * need_des 2676 */ 2677 #define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x16c) 2678 /** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; 2679 * need_des 2680 */ 2681 #define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(20)) 2682 #define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) 2683 #define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U 2684 #define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 2685 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; 2686 * need_des 2687 */ 2688 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) 2689 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) 2690 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U 2691 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 2692 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; 2693 * need_des 2694 */ 2695 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) 2696 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) 2697 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U 2698 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 2699 /** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; 2700 * need_des 2701 */ 2702 #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) 2703 #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) 2704 #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U 2705 #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 2706 /** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; 2707 * need_des 2708 */ 2709 #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) 2710 #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) 2711 #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U 2712 #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 2713 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; 2714 * need_des 2715 */ 2716 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) 2717 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) 2718 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U 2719 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 2720 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; 2721 * need_des 2722 */ 2723 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) 2724 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) 2725 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U 2726 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 2727 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; 2728 * need_des 2729 */ 2730 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) 2731 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) 2732 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U 2733 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 2734 /** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; 2735 * need_des 2736 */ 2737 #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) 2738 #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) 2739 #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U 2740 #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 2741 /** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; 2742 * need_des 2743 */ 2744 #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) 2745 #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) 2746 #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U 2747 #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 2748 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; 2749 * need_des 2750 */ 2751 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) 2752 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) 2753 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U 2754 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 2755 /** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; 2756 * need_des 2757 */ 2758 #define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) 2759 #define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) 2760 #define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U 2761 #define PMU_HP_SW_TRIGGER_INT_RAW_S 31 2762 2763 /** PMU_LP_INT_ST_REG register 2764 * need_des 2765 */ 2766 #define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x170) 2767 /** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; 2768 * need_des 2769 */ 2770 #define PMU_LP_CPU_WAKEUP_INT_ST (BIT(20)) 2771 #define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) 2772 #define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U 2773 #define PMU_LP_CPU_WAKEUP_INT_ST_S 20 2774 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; 2775 * need_des 2776 */ 2777 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) 2778 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) 2779 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U 2780 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 2781 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; 2782 * need_des 2783 */ 2784 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) 2785 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) 2786 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U 2787 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 2788 /** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; 2789 * need_des 2790 */ 2791 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) 2792 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) 2793 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U 2794 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 2795 /** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; 2796 * need_des 2797 */ 2798 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) 2799 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) 2800 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U 2801 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 2802 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; 2803 * need_des 2804 */ 2805 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) 2806 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) 2807 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U 2808 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 2809 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; 2810 * need_des 2811 */ 2812 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) 2813 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) 2814 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U 2815 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 2816 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; 2817 * need_des 2818 */ 2819 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) 2820 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) 2821 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U 2822 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 2823 /** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; 2824 * need_des 2825 */ 2826 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) 2827 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) 2828 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U 2829 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 2830 /** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; 2831 * need_des 2832 */ 2833 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) 2834 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) 2835 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U 2836 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 2837 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; 2838 * need_des 2839 */ 2840 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) 2841 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) 2842 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U 2843 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 2844 /** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; 2845 * need_des 2846 */ 2847 #define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) 2848 #define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) 2849 #define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U 2850 #define PMU_HP_SW_TRIGGER_INT_ST_S 31 2851 2852 /** PMU_LP_INT_ENA_REG register 2853 * need_des 2854 */ 2855 #define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x174) 2856 /** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; 2857 * need_des 2858 */ 2859 #define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(20)) 2860 #define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) 2861 #define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U 2862 #define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 2863 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; 2864 * need_des 2865 */ 2866 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) 2867 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) 2868 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U 2869 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 2870 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; 2871 * need_des 2872 */ 2873 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) 2874 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) 2875 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U 2876 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 2877 /** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; 2878 * need_des 2879 */ 2880 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) 2881 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) 2882 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U 2883 #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 2884 /** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; 2885 * need_des 2886 */ 2887 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) 2888 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) 2889 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U 2890 #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 2891 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; 2892 * need_des 2893 */ 2894 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) 2895 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) 2896 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U 2897 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 2898 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; 2899 * need_des 2900 */ 2901 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) 2902 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) 2903 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U 2904 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 2905 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; 2906 * need_des 2907 */ 2908 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) 2909 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) 2910 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U 2911 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 2912 /** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; 2913 * need_des 2914 */ 2915 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) 2916 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) 2917 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U 2918 #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 2919 /** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; 2920 * need_des 2921 */ 2922 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) 2923 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) 2924 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U 2925 #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 2926 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; 2927 * need_des 2928 */ 2929 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) 2930 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) 2931 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U 2932 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 2933 /** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; 2934 * need_des 2935 */ 2936 #define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) 2937 #define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) 2938 #define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U 2939 #define PMU_HP_SW_TRIGGER_INT_ENA_S 31 2940 2941 /** PMU_LP_INT_CLR_REG register 2942 * need_des 2943 */ 2944 #define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x178) 2945 /** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; 2946 * need_des 2947 */ 2948 #define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(20)) 2949 #define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) 2950 #define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U 2951 #define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 2952 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; 2953 * need_des 2954 */ 2955 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) 2956 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) 2957 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U 2958 #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 2959 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; 2960 * need_des 2961 */ 2962 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) 2963 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) 2964 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U 2965 #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 2966 /** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; 2967 * need_des 2968 */ 2969 #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) 2970 #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) 2971 #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U 2972 #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 2973 /** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; 2974 * need_des 2975 */ 2976 #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) 2977 #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) 2978 #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U 2979 #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 2980 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; 2981 * need_des 2982 */ 2983 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) 2984 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) 2985 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U 2986 #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 2987 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; 2988 * need_des 2989 */ 2990 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) 2991 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) 2992 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U 2993 #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 2994 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; 2995 * need_des 2996 */ 2997 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) 2998 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) 2999 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U 3000 #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 3001 /** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; 3002 * need_des 3003 */ 3004 #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) 3005 #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) 3006 #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U 3007 #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 3008 /** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; 3009 * need_des 3010 */ 3011 #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) 3012 #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) 3013 #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U 3014 #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 3015 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; 3016 * need_des 3017 */ 3018 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) 3019 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) 3020 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U 3021 #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 3022 /** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; 3023 * need_des 3024 */ 3025 #define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) 3026 #define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) 3027 #define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U 3028 #define PMU_HP_SW_TRIGGER_INT_CLR_S 31 3029 3030 /** PMU_LP_CPU_PWR0_REG register 3031 * need_des 3032 */ 3033 #define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x17c) 3034 /** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; 3035 * need_des 3036 */ 3037 #define PMU_LP_CPU_WAITI_RDY (BIT(0)) 3038 #define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) 3039 #define PMU_LP_CPU_WAITI_RDY_V 0x00000001U 3040 #define PMU_LP_CPU_WAITI_RDY_S 0 3041 /** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; 3042 * need_des 3043 */ 3044 #define PMU_LP_CPU_STALL_RDY (BIT(1)) 3045 #define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) 3046 #define PMU_LP_CPU_STALL_RDY_V 0x00000001U 3047 #define PMU_LP_CPU_STALL_RDY_S 1 3048 /** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; 3049 * need_des 3050 */ 3051 #define PMU_LP_CPU_FORCE_STALL (BIT(18)) 3052 #define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) 3053 #define PMU_LP_CPU_FORCE_STALL_V 0x00000001U 3054 #define PMU_LP_CPU_FORCE_STALL_S 18 3055 /** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; 3056 * need_des 3057 */ 3058 #define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) 3059 #define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) 3060 #define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U 3061 #define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 3062 /** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; 3063 * need_des 3064 */ 3065 #define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) 3066 #define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) 3067 #define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U 3068 #define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 3069 /** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; 3070 * need_des 3071 */ 3072 #define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU 3073 #define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) 3074 #define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU 3075 #define PMU_LP_CPU_SLP_STALL_WAIT_S 21 3076 /** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; 3077 * need_des 3078 */ 3079 #define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) 3080 #define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) 3081 #define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U 3082 #define PMU_LP_CPU_SLP_STALL_EN_S 29 3083 /** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; 3084 * need_des 3085 */ 3086 #define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) 3087 #define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) 3088 #define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U 3089 #define PMU_LP_CPU_SLP_RESET_EN_S 30 3090 /** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; 3091 * need_des 3092 */ 3093 #define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) 3094 #define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) 3095 #define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U 3096 #define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 3097 3098 /** PMU_LP_CPU_PWR1_REG register 3099 * need_des 3100 */ 3101 #define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x180) 3102 /** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; 3103 * need_des 3104 */ 3105 #define PMU_LP_CPU_WAKEUP_EN 0x0000FFFFU 3106 #define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) 3107 #define PMU_LP_CPU_WAKEUP_EN_V 0x0000FFFFU 3108 #define PMU_LP_CPU_WAKEUP_EN_S 0 3109 /** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; 3110 * need_des 3111 */ 3112 #define PMU_LP_CPU_SLEEP_REQ (BIT(31)) 3113 #define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) 3114 #define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U 3115 #define PMU_LP_CPU_SLEEP_REQ_S 31 3116 3117 /** PMU_HP_LP_CPU_COMM_REG register 3118 * need_des 3119 */ 3120 #define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x184) 3121 /** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; 3122 * need_des 3123 */ 3124 #define PMU_LP_TRIGGER_HP (BIT(30)) 3125 #define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) 3126 #define PMU_LP_TRIGGER_HP_V 0x00000001U 3127 #define PMU_LP_TRIGGER_HP_S 30 3128 /** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; 3129 * need_des 3130 */ 3131 #define PMU_HP_TRIGGER_LP (BIT(31)) 3132 #define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) 3133 #define PMU_HP_TRIGGER_LP_V 0x00000001U 3134 #define PMU_HP_TRIGGER_LP_S 31 3135 3136 /** PMU_HP_REGULATOR_CFG_REG register 3137 * need_des 3138 */ 3139 #define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x188) 3140 /** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; 3141 * need_des 3142 */ 3143 #define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) 3144 #define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) 3145 #define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U 3146 #define PMU_DIG_REGULATOR_EN_CAL_S 31 3147 3148 /** PMU_MAIN_STATE_REG register 3149 * need_des 3150 */ 3151 #define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x18c) 3152 /** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; 3153 * need_des 3154 */ 3155 #define PMU_MAIN_LAST_ST_STATE 0x0000007FU 3156 #define PMU_MAIN_LAST_ST_STATE_M (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S) 3157 #define PMU_MAIN_LAST_ST_STATE_V 0x0000007FU 3158 #define PMU_MAIN_LAST_ST_STATE_S 11 3159 /** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; 3160 * need_des 3161 */ 3162 #define PMU_MAIN_TAR_ST_STATE 0x0000007FU 3163 #define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) 3164 #define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU 3165 #define PMU_MAIN_TAR_ST_STATE_S 18 3166 /** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; 3167 * need_des 3168 */ 3169 #define PMU_MAIN_CUR_ST_STATE 0x0000007FU 3170 #define PMU_MAIN_CUR_ST_STATE_M (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S) 3171 #define PMU_MAIN_CUR_ST_STATE_V 0x0000007FU 3172 #define PMU_MAIN_CUR_ST_STATE_S 25 3173 3174 /** PMU_PWR_STATE_REG register 3175 * need_des 3176 */ 3177 #define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x190) 3178 /** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; 3179 * need_des 3180 */ 3181 #define PMU_BACKUP_ST_STATE 0x0000001FU 3182 #define PMU_BACKUP_ST_STATE_M (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S) 3183 #define PMU_BACKUP_ST_STATE_V 0x0000001FU 3184 #define PMU_BACKUP_ST_STATE_S 13 3185 /** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; 3186 * need_des 3187 */ 3188 #define PMU_LP_PWR_ST_STATE 0x0000001FU 3189 #define PMU_LP_PWR_ST_STATE_M (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S) 3190 #define PMU_LP_PWR_ST_STATE_V 0x0000001FU 3191 #define PMU_LP_PWR_ST_STATE_S 18 3192 /** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; 3193 * need_des 3194 */ 3195 #define PMU_HP_PWR_ST_STATE 0x000001FFU 3196 #define PMU_HP_PWR_ST_STATE_M (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S) 3197 #define PMU_HP_PWR_ST_STATE_V 0x000001FFU 3198 #define PMU_HP_PWR_ST_STATE_S 23 3199 3200 /** PMU_CLK_STATE0_REG register 3201 * need_des 3202 */ 3203 #define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x194) 3204 /** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; 3205 * need_des 3206 */ 3207 #define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) 3208 #define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) 3209 #define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U 3210 #define PMU_STABLE_XPD_BBPLL_STATE_S 0 3211 /** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; 3212 * need_des 3213 */ 3214 #define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) 3215 #define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) 3216 #define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U 3217 #define PMU_STABLE_XPD_XTAL_STATE_S 1 3218 /** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0; 3219 * need_des 3220 */ 3221 #define PMU_SYS_CLK_SLP_SEL_STATE (BIT(15)) 3222 #define PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S) 3223 #define PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U 3224 #define PMU_SYS_CLK_SLP_SEL_STATE_S 15 3225 /** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0; 3226 * need_des 3227 */ 3228 #define PMU_SYS_CLK_SEL_STATE 0x00000003U 3229 #define PMU_SYS_CLK_SEL_STATE_M (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S) 3230 #define PMU_SYS_CLK_SEL_STATE_V 0x00000003U 3231 #define PMU_SYS_CLK_SEL_STATE_S 16 3232 /** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0; 3233 * need_des 3234 */ 3235 #define PMU_SYS_CLK_NO_DIV_STATE (BIT(18)) 3236 #define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) 3237 #define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U 3238 #define PMU_SYS_CLK_NO_DIV_STATE_S 18 3239 /** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; 3240 * need_des 3241 */ 3242 #define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) 3243 #define PMU_ICG_SYS_CLK_EN_STATE_M (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S) 3244 #define PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U 3245 #define PMU_ICG_SYS_CLK_EN_STATE_S 19 3246 /** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0; 3247 * need_des 3248 */ 3249 #define PMU_ICG_MODEM_SWITCH_STATE (BIT(20)) 3250 #define PMU_ICG_MODEM_SWITCH_STATE_M (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S) 3251 #define PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U 3252 #define PMU_ICG_MODEM_SWITCH_STATE_S 20 3253 /** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0; 3254 * need_des 3255 */ 3256 #define PMU_ICG_MODEM_CODE_STATE 0x00000003U 3257 #define PMU_ICG_MODEM_CODE_STATE_M (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S) 3258 #define PMU_ICG_MODEM_CODE_STATE_V 0x00000003U 3259 #define PMU_ICG_MODEM_CODE_STATE_S 21 3260 /** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0; 3261 * need_des 3262 */ 3263 #define PMU_ICG_SLP_SEL_STATE (BIT(23)) 3264 #define PMU_ICG_SLP_SEL_STATE_M (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S) 3265 #define PMU_ICG_SLP_SEL_STATE_V 0x00000001U 3266 #define PMU_ICG_SLP_SEL_STATE_S 23 3267 /** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0; 3268 * need_des 3269 */ 3270 #define PMU_ICG_GLOBAL_XTAL_STATE (BIT(24)) 3271 #define PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S) 3272 #define PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U 3273 #define PMU_ICG_GLOBAL_XTAL_STATE_S 24 3274 /** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0; 3275 * need_des 3276 */ 3277 #define PMU_ICG_GLOBAL_PLL_STATE (BIT(25)) 3278 #define PMU_ICG_GLOBAL_PLL_STATE_M (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S) 3279 #define PMU_ICG_GLOBAL_PLL_STATE_V 0x00000001U 3280 #define PMU_ICG_GLOBAL_PLL_STATE_S 25 3281 /** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0; 3282 * need_des 3283 */ 3284 #define PMU_ANA_I2C_ISO_EN_STATE (BIT(26)) 3285 #define PMU_ANA_I2C_ISO_EN_STATE_M (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S) 3286 #define PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U 3287 #define PMU_ANA_I2C_ISO_EN_STATE_S 26 3288 /** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0; 3289 * need_des 3290 */ 3291 #define PMU_ANA_I2C_RETENTION_STATE (BIT(27)) 3292 #define PMU_ANA_I2C_RETENTION_STATE_M (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S) 3293 #define PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U 3294 #define PMU_ANA_I2C_RETENTION_STATE_S 27 3295 /** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0; 3296 * need_des 3297 */ 3298 #define PMU_ANA_XPD_BB_I2C_STATE (BIT(28)) 3299 #define PMU_ANA_XPD_BB_I2C_STATE_M (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S) 3300 #define PMU_ANA_XPD_BB_I2C_STATE_V 0x00000001U 3301 #define PMU_ANA_XPD_BB_I2C_STATE_S 28 3302 /** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0; 3303 * need_des 3304 */ 3305 #define PMU_ANA_XPD_BBPLL_I2C_STATE (BIT(29)) 3306 #define PMU_ANA_XPD_BBPLL_I2C_STATE_M (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S) 3307 #define PMU_ANA_XPD_BBPLL_I2C_STATE_V 0x00000001U 3308 #define PMU_ANA_XPD_BBPLL_I2C_STATE_S 29 3309 /** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0; 3310 * need_des 3311 */ 3312 #define PMU_ANA_XPD_BBPLL_STATE (BIT(30)) 3313 #define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) 3314 #define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U 3315 #define PMU_ANA_XPD_BBPLL_STATE_S 30 3316 /** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; 3317 * need_des 3318 */ 3319 #define PMU_ANA_XPD_XTAL_STATE (BIT(31)) 3320 #define PMU_ANA_XPD_XTAL_STATE_M (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S) 3321 #define PMU_ANA_XPD_XTAL_STATE_V 0x00000001U 3322 #define PMU_ANA_XPD_XTAL_STATE_S 31 3323 3324 /** PMU_CLK_STATE1_REG register 3325 * need_des 3326 */ 3327 #define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x198) 3328 /** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; 3329 * need_des 3330 */ 3331 #define PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU 3332 #define PMU_ICG_FUNC_EN_STATE_M (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S) 3333 #define PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU 3334 #define PMU_ICG_FUNC_EN_STATE_S 0 3335 3336 /** PMU_CLK_STATE2_REG register 3337 * need_des 3338 */ 3339 #define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x19c) 3340 /** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; 3341 * need_des 3342 */ 3343 #define PMU_ICG_APB_EN_STATE 0xFFFFFFFFU 3344 #define PMU_ICG_APB_EN_STATE_M (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S) 3345 #define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU 3346 #define PMU_ICG_APB_EN_STATE_S 0 3347 3348 /** PMU_VDD_SPI_STATUS_REG register 3349 * need_des 3350 */ 3351 #define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a0) 3352 /** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; 3353 * need_des 3354 */ 3355 #define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) 3356 #define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) 3357 #define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U 3358 #define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 3359 3360 /** PMU_DATE_REG register 3361 * need_des 3362 */ 3363 #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) 3364 /** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35676752; 3365 * need_des 3366 */ 3367 #define PMU_PMU_DATE 0x7FFFFFFFU 3368 #define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) 3369 #define PMU_PMU_DATE_V 0x7FFFFFFFU 3370 #define PMU_PMU_DATE_S 0 3371 /** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; 3372 * need_des 3373 */ 3374 #define PMU_CLK_EN (BIT(31)) 3375 #define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) 3376 #define PMU_CLK_EN_V 0x00000001U 3377 #define PMU_CLK_EN_S 31 3378 3379 #ifdef __cplusplus 3380 } 3381 #endif 3382
