1 /**
2  * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
3  *
4  *  SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdint.h>
9 #include "soc/soc.h"
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13 
14 /** PCR_UART0_CONF_REG register
15  *  UART0 configuration register
16  */
17 #define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
18 /** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
19  *  Set 1 to enable uart0 apb clock
20  */
21 #define PCR_UART0_CLK_EN    (BIT(0))
22 #define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
23 #define PCR_UART0_CLK_EN_V  0x00000001U
24 #define PCR_UART0_CLK_EN_S  0
25 /** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
26  *  Set 0 to reset uart0 module
27  */
28 #define PCR_UART0_RST_EN    (BIT(1))
29 #define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
30 #define PCR_UART0_RST_EN_V  0x00000001U
31 #define PCR_UART0_RST_EN_S  1
32 /** PCR_UART0_READY : RO; bitpos: [2]; default: 1;
33  *  Query this field after reset uart0 module
34  */
35 #define PCR_UART0_READY    (BIT(2))
36 #define PCR_UART0_READY_M  (PCR_UART0_READY_V << PCR_UART0_READY_S)
37 #define PCR_UART0_READY_V  0x00000001U
38 #define PCR_UART0_READY_S  2
39 
40 /** PCR_UART0_SCLK_CONF_REG register
41  *  UART0_SCLK configuration register
42  */
43 #define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
44 /** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
45  *  The  denominator of the frequency divider factor of the uart0 function clock.
46  */
47 #define PCR_UART0_SCLK_DIV_A    0x0000003FU
48 #define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
49 #define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
50 #define PCR_UART0_SCLK_DIV_A_S  0
51 /** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
52  *  The numerator of the frequency divider factor of the uart0 function clock.
53  */
54 #define PCR_UART0_SCLK_DIV_B    0x0000003FU
55 #define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
56 #define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
57 #define PCR_UART0_SCLK_DIV_B_S  6
58 /** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
59  *  The integral part of the frequency divider factor of the uart0 function clock.
60  */
61 #define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
62 #define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
63 #define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
64 #define PCR_UART0_SCLK_DIV_NUM_S  12
65 /** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
66  *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
67  *  FOSC, 3(default): XTAL.
68  */
69 #define PCR_UART0_SCLK_SEL    0x00000003U
70 #define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
71 #define PCR_UART0_SCLK_SEL_V  0x00000003U
72 #define PCR_UART0_SCLK_SEL_S  20
73 /** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
74  *  Set 1 to enable uart0 function clock
75  */
76 #define PCR_UART0_SCLK_EN    (BIT(22))
77 #define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
78 #define PCR_UART0_SCLK_EN_V  0x00000001U
79 #define PCR_UART0_SCLK_EN_S  22
80 
81 /** PCR_UART0_PD_CTRL_REG register
82  *  UART0 power control register
83  */
84 #define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
85 /** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
86  *  Set this bit to force power down UART0 memory.
87  */
88 #define PCR_UART0_MEM_FORCE_PU    (BIT(1))
89 #define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
90 #define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
91 #define PCR_UART0_MEM_FORCE_PU_S  1
92 /** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
93  *  Set this bit to force power up UART0 memory.
94  */
95 #define PCR_UART0_MEM_FORCE_PD    (BIT(2))
96 #define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
97 #define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
98 #define PCR_UART0_MEM_FORCE_PD_S  2
99 
100 /** PCR_UART1_CONF_REG register
101  *  UART1 configuration register
102  */
103 #define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
104 /** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
105  *  Set 1 to enable uart1 apb clock
106  */
107 #define PCR_UART1_CLK_EN    (BIT(0))
108 #define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
109 #define PCR_UART1_CLK_EN_V  0x00000001U
110 #define PCR_UART1_CLK_EN_S  0
111 /** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
112  *  Set 0 to reset uart1 module
113  */
114 #define PCR_UART1_RST_EN    (BIT(1))
115 #define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
116 #define PCR_UART1_RST_EN_V  0x00000001U
117 #define PCR_UART1_RST_EN_S  1
118 /** PCR_UART1_READY : RO; bitpos: [2]; default: 1;
119  *  Query this field after reset uart1 module
120  */
121 #define PCR_UART1_READY    (BIT(2))
122 #define PCR_UART1_READY_M  (PCR_UART1_READY_V << PCR_UART1_READY_S)
123 #define PCR_UART1_READY_V  0x00000001U
124 #define PCR_UART1_READY_S  2
125 
126 /** PCR_UART1_SCLK_CONF_REG register
127  *  UART1_SCLK configuration register
128  */
129 #define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
130 /** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
131  *  The  denominator of the frequency divider factor of the uart1 function clock.
132  */
133 #define PCR_UART1_SCLK_DIV_A    0x0000003FU
134 #define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
135 #define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
136 #define PCR_UART1_SCLK_DIV_A_S  0
137 /** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
138  *  The numerator of the frequency divider factor of the uart1 function clock.
139  */
140 #define PCR_UART1_SCLK_DIV_B    0x0000003FU
141 #define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
142 #define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
143 #define PCR_UART1_SCLK_DIV_B_S  6
144 /** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
145  *  The integral part of the frequency divider factor of the uart1 function clock.
146  */
147 #define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
148 #define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
149 #define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
150 #define PCR_UART1_SCLK_DIV_NUM_S  12
151 /** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
152  *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
153  *  FOSC, 3(default): XTAL.
154  */
155 #define PCR_UART1_SCLK_SEL    0x00000003U
156 #define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
157 #define PCR_UART1_SCLK_SEL_V  0x00000003U
158 #define PCR_UART1_SCLK_SEL_S  20
159 /** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
160  *  Set 1 to enable uart0 function clock
161  */
162 #define PCR_UART1_SCLK_EN    (BIT(22))
163 #define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
164 #define PCR_UART1_SCLK_EN_V  0x00000001U
165 #define PCR_UART1_SCLK_EN_S  22
166 
167 /** PCR_UART1_PD_CTRL_REG register
168  *  UART1 power control register
169  */
170 #define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
171 /** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
172  *  Set this bit to force power down UART1 memory.
173  */
174 #define PCR_UART1_MEM_FORCE_PU    (BIT(1))
175 #define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
176 #define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
177 #define PCR_UART1_MEM_FORCE_PU_S  1
178 /** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
179  *  Set this bit to force power up UART1 memory.
180  */
181 #define PCR_UART1_MEM_FORCE_PD    (BIT(2))
182 #define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
183 #define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
184 #define PCR_UART1_MEM_FORCE_PD_S  2
185 
186 /** PCR_MSPI_CONF_REG register
187  *  MSPI configuration register
188  */
189 #define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
190 /** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
191  *  Set 1 to enable mspi clock, include mspi pll clock
192  */
193 #define PCR_MSPI_CLK_EN    (BIT(0))
194 #define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
195 #define PCR_MSPI_CLK_EN_V  0x00000001U
196 #define PCR_MSPI_CLK_EN_S  0
197 /** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
198  *  Set 0 to reset mspi module
199  */
200 #define PCR_MSPI_RST_EN    (BIT(1))
201 #define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
202 #define PCR_MSPI_RST_EN_V  0x00000001U
203 #define PCR_MSPI_RST_EN_S  1
204 /** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
205  *  Set 1 to enable mspi pll clock
206  */
207 #define PCR_MSPI_PLL_CLK_EN    (BIT(2))
208 #define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
209 #define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
210 #define PCR_MSPI_PLL_CLK_EN_S  2
211 /** PCR_MSPI_CLK_SEL : R/W; bitpos: [4:3]; default: 0;
212  *  set this field to select clock-source.
213  */
214 #define PCR_MSPI_CLK_SEL    0x00000003U
215 #define PCR_MSPI_CLK_SEL_M  (PCR_MSPI_CLK_SEL_V << PCR_MSPI_CLK_SEL_S)
216 #define PCR_MSPI_CLK_SEL_V  0x00000003U
217 #define PCR_MSPI_CLK_SEL_S  3
218 /** PCR_MSPI_READY : RO; bitpos: [5]; default: 1;
219  *  Query this field after reset mspi module
220  */
221 #define PCR_MSPI_READY    (BIT(5))
222 #define PCR_MSPI_READY_M  (PCR_MSPI_READY_V << PCR_MSPI_READY_S)
223 #define PCR_MSPI_READY_V  0x00000001U
224 #define PCR_MSPI_READY_S  5
225 
226 /** PCR_MSPI_CLK_CONF_REG register
227  *  MSPI_CLK configuration register
228  */
229 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
230 /** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
231  *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
232  *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
233  *  low-speed clock-source such as XTAL/FOSC.
234  */
235 #define PCR_MSPI_FAST_DIV_NUM    0x000000FFU
236 #define PCR_MSPI_FAST_DIV_NUM_M  (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S)
237 #define PCR_MSPI_FAST_DIV_NUM_V  0x000000FFU
238 #define PCR_MSPI_FAST_DIV_NUM_S  0
239 
240 /** PCR_I2C0_CONF_REG register
241  *  I2C configuration register
242  */
243 #define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x20)
244 /** PCR_I2C0_CLK_EN : R/W; bitpos: [0]; default: 1;
245  *  Set 1 to enable i2c apb clock
246  */
247 #define PCR_I2C0_CLK_EN    (BIT(0))
248 #define PCR_I2C0_CLK_EN_M  (PCR_I2C0_CLK_EN_V << PCR_I2C0_CLK_EN_S)
249 #define PCR_I2C0_CLK_EN_V  0x00000001U
250 #define PCR_I2C0_CLK_EN_S  0
251 /** PCR_I2C0_RST_EN : R/W; bitpos: [1]; default: 0;
252  *  Set 0 to reset i2c module
253  */
254 #define PCR_I2C0_RST_EN    (BIT(1))
255 #define PCR_I2C0_RST_EN_M  (PCR_I2C0_RST_EN_V << PCR_I2C0_RST_EN_S)
256 #define PCR_I2C0_RST_EN_V  0x00000001U
257 #define PCR_I2C0_RST_EN_S  1
258 /** PCR_I2C0_READY : RO; bitpos: [2]; default: 1;
259  *  Query this field after reset i2c0 module
260  */
261 #define PCR_I2C0_READY    (BIT(2))
262 #define PCR_I2C0_READY_M  (PCR_I2C0_READY_V << PCR_I2C0_READY_S)
263 #define PCR_I2C0_READY_V  0x00000001U
264 #define PCR_I2C0_READY_S  2
265 
266 /** PCR_I2C0_SCLK_CONF_REG register
267  *  I2C_SCLK configuration register
268  */
269 #define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
270 /** PCR_I2C0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
271  *  The  denominator of the frequency divider factor of the i2c function clock.
272  */
273 #define PCR_I2C0_SCLK_DIV_A    0x0000003FU
274 #define PCR_I2C0_SCLK_DIV_A_M  (PCR_I2C0_SCLK_DIV_A_V << PCR_I2C0_SCLK_DIV_A_S)
275 #define PCR_I2C0_SCLK_DIV_A_V  0x0000003FU
276 #define PCR_I2C0_SCLK_DIV_A_S  0
277 /** PCR_I2C0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
278  *  The numerator of the frequency divider factor of the i2c function clock.
279  */
280 #define PCR_I2C0_SCLK_DIV_B    0x0000003FU
281 #define PCR_I2C0_SCLK_DIV_B_M  (PCR_I2C0_SCLK_DIV_B_V << PCR_I2C0_SCLK_DIV_B_S)
282 #define PCR_I2C0_SCLK_DIV_B_V  0x0000003FU
283 #define PCR_I2C0_SCLK_DIV_B_S  6
284 /** PCR_I2C0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
285  *  The integral part of the frequency divider factor of the i2c function clock.
286  */
287 #define PCR_I2C0_SCLK_DIV_NUM    0x000000FFU
288 #define PCR_I2C0_SCLK_DIV_NUM_M  (PCR_I2C0_SCLK_DIV_NUM_V << PCR_I2C0_SCLK_DIV_NUM_S)
289 #define PCR_I2C0_SCLK_DIV_NUM_V  0x000000FFU
290 #define PCR_I2C0_SCLK_DIV_NUM_S  12
291 /** PCR_I2C0_SCLK_SEL : R/W; bitpos: [20]; default: 0;
292  *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
293  */
294 #define PCR_I2C0_SCLK_SEL    (BIT(20))
295 #define PCR_I2C0_SCLK_SEL_M  (PCR_I2C0_SCLK_SEL_V << PCR_I2C0_SCLK_SEL_S)
296 #define PCR_I2C0_SCLK_SEL_V  0x00000001U
297 #define PCR_I2C0_SCLK_SEL_S  20
298 /** PCR_I2C0_SCLK_EN : R/W; bitpos: [22]; default: 1;
299  *  Set 1 to enable i2c function clock
300  */
301 #define PCR_I2C0_SCLK_EN    (BIT(22))
302 #define PCR_I2C0_SCLK_EN_M  (PCR_I2C0_SCLK_EN_V << PCR_I2C0_SCLK_EN_S)
303 #define PCR_I2C0_SCLK_EN_V  0x00000001U
304 #define PCR_I2C0_SCLK_EN_S  22
305 
306 /** PCR_I2C1_CONF_REG register
307  *  I2C configuration register
308  */
309 #define PCR_I2C1_CONF_REG (DR_REG_PCR_BASE + 0x28)
310 /** PCR_I2C1_CLK_EN : R/W; bitpos: [0]; default: 1;
311  *  Set 1 to enable i2c apb clock
312  */
313 #define PCR_I2C1_CLK_EN    (BIT(0))
314 #define PCR_I2C1_CLK_EN_M  (PCR_I2C1_CLK_EN_V << PCR_I2C1_CLK_EN_S)
315 #define PCR_I2C1_CLK_EN_V  0x00000001U
316 #define PCR_I2C1_CLK_EN_S  0
317 /** PCR_I2C1_RST_EN : R/W; bitpos: [1]; default: 0;
318  *  Set 0 to reset i2c module
319  */
320 #define PCR_I2C1_RST_EN    (BIT(1))
321 #define PCR_I2C1_RST_EN_M  (PCR_I2C1_RST_EN_V << PCR_I2C1_RST_EN_S)
322 #define PCR_I2C1_RST_EN_V  0x00000001U
323 #define PCR_I2C1_RST_EN_S  1
324 /** PCR_I2C1_READY : RO; bitpos: [2]; default: 1;
325  *  Query this field after reset i2c1 module
326  */
327 #define PCR_I2C1_READY    (BIT(2))
328 #define PCR_I2C1_READY_M  (PCR_I2C1_READY_V << PCR_I2C1_READY_S)
329 #define PCR_I2C1_READY_V  0x00000001U
330 #define PCR_I2C1_READY_S  2
331 
332 /** PCR_I2C1_SCLK_CONF_REG register
333  *  I2C_SCLK configuration register
334  */
335 #define PCR_I2C1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x2c)
336 /** PCR_I2C1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
337  *  The  denominator of the frequency divider factor of the i2c function clock.
338  */
339 #define PCR_I2C1_SCLK_DIV_A    0x0000003FU
340 #define PCR_I2C1_SCLK_DIV_A_M  (PCR_I2C1_SCLK_DIV_A_V << PCR_I2C1_SCLK_DIV_A_S)
341 #define PCR_I2C1_SCLK_DIV_A_V  0x0000003FU
342 #define PCR_I2C1_SCLK_DIV_A_S  0
343 /** PCR_I2C1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
344  *  The numerator of the frequency divider factor of the i2c function clock.
345  */
346 #define PCR_I2C1_SCLK_DIV_B    0x0000003FU
347 #define PCR_I2C1_SCLK_DIV_B_M  (PCR_I2C1_SCLK_DIV_B_V << PCR_I2C1_SCLK_DIV_B_S)
348 #define PCR_I2C1_SCLK_DIV_B_V  0x0000003FU
349 #define PCR_I2C1_SCLK_DIV_B_S  6
350 /** PCR_I2C1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
351  *  The integral part of the frequency divider factor of the i2c function clock.
352  */
353 #define PCR_I2C1_SCLK_DIV_NUM    0x000000FFU
354 #define PCR_I2C1_SCLK_DIV_NUM_M  (PCR_I2C1_SCLK_DIV_NUM_V << PCR_I2C1_SCLK_DIV_NUM_S)
355 #define PCR_I2C1_SCLK_DIV_NUM_V  0x000000FFU
356 #define PCR_I2C1_SCLK_DIV_NUM_S  12
357 /** PCR_I2C1_SCLK_SEL : R/W; bitpos: [20]; default: 0;
358  *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
359  */
360 #define PCR_I2C1_SCLK_SEL    (BIT(20))
361 #define PCR_I2C1_SCLK_SEL_M  (PCR_I2C1_SCLK_SEL_V << PCR_I2C1_SCLK_SEL_S)
362 #define PCR_I2C1_SCLK_SEL_V  0x00000001U
363 #define PCR_I2C1_SCLK_SEL_S  20
364 /** PCR_I2C1_SCLK_EN : R/W; bitpos: [22]; default: 1;
365  *  Set 1 to enable i2c function clock
366  */
367 #define PCR_I2C1_SCLK_EN    (BIT(22))
368 #define PCR_I2C1_SCLK_EN_M  (PCR_I2C1_SCLK_EN_V << PCR_I2C1_SCLK_EN_S)
369 #define PCR_I2C1_SCLK_EN_V  0x00000001U
370 #define PCR_I2C1_SCLK_EN_S  22
371 
372 /** PCR_UHCI_CONF_REG register
373  *  UHCI configuration register
374  */
375 #define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x30)
376 /** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
377  *  Set 1 to enable uhci clock
378  */
379 #define PCR_UHCI_CLK_EN    (BIT(0))
380 #define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
381 #define PCR_UHCI_CLK_EN_V  0x00000001U
382 #define PCR_UHCI_CLK_EN_S  0
383 /** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
384  *  Set 0 to reset uhci module
385  */
386 #define PCR_UHCI_RST_EN    (BIT(1))
387 #define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
388 #define PCR_UHCI_RST_EN_V  0x00000001U
389 #define PCR_UHCI_RST_EN_S  1
390 /** PCR_UHCI_READY : RO; bitpos: [2]; default: 1;
391  *  Query this field after reset uhci module
392  */
393 #define PCR_UHCI_READY    (BIT(2))
394 #define PCR_UHCI_READY_M  (PCR_UHCI_READY_V << PCR_UHCI_READY_S)
395 #define PCR_UHCI_READY_V  0x00000001U
396 #define PCR_UHCI_READY_S  2
397 
398 /** PCR_RMT_CONF_REG register
399  *  RMT configuration register
400  */
401 #define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x34)
402 /** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
403  *  Set 1 to enable rmt apb clock
404  */
405 #define PCR_RMT_CLK_EN    (BIT(0))
406 #define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
407 #define PCR_RMT_CLK_EN_V  0x00000001U
408 #define PCR_RMT_CLK_EN_S  0
409 /** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
410  *  Set 0 to reset rmt module
411  */
412 #define PCR_RMT_RST_EN    (BIT(1))
413 #define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
414 #define PCR_RMT_RST_EN_V  0x00000001U
415 #define PCR_RMT_RST_EN_S  1
416 /** PCR_RMT_READY : RO; bitpos: [2]; default: 1;
417  *  Query this field after reset rmt module
418  */
419 #define PCR_RMT_READY    (BIT(2))
420 #define PCR_RMT_READY_M  (PCR_RMT_READY_V << PCR_RMT_READY_S)
421 #define PCR_RMT_READY_V  0x00000001U
422 #define PCR_RMT_READY_S  2
423 
424 /** PCR_RMT_SCLK_CONF_REG register
425  *  RMT_SCLK configuration register
426  */
427 #define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
428 /** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
429  *  The  denominator of the frequency divider factor of the rmt function clock.
430  */
431 #define PCR_RMT_SCLK_DIV_A    0x0000003FU
432 #define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
433 #define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
434 #define PCR_RMT_SCLK_DIV_A_S  0
435 /** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
436  *  The numerator of the frequency divider factor of the rmt function clock.
437  */
438 #define PCR_RMT_SCLK_DIV_B    0x0000003FU
439 #define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
440 #define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
441 #define PCR_RMT_SCLK_DIV_B_S  6
442 /** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
443  *  The integral part of the frequency divider factor of the rmt function clock.
444  */
445 #define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
446 #define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
447 #define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
448 #define PCR_RMT_SCLK_DIV_NUM_S  12
449 /** PCR_RMT_SCLK_SEL : R/W; bitpos: [20]; default: 1;
450  *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
451  *  80MHz, 2: FOSC, 3: XTAL.
452  */
453 #define PCR_RMT_SCLK_SEL    (BIT(20))
454 #define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
455 #define PCR_RMT_SCLK_SEL_V  0x00000001U
456 #define PCR_RMT_SCLK_SEL_S  20
457 /** PCR_RMT_SCLK_EN : R/W; bitpos: [21]; default: 1;
458  *  Set 1 to enable rmt function clock
459  */
460 #define PCR_RMT_SCLK_EN    (BIT(21))
461 #define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
462 #define PCR_RMT_SCLK_EN_V  0x00000001U
463 #define PCR_RMT_SCLK_EN_S  21
464 
465 /** PCR_LEDC_CONF_REG register
466  *  LEDC configuration register
467  */
468 #define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x3c)
469 /** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
470  *  Set 1 to enable ledc apb clock
471  */
472 #define PCR_LEDC_CLK_EN    (BIT(0))
473 #define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
474 #define PCR_LEDC_CLK_EN_V  0x00000001U
475 #define PCR_LEDC_CLK_EN_S  0
476 /** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
477  *  Set 0 to reset ledc module
478  */
479 #define PCR_LEDC_RST_EN    (BIT(1))
480 #define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
481 #define PCR_LEDC_RST_EN_V  0x00000001U
482 #define PCR_LEDC_RST_EN_S  1
483 /** PCR_LEDC_READY : RO; bitpos: [2]; default: 1;
484  *  Query this field after reset ledc module
485  */
486 #define PCR_LEDC_READY    (BIT(2))
487 #define PCR_LEDC_READY_M  (PCR_LEDC_READY_V << PCR_LEDC_READY_S)
488 #define PCR_LEDC_READY_V  0x00000001U
489 #define PCR_LEDC_READY_S  2
490 
491 /** PCR_LEDC_SCLK_CONF_REG register
492  *  LEDC_SCLK configuration register
493  */
494 #define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
495 /** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
496  *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
497  *  80MHz, 2: FOSC, 3: XTAL.
498  */
499 #define PCR_LEDC_SCLK_SEL    0x00000003U
500 #define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
501 #define PCR_LEDC_SCLK_SEL_V  0x00000003U
502 #define PCR_LEDC_SCLK_SEL_S  20
503 /** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
504  *  Set 1 to enable ledc function clock
505  */
506 #define PCR_LEDC_SCLK_EN    (BIT(22))
507 #define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
508 #define PCR_LEDC_SCLK_EN_V  0x00000001U
509 #define PCR_LEDC_SCLK_EN_S  22
510 
511 /** PCR_TIMERGROUP0_CONF_REG register
512  *  TIMERGROUP0 configuration register
513  */
514 #define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x44)
515 /** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
516  *  Set 1 to enable timer_group0 apb clock
517  */
518 #define PCR_TG0_CLK_EN    (BIT(0))
519 #define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
520 #define PCR_TG0_CLK_EN_V  0x00000001U
521 #define PCR_TG0_CLK_EN_S  0
522 /** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
523  *  Set 0 to reset timer_group0 module
524  */
525 #define PCR_TG0_RST_EN    (BIT(1))
526 #define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
527 #define PCR_TG0_RST_EN_V  0x00000001U
528 #define PCR_TG0_RST_EN_S  1
529 /** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1;
530  *  Query this field after reset timer_group0 wdt module
531  */
532 #define PCR_TG0_WDT_READY    (BIT(2))
533 #define PCR_TG0_WDT_READY_M  (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S)
534 #define PCR_TG0_WDT_READY_V  0x00000001U
535 #define PCR_TG0_WDT_READY_S  2
536 /** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1;
537  *  Query this field after reset timer_group0 timer0 module
538  */
539 #define PCR_TG0_TIMER0_READY    (BIT(3))
540 #define PCR_TG0_TIMER0_READY_M  (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S)
541 #define PCR_TG0_TIMER0_READY_V  0x00000001U
542 #define PCR_TG0_TIMER0_READY_S  3
543 /** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1;
544  *  reserved
545  */
546 #define PCR_TG0_TIMER1_READY    (BIT(4))
547 #define PCR_TG0_TIMER1_READY_M  (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S)
548 #define PCR_TG0_TIMER1_READY_V  0x00000001U
549 #define PCR_TG0_TIMER1_READY_S  4
550 
551 /** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
552  *  TIMERGROUP0_TIMER_CLK configuration register
553  */
554 #define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48)
555 /** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
556  *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
557  *  reserved.
558  */
559 #define PCR_TG0_TIMER_CLK_SEL    0x00000003U
560 #define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
561 #define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
562 #define PCR_TG0_TIMER_CLK_SEL_S  20
563 /** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
564  *  Set 1 to enable timer_group0 timer clock
565  */
566 #define PCR_TG0_TIMER_CLK_EN    (BIT(22))
567 #define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
568 #define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
569 #define PCR_TG0_TIMER_CLK_EN_S  22
570 
571 /** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
572  *  TIMERGROUP0_WDT_CLK configuration register
573  */
574 #define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c)
575 /** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
576  *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
577  *  reserved.
578  */
579 #define PCR_TG0_WDT_CLK_SEL    0x00000003U
580 #define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
581 #define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
582 #define PCR_TG0_WDT_CLK_SEL_S  20
583 /** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
584  *  Set 1 to enable timer_group0 wdt clock
585  */
586 #define PCR_TG0_WDT_CLK_EN    (BIT(22))
587 #define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
588 #define PCR_TG0_WDT_CLK_EN_V  0x00000001U
589 #define PCR_TG0_WDT_CLK_EN_S  22
590 
591 /** PCR_TIMERGROUP1_CONF_REG register
592  *  TIMERGROUP1 configuration register
593  */
594 #define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x50)
595 /** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
596  *  Set 1 to enable timer_group1 apb clock
597  */
598 #define PCR_TG1_CLK_EN    (BIT(0))
599 #define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
600 #define PCR_TG1_CLK_EN_V  0x00000001U
601 #define PCR_TG1_CLK_EN_S  0
602 /** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
603  *  Set 0 to reset timer_group1 module
604  */
605 #define PCR_TG1_RST_EN    (BIT(1))
606 #define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
607 #define PCR_TG1_RST_EN_V  0x00000001U
608 #define PCR_TG1_RST_EN_S  1
609 /** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1;
610  *  Query this field after reset timer_group1 wdt module
611  */
612 #define PCR_TG1_WDT_READY    (BIT(2))
613 #define PCR_TG1_WDT_READY_M  (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S)
614 #define PCR_TG1_WDT_READY_V  0x00000001U
615 #define PCR_TG1_WDT_READY_S  2
616 /** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1;
617  *  Query this field after reset timer_group1 timer0 module
618  */
619 #define PCR_TG1_TIMER0_READY    (BIT(3))
620 #define PCR_TG1_TIMER0_READY_M  (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S)
621 #define PCR_TG1_TIMER0_READY_V  0x00000001U
622 #define PCR_TG1_TIMER0_READY_S  3
623 /** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1;
624  *  reserved
625  */
626 #define PCR_TG1_TIMER1_READY    (BIT(4))
627 #define PCR_TG1_TIMER1_READY_M  (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S)
628 #define PCR_TG1_TIMER1_READY_V  0x00000001U
629 #define PCR_TG1_TIMER1_READY_S  4
630 
631 /** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
632  *  TIMERGROUP1_TIMER_CLK configuration register
633  */
634 #define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54)
635 /** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
636  *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
637  *  reserved.
638  */
639 #define PCR_TG1_TIMER_CLK_SEL    0x00000003U
640 #define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
641 #define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
642 #define PCR_TG1_TIMER_CLK_SEL_S  20
643 /** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
644  *  Set 1 to enable timer_group1 timer clock
645  */
646 #define PCR_TG1_TIMER_CLK_EN    (BIT(22))
647 #define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
648 #define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
649 #define PCR_TG1_TIMER_CLK_EN_S  22
650 
651 /** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
652  *  TIMERGROUP1_WDT_CLK configuration register
653  */
654 #define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58)
655 /** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
656  *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
657  *  reserved.
658  */
659 #define PCR_TG1_WDT_CLK_SEL    0x00000003U
660 #define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
661 #define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
662 #define PCR_TG1_WDT_CLK_SEL_S  20
663 /** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
664  *  Set 1 to enable timer_group0 wdt clock
665  */
666 #define PCR_TG1_WDT_CLK_EN    (BIT(22))
667 #define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
668 #define PCR_TG1_WDT_CLK_EN_V  0x00000001U
669 #define PCR_TG1_WDT_CLK_EN_S  22
670 
671 /** PCR_SYSTIMER_CONF_REG register
672  *  SYSTIMER configuration register
673  */
674 #define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x5c)
675 /** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
676  *  Set 1 to enable systimer apb clock
677  */
678 #define PCR_SYSTIMER_CLK_EN    (BIT(0))
679 #define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
680 #define PCR_SYSTIMER_CLK_EN_V  0x00000001U
681 #define PCR_SYSTIMER_CLK_EN_S  0
682 /** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
683  *  Set 0 to reset systimer module
684  */
685 #define PCR_SYSTIMER_RST_EN    (BIT(1))
686 #define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
687 #define PCR_SYSTIMER_RST_EN_V  0x00000001U
688 #define PCR_SYSTIMER_RST_EN_S  1
689 /** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1;
690  *  Query this field after reset systimer module
691  */
692 #define PCR_SYSTIMER_READY    (BIT(2))
693 #define PCR_SYSTIMER_READY_M  (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S)
694 #define PCR_SYSTIMER_READY_V  0x00000001U
695 #define PCR_SYSTIMER_READY_S  2
696 
697 /** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
698  *  SYSTIMER_FUNC_CLK configuration register
699  */
700 #define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
701 /** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
702  *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
703  */
704 #define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
705 #define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
706 #define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
707 #define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
708 /** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
709  *  Set 1 to enable systimer function clock
710  */
711 #define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
712 #define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
713 #define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
714 #define PCR_SYSTIMER_FUNC_CLK_EN_S  22
715 
716 /** PCR_TWAI0_CONF_REG register
717  *  TWAI0 configuration register
718  */
719 #define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x64)
720 /** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
721  *  Set 1 to enable twai0 apb clock
722  */
723 #define PCR_TWAI0_CLK_EN    (BIT(0))
724 #define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
725 #define PCR_TWAI0_CLK_EN_V  0x00000001U
726 #define PCR_TWAI0_CLK_EN_S  0
727 /** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
728  *  Set 0 to reset twai0 module
729  */
730 #define PCR_TWAI0_RST_EN    (BIT(1))
731 #define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
732 #define PCR_TWAI0_RST_EN_V  0x00000001U
733 #define PCR_TWAI0_RST_EN_S  1
734 /** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1;
735  *  Query this field after reset twai0 module
736  */
737 #define PCR_TWAI0_READY    (BIT(2))
738 #define PCR_TWAI0_READY_M  (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S)
739 #define PCR_TWAI0_READY_V  0x00000001U
740 #define PCR_TWAI0_READY_S  2
741 
742 /** PCR_TWAI0_FUNC_CLK_CONF_REG register
743  *  TWAI0_FUNC_CLK configuration register
744  */
745 #define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
746 /** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
747  *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
748  */
749 #define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
750 #define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
751 #define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
752 #define PCR_TWAI0_FUNC_CLK_SEL_S  20
753 /** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
754  *  Set 1 to enable twai0 function clock
755  */
756 #define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
757 #define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
758 #define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
759 #define PCR_TWAI0_FUNC_CLK_EN_S  22
760 
761 /** PCR_I2S_CONF_REG register
762  *  I2S configuration register
763  */
764 #define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
765 /** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
766  *  Set 1 to enable i2s apb clock
767  */
768 #define PCR_I2S_CLK_EN    (BIT(0))
769 #define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
770 #define PCR_I2S_CLK_EN_V  0x00000001U
771 #define PCR_I2S_CLK_EN_S  0
772 /** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
773  *  Set 0 to reset i2s module
774  */
775 #define PCR_I2S_RST_EN    (BIT(1))
776 #define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
777 #define PCR_I2S_RST_EN_V  0x00000001U
778 #define PCR_I2S_RST_EN_S  1
779 /** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1;
780  *  Query this field before using i2s rx function, after reset i2s module
781  */
782 #define PCR_I2S_RX_READY    (BIT(2))
783 #define PCR_I2S_RX_READY_M  (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S)
784 #define PCR_I2S_RX_READY_V  0x00000001U
785 #define PCR_I2S_RX_READY_S  2
786 /** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1;
787  *  Query this field before using i2s tx function, after reset i2s module
788  */
789 #define PCR_I2S_TX_READY    (BIT(3))
790 #define PCR_I2S_TX_READY_M  (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S)
791 #define PCR_I2S_TX_READY_V  0x00000001U
792 #define PCR_I2S_TX_READY_S  3
793 
794 /** PCR_I2S_TX_CLKM_CONF_REG register
795  *  I2S_TX_CLKM configuration register
796  */
797 #define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
798 /** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
799  *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
800  *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
801  *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
802  *  (n+1)-div] + y * (n+1)-div.
803  */
804 #define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
805 #define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
806 #define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
807 #define PCR_I2S_TX_CLKM_DIV_NUM_S  12
808 /** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
809  *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
810  *  I2S_MCLK_in.
811  */
812 #define PCR_I2S_TX_CLKM_SEL    0x00000003U
813 #define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
814 #define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
815 #define PCR_I2S_TX_CLKM_SEL_S  20
816 /** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
817  *  Set 1 to enable i2s_tx function clock
818  */
819 #define PCR_I2S_TX_CLKM_EN    (BIT(22))
820 #define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
821 #define PCR_I2S_TX_CLKM_EN_V  0x00000001U
822 #define PCR_I2S_TX_CLKM_EN_S  22
823 
824 /** PCR_I2S_TX_CLKM_DIV_CONF_REG register
825  *  I2S_TX_CLKM_DIV configuration register
826  */
827 #define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
828 /** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
829  *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
830  *  I2S_TX_CLKM_DIV_Z is (a-b).
831  */
832 #define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
833 #define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
834 #define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
835 #define PCR_I2S_TX_CLKM_DIV_Z_S  0
836 /** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
837  *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
838  *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
839  */
840 #define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
841 #define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
842 #define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
843 #define PCR_I2S_TX_CLKM_DIV_Y_S  9
844 /** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
845  *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
846  *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
847  */
848 #define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
849 #define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
850 #define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
851 #define PCR_I2S_TX_CLKM_DIV_X_S  18
852 /** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
853  *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
854  *  I2S_TX_CLKM_DIV_YN1 is 1.
855  */
856 #define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
857 #define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
858 #define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
859 #define PCR_I2S_TX_CLKM_DIV_YN1_S  27
860 
861 /** PCR_I2S_RX_CLKM_CONF_REG register
862  *  I2S_RX_CLKM configuration register
863  */
864 #define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
865 /** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
866  *  Integral I2S clock divider value
867  */
868 #define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
869 #define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
870 #define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
871 #define PCR_I2S_RX_CLKM_DIV_NUM_S  12
872 /** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
873  *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
874  */
875 #define PCR_I2S_RX_CLKM_SEL    0x00000003U
876 #define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
877 #define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
878 #define PCR_I2S_RX_CLKM_SEL_S  20
879 /** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
880  *  Set 1 to enable i2s_rx function clock
881  */
882 #define PCR_I2S_RX_CLKM_EN    (BIT(22))
883 #define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
884 #define PCR_I2S_RX_CLKM_EN_V  0x00000001U
885 #define PCR_I2S_RX_CLKM_EN_S  22
886 /** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
887  *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
888  */
889 #define PCR_I2S_MCLK_SEL    (BIT(23))
890 #define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
891 #define PCR_I2S_MCLK_SEL_V  0x00000001U
892 #define PCR_I2S_MCLK_SEL_S  23
893 
894 /** PCR_I2S_RX_CLKM_DIV_CONF_REG register
895  *  I2S_RX_CLKM_DIV configuration register
896  */
897 #define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
898 /** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
899  *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
900  *  I2S_RX_CLKM_DIV_Z is (a-b).
901  */
902 #define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
903 #define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
904 #define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
905 #define PCR_I2S_RX_CLKM_DIV_Z_S  0
906 /** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
907  *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
908  *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
909  */
910 #define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
911 #define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
912 #define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
913 #define PCR_I2S_RX_CLKM_DIV_Y_S  9
914 /** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
915  *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
916  *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
917  */
918 #define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
919 #define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
920 #define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
921 #define PCR_I2S_RX_CLKM_DIV_X_S  18
922 /** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
923  *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
924  *  I2S_RX_CLKM_DIV_YN1 is 1.
925  */
926 #define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
927 #define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
928 #define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
929 #define PCR_I2S_RX_CLKM_DIV_YN1_S  27
930 
931 /** PCR_SARADC_CONF_REG register
932  *  SARADC configuration register
933  */
934 #define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
935 /** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
936  *  no use
937  */
938 #define PCR_SARADC_CLK_EN    (BIT(0))
939 #define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
940 #define PCR_SARADC_CLK_EN_V  0x00000001U
941 #define PCR_SARADC_CLK_EN_S  0
942 /** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
943  *  Set 0 to reset function_register of saradc module
944  */
945 #define PCR_SARADC_RST_EN    (BIT(1))
946 #define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
947 #define PCR_SARADC_RST_EN_V  0x00000001U
948 #define PCR_SARADC_RST_EN_S  1
949 /** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
950  *  Set 1 to enable saradc apb clock
951  */
952 #define PCR_SARADC_REG_CLK_EN    (BIT(2))
953 #define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
954 #define PCR_SARADC_REG_CLK_EN_V  0x00000001U
955 #define PCR_SARADC_REG_CLK_EN_S  2
956 /** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
957  *  Set 0 to reset apb_register of saradc module
958  */
959 #define PCR_SARADC_REG_RST_EN    (BIT(3))
960 #define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
961 #define PCR_SARADC_REG_RST_EN_V  0x00000001U
962 #define PCR_SARADC_REG_RST_EN_S  3
963 
964 /** PCR_SARADC_CLKM_CONF_REG register
965  *  SARADC_CLKM configuration register
966  */
967 #define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
968 /** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
969  *  The  denominator of the frequency divider factor of the saradc function clock.
970  */
971 #define PCR_SARADC_CLKM_DIV_A    0x0000003FU
972 #define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
973 #define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
974 #define PCR_SARADC_CLKM_DIV_A_S  0
975 /** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
976  *  The numerator of the frequency divider factor of the saradc function clock.
977  */
978 #define PCR_SARADC_CLKM_DIV_B    0x0000003FU
979 #define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
980 #define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
981 #define PCR_SARADC_CLKM_DIV_B_S  6
982 /** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
983  *  The integral part of the frequency divider factor of the saradc function clock.
984  */
985 #define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
986 #define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
987 #define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
988 #define PCR_SARADC_CLKM_DIV_NUM_S  12
989 /** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
990  *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
991  *  reserved.
992  */
993 #define PCR_SARADC_CLKM_SEL    0x00000003U
994 #define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
995 #define PCR_SARADC_CLKM_SEL_V  0x00000003U
996 #define PCR_SARADC_CLKM_SEL_S  20
997 /** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
998  *  Set 1 to enable saradc function clock
999  */
1000 #define PCR_SARADC_CLKM_EN    (BIT(22))
1001 #define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
1002 #define PCR_SARADC_CLKM_EN_V  0x00000001U
1003 #define PCR_SARADC_CLKM_EN_S  22
1004 
1005 /** PCR_TSENS_CLK_CONF_REG register
1006  *  TSENS_CLK configuration register
1007  */
1008 #define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
1009 /** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
1010  *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
1011  */
1012 #define PCR_TSENS_CLK_SEL    (BIT(20))
1013 #define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
1014 #define PCR_TSENS_CLK_SEL_V  0x00000001U
1015 #define PCR_TSENS_CLK_SEL_S  20
1016 /** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
1017  *  Set 1 to enable tsens clock
1018  */
1019 #define PCR_TSENS_CLK_EN    (BIT(22))
1020 #define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
1021 #define PCR_TSENS_CLK_EN_V  0x00000001U
1022 #define PCR_TSENS_CLK_EN_S  22
1023 /** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
1024  *  Set 0 to reset tsens module
1025  */
1026 #define PCR_TSENS_RST_EN    (BIT(23))
1027 #define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
1028 #define PCR_TSENS_RST_EN_V  0x00000001U
1029 #define PCR_TSENS_RST_EN_S  23
1030 
1031 /** PCR_USB_DEVICE_CONF_REG register
1032  *  USB_DEVICE configuration register
1033  */
1034 #define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
1035 /** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
1036  *  Set 1 to enable usb_device clock
1037  */
1038 #define PCR_USB_DEVICE_CLK_EN    (BIT(0))
1039 #define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
1040 #define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
1041 #define PCR_USB_DEVICE_CLK_EN_S  0
1042 /** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
1043  *  Set 0 to reset usb_device module
1044  */
1045 #define PCR_USB_DEVICE_RST_EN    (BIT(1))
1046 #define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
1047 #define PCR_USB_DEVICE_RST_EN_V  0x00000001U
1048 #define PCR_USB_DEVICE_RST_EN_S  1
1049 /** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1;
1050  *  Query this field after reset usb_device module
1051  */
1052 #define PCR_USB_DEVICE_READY    (BIT(2))
1053 #define PCR_USB_DEVICE_READY_M  (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S)
1054 #define PCR_USB_DEVICE_READY_V  0x00000001U
1055 #define PCR_USB_DEVICE_READY_S  2
1056 
1057 /** PCR_INTMTX_CONF_REG register
1058  *  INTMTX configuration register
1059  */
1060 #define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
1061 /** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
1062  *  Set 1 to enable intmtx clock
1063  */
1064 #define PCR_INTMTX_CLK_EN    (BIT(0))
1065 #define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
1066 #define PCR_INTMTX_CLK_EN_V  0x00000001U
1067 #define PCR_INTMTX_CLK_EN_S  0
1068 /** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
1069  *  Set 0 to reset intmtx module
1070  */
1071 #define PCR_INTMTX_RST_EN    (BIT(1))
1072 #define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
1073 #define PCR_INTMTX_RST_EN_V  0x00000001U
1074 #define PCR_INTMTX_RST_EN_S  1
1075 /** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1;
1076  *  Query this field after reset intmtx module
1077  */
1078 #define PCR_INTMTX_READY    (BIT(2))
1079 #define PCR_INTMTX_READY_M  (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S)
1080 #define PCR_INTMTX_READY_V  0x00000001U
1081 #define PCR_INTMTX_READY_S  2
1082 
1083 /** PCR_PCNT_CONF_REG register
1084  *  PCNT configuration register
1085  */
1086 #define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
1087 /** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
1088  *  Set 1 to enable pcnt clock
1089  */
1090 #define PCR_PCNT_CLK_EN    (BIT(0))
1091 #define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
1092 #define PCR_PCNT_CLK_EN_V  0x00000001U
1093 #define PCR_PCNT_CLK_EN_S  0
1094 /** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
1095  *  Set 0 to reset pcnt module
1096  */
1097 #define PCR_PCNT_RST_EN    (BIT(1))
1098 #define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
1099 #define PCR_PCNT_RST_EN_V  0x00000001U
1100 #define PCR_PCNT_RST_EN_S  1
1101 /** PCR_PCNT_READY : RO; bitpos: [2]; default: 1;
1102  *  Query this field after reset pcnt module
1103  */
1104 #define PCR_PCNT_READY    (BIT(2))
1105 #define PCR_PCNT_READY_M  (PCR_PCNT_READY_V << PCR_PCNT_READY_S)
1106 #define PCR_PCNT_READY_V  0x00000001U
1107 #define PCR_PCNT_READY_S  2
1108 
1109 /** PCR_ETM_CONF_REG register
1110  *  ETM configuration register
1111  */
1112 #define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
1113 /** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
1114  *  Set 1 to enable etm clock
1115  */
1116 #define PCR_ETM_CLK_EN    (BIT(0))
1117 #define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
1118 #define PCR_ETM_CLK_EN_V  0x00000001U
1119 #define PCR_ETM_CLK_EN_S  0
1120 /** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
1121  *  Set 0 to reset etm module
1122  */
1123 #define PCR_ETM_RST_EN    (BIT(1))
1124 #define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
1125 #define PCR_ETM_RST_EN_V  0x00000001U
1126 #define PCR_ETM_RST_EN_S  1
1127 /** PCR_ETM_READY : RO; bitpos: [2]; default: 1;
1128  *  Query this field after reset etm module
1129  */
1130 #define PCR_ETM_READY    (BIT(2))
1131 #define PCR_ETM_READY_M  (PCR_ETM_READY_V << PCR_ETM_READY_S)
1132 #define PCR_ETM_READY_V  0x00000001U
1133 #define PCR_ETM_READY_S  2
1134 
1135 /** PCR_PWM_CONF_REG register
1136  *  PWM configuration register
1137  */
1138 #define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
1139 /** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
1140  *  Set 1 to enable pwm clock
1141  */
1142 #define PCR_PWM_CLK_EN    (BIT(0))
1143 #define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
1144 #define PCR_PWM_CLK_EN_V  0x00000001U
1145 #define PCR_PWM_CLK_EN_S  0
1146 /** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
1147  *  Set 0 to reset pwm module
1148  */
1149 #define PCR_PWM_RST_EN    (BIT(1))
1150 #define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
1151 #define PCR_PWM_RST_EN_V  0x00000001U
1152 #define PCR_PWM_RST_EN_S  1
1153 /** PCR_PWM_READY : RO; bitpos: [2]; default: 1;
1154  *  Query this field after reset pwm module
1155  */
1156 #define PCR_PWM_READY    (BIT(2))
1157 #define PCR_PWM_READY_M  (PCR_PWM_READY_V << PCR_PWM_READY_S)
1158 #define PCR_PWM_READY_V  0x00000001U
1159 #define PCR_PWM_READY_S  2
1160 
1161 /** PCR_PWM_CLK_CONF_REG register
1162  *  PWM_CLK configuration register
1163  */
1164 #define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
1165 /** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
1166  *  The integral part of the frequency divider factor of the pwm function clock.
1167  */
1168 #define PCR_PWM_DIV_NUM    0x000000FFU
1169 #define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
1170 #define PCR_PWM_DIV_NUM_V  0x000000FFU
1171 #define PCR_PWM_DIV_NUM_S  12
1172 /** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
1173  *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
1174  *  160MHz, 2: XTAL, 3: FOSC.
1175  */
1176 #define PCR_PWM_CLKM_SEL    0x00000003U
1177 #define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
1178 #define PCR_PWM_CLKM_SEL_V  0x00000003U
1179 #define PCR_PWM_CLKM_SEL_S  20
1180 /** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
1181  *  set this field as 1 to activate pwm clkm.
1182  */
1183 #define PCR_PWM_CLKM_EN    (BIT(22))
1184 #define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
1185 #define PCR_PWM_CLKM_EN_V  0x00000001U
1186 #define PCR_PWM_CLKM_EN_S  22
1187 
1188 /** PCR_PARL_IO_CONF_REG register
1189  *  PARL_IO configuration register
1190  */
1191 #define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
1192 /** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
1193  *  Set 1 to enable parl apb clock
1194  */
1195 #define PCR_PARL_CLK_EN    (BIT(0))
1196 #define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
1197 #define PCR_PARL_CLK_EN_V  0x00000001U
1198 #define PCR_PARL_CLK_EN_S  0
1199 /** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
1200  *  Set 0 to reset parl apb reg
1201  */
1202 #define PCR_PARL_RST_EN    (BIT(1))
1203 #define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
1204 #define PCR_PARL_RST_EN_V  0x00000001U
1205 #define PCR_PARL_RST_EN_S  1
1206 /** PCR_PARL_READY : RO; bitpos: [2]; default: 1;
1207  *  Query this field after reset parl module
1208  */
1209 #define PCR_PARL_READY    (BIT(2))
1210 #define PCR_PARL_READY_M  (PCR_PARL_READY_V << PCR_PARL_READY_S)
1211 #define PCR_PARL_READY_V  0x00000001U
1212 #define PCR_PARL_READY_S  2
1213 
1214 /** PCR_PARL_CLK_RX_CONF_REG register
1215  *  PARL_CLK_RX configuration register
1216  */
1217 #define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
1218 /** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
1219  *  The integral part of the frequency divider factor of the parl rx clock.
1220  */
1221 #define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
1222 #define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
1223 #define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
1224 #define PCR_PARL_CLK_RX_DIV_NUM_S  0
1225 /** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
1226  *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
1227  *  user clock from pad.
1228  */
1229 #define PCR_PARL_CLK_RX_SEL    0x00000003U
1230 #define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
1231 #define PCR_PARL_CLK_RX_SEL_V  0x00000003U
1232 #define PCR_PARL_CLK_RX_SEL_S  16
1233 /** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
1234  *  Set 1 to enable parl rx clock
1235  */
1236 #define PCR_PARL_CLK_RX_EN    (BIT(18))
1237 #define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
1238 #define PCR_PARL_CLK_RX_EN_V  0x00000001U
1239 #define PCR_PARL_CLK_RX_EN_S  18
1240 /** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
1241  *  Set 0 to reset parl rx module
1242  */
1243 #define PCR_PARL_RX_RST_EN    (BIT(19))
1244 #define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
1245 #define PCR_PARL_RX_RST_EN_V  0x00000001U
1246 #define PCR_PARL_RX_RST_EN_S  19
1247 
1248 /** PCR_PARL_CLK_TX_CONF_REG register
1249  *  PARL_CLK_TX configuration register
1250  */
1251 #define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
1252 /** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
1253  *  The integral part of the frequency divider factor of the parl tx clock.
1254  */
1255 #define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
1256 #define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
1257 #define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
1258 #define PCR_PARL_CLK_TX_DIV_NUM_S  0
1259 /** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
1260  *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
1261  *  user clock from pad.
1262  */
1263 #define PCR_PARL_CLK_TX_SEL    0x00000003U
1264 #define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
1265 #define PCR_PARL_CLK_TX_SEL_V  0x00000003U
1266 #define PCR_PARL_CLK_TX_SEL_S  16
1267 /** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
1268  *  Set 1 to enable parl tx clock
1269  */
1270 #define PCR_PARL_CLK_TX_EN    (BIT(18))
1271 #define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
1272 #define PCR_PARL_CLK_TX_EN_V  0x00000001U
1273 #define PCR_PARL_CLK_TX_EN_S  18
1274 /** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
1275  *  Set 0 to reset parl tx module
1276  */
1277 #define PCR_PARL_TX_RST_EN    (BIT(19))
1278 #define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
1279 #define PCR_PARL_TX_RST_EN_V  0x00000001U
1280 #define PCR_PARL_TX_RST_EN_S  19
1281 
1282 /** PCR_PVT_MONITOR_CONF_REG register
1283  *  PVT_MONITOR configuration register
1284  */
1285 #define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0)
1286 /** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
1287  *  Set 1 to enable apb clock of pvt module
1288  */
1289 #define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
1290 #define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
1291 #define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
1292 #define PCR_PVT_MONITOR_CLK_EN_S  0
1293 /** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
1294  *  Set 0 to reset all pvt monitor module
1295  */
1296 #define PCR_PVT_MONITOR_RST_EN    (BIT(1))
1297 #define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
1298 #define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
1299 #define PCR_PVT_MONITOR_RST_EN_S  1
1300 /** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
1301  *  Set 1 to enable function clock of modem pvt module
1302  */
1303 #define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
1304 #define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
1305 #define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
1306 #define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
1307 /** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
1308  *  Set 1 to enable function clock of cpu pvt module
1309  */
1310 #define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
1311 #define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
1312 #define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
1313 #define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
1314 /** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
1315  *  Set 1 to enable function clock of hp_peri pvt module
1316  */
1317 #define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
1318 #define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
1319 #define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
1320 #define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
1321 
1322 /** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
1323  *  PVT_MONITOR function clock configuration register
1324  */
1325 #define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4)
1326 /** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
1327  *  The integral part of the frequency divider factor of the pvt_monitor function clock.
1328  */
1329 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
1330 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
1331 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
1332 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
1333 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
1334  *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
1335  *  divided by 3.
1336  */
1337 #define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
1338 #define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
1339 #define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
1340 #define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
1341 /** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
1342  *  Set 1 to enable source clock of pvt sitex
1343  */
1344 #define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
1345 #define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
1346 #define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
1347 #define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
1348 
1349 /** PCR_GDMA_CONF_REG register
1350  *  GDMA configuration register
1351  */
1352 #define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8)
1353 /** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
1354  *  Set 1 to enable gdma clock
1355  */
1356 #define PCR_GDMA_CLK_EN    (BIT(0))
1357 #define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
1358 #define PCR_GDMA_CLK_EN_V  0x00000001U
1359 #define PCR_GDMA_CLK_EN_S  0
1360 /** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
1361  *  Set 0 to reset gdma module
1362  */
1363 #define PCR_GDMA_RST_EN    (BIT(1))
1364 #define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
1365 #define PCR_GDMA_RST_EN_V  0x00000001U
1366 #define PCR_GDMA_RST_EN_S  1
1367 
1368 /** PCR_SPI2_CONF_REG register
1369  *  SPI2 configuration register
1370  */
1371 #define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc)
1372 /** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
1373  *  Set 1 to enable spi2 apb clock
1374  */
1375 #define PCR_SPI2_CLK_EN    (BIT(0))
1376 #define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
1377 #define PCR_SPI2_CLK_EN_V  0x00000001U
1378 #define PCR_SPI2_CLK_EN_S  0
1379 /** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
1380  *  Set 0 to reset spi2 module
1381  */
1382 #define PCR_SPI2_RST_EN    (BIT(1))
1383 #define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
1384 #define PCR_SPI2_RST_EN_V  0x00000001U
1385 #define PCR_SPI2_RST_EN_S  1
1386 /** PCR_SPI2_READY : RO; bitpos: [2]; default: 1;
1387  *  Query this field after reset spi2 module
1388  */
1389 #define PCR_SPI2_READY    (BIT(2))
1390 #define PCR_SPI2_READY_M  (PCR_SPI2_READY_V << PCR_SPI2_READY_S)
1391 #define PCR_SPI2_READY_V  0x00000001U
1392 #define PCR_SPI2_READY_S  2
1393 
1394 /** PCR_SPI2_CLKM_CONF_REG register
1395  *  SPI2_CLKM configuration register
1396  */
1397 #define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0)
1398 /** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
1399  *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
1400  *  reserved.
1401  */
1402 #define PCR_SPI2_CLKM_SEL    0x00000003U
1403 #define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
1404 #define PCR_SPI2_CLKM_SEL_V  0x00000003U
1405 #define PCR_SPI2_CLKM_SEL_S  20
1406 /** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
1407  *  Set 1 to enable spi2 function clock
1408  */
1409 #define PCR_SPI2_CLKM_EN    (BIT(22))
1410 #define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
1411 #define PCR_SPI2_CLKM_EN_V  0x00000001U
1412 #define PCR_SPI2_CLKM_EN_S  22
1413 
1414 /** PCR_AES_CONF_REG register
1415  *  AES configuration register
1416  */
1417 #define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4)
1418 /** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
1419  *  Set 1 to enable aes clock
1420  */
1421 #define PCR_AES_CLK_EN    (BIT(0))
1422 #define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
1423 #define PCR_AES_CLK_EN_V  0x00000001U
1424 #define PCR_AES_CLK_EN_S  0
1425 /** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
1426  *  Set 0 to reset aes module
1427  */
1428 #define PCR_AES_RST_EN    (BIT(1))
1429 #define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
1430 #define PCR_AES_RST_EN_V  0x00000001U
1431 #define PCR_AES_RST_EN_S  1
1432 /** PCR_AES_READY : RO; bitpos: [2]; default: 1;
1433  *  Query this field after reset aes module
1434  */
1435 #define PCR_AES_READY    (BIT(2))
1436 #define PCR_AES_READY_M  (PCR_AES_READY_V << PCR_AES_READY_S)
1437 #define PCR_AES_READY_V  0x00000001U
1438 #define PCR_AES_READY_S  2
1439 
1440 /** PCR_SHA_CONF_REG register
1441  *  SHA configuration register
1442  */
1443 #define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8)
1444 /** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
1445  *  Set 1 to enable sha clock
1446  */
1447 #define PCR_SHA_CLK_EN    (BIT(0))
1448 #define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
1449 #define PCR_SHA_CLK_EN_V  0x00000001U
1450 #define PCR_SHA_CLK_EN_S  0
1451 /** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
1452  *  Set 0 to reset sha module
1453  */
1454 #define PCR_SHA_RST_EN    (BIT(1))
1455 #define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
1456 #define PCR_SHA_RST_EN_V  0x00000001U
1457 #define PCR_SHA_RST_EN_S  1
1458 /** PCR_SHA_READY : RO; bitpos: [2]; default: 1;
1459  *  Query this field after reset sha module
1460  */
1461 #define PCR_SHA_READY    (BIT(2))
1462 #define PCR_SHA_READY_M  (PCR_SHA_READY_V << PCR_SHA_READY_S)
1463 #define PCR_SHA_READY_V  0x00000001U
1464 #define PCR_SHA_READY_S  2
1465 
1466 /** PCR_RSA_CONF_REG register
1467  *  RSA configuration register
1468  */
1469 #define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
1470 /** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
1471  *  Set 1 to enable rsa clock
1472  */
1473 #define PCR_RSA_CLK_EN    (BIT(0))
1474 #define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
1475 #define PCR_RSA_CLK_EN_V  0x00000001U
1476 #define PCR_RSA_CLK_EN_S  0
1477 /** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
1478  *  Set 0 to reset rsa module
1479  */
1480 #define PCR_RSA_RST_EN    (BIT(1))
1481 #define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
1482 #define PCR_RSA_RST_EN_V  0x00000001U
1483 #define PCR_RSA_RST_EN_S  1
1484 /** PCR_RSA_READY : RO; bitpos: [2]; default: 1;
1485  *  Query this field after reset rsa module
1486  */
1487 #define PCR_RSA_READY    (BIT(2))
1488 #define PCR_RSA_READY_M  (PCR_RSA_READY_V << PCR_RSA_READY_S)
1489 #define PCR_RSA_READY_V  0x00000001U
1490 #define PCR_RSA_READY_S  2
1491 
1492 /** PCR_RSA_PD_CTRL_REG register
1493  *  RSA power control register
1494  */
1495 #define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0)
1496 /** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
1497  *  Set this bit to power down rsa internal memory.
1498  */
1499 #define PCR_RSA_MEM_PD    (BIT(0))
1500 #define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
1501 #define PCR_RSA_MEM_PD_V  0x00000001U
1502 #define PCR_RSA_MEM_PD_S  0
1503 /** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
1504  *  Set this bit to force power up rsa internal memory
1505  */
1506 #define PCR_RSA_MEM_FORCE_PU    (BIT(1))
1507 #define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
1508 #define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
1509 #define PCR_RSA_MEM_FORCE_PU_S  1
1510 /** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
1511  *  Set this bit to force power down rsa internal memory.
1512  */
1513 #define PCR_RSA_MEM_FORCE_PD    (BIT(2))
1514 #define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
1515 #define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
1516 #define PCR_RSA_MEM_FORCE_PD_S  2
1517 
1518 /** PCR_ECC_CONF_REG register
1519  *  ECC configuration register
1520  */
1521 #define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4)
1522 /** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
1523  *  Set 1 to enable ecc clock
1524  */
1525 #define PCR_ECC_CLK_EN    (BIT(0))
1526 #define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
1527 #define PCR_ECC_CLK_EN_V  0x00000001U
1528 #define PCR_ECC_CLK_EN_S  0
1529 /** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
1530  *  Set 0 to reset ecc module
1531  */
1532 #define PCR_ECC_RST_EN    (BIT(1))
1533 #define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
1534 #define PCR_ECC_RST_EN_V  0x00000001U
1535 #define PCR_ECC_RST_EN_S  1
1536 /** PCR_ECC_READY : RO; bitpos: [2]; default: 1;
1537  *  Query this field after reset ecc module
1538  */
1539 #define PCR_ECC_READY    (BIT(2))
1540 #define PCR_ECC_READY_M  (PCR_ECC_READY_V << PCR_ECC_READY_S)
1541 #define PCR_ECC_READY_V  0x00000001U
1542 #define PCR_ECC_READY_S  2
1543 
1544 /** PCR_ECC_PD_CTRL_REG register
1545  *  ECC power control register
1546  */
1547 #define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8)
1548 /** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
1549  *  Set this bit to power down ecc internal memory.
1550  */
1551 #define PCR_ECC_MEM_PD    (BIT(0))
1552 #define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
1553 #define PCR_ECC_MEM_PD_V  0x00000001U
1554 #define PCR_ECC_MEM_PD_S  0
1555 /** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
1556  *  Set this bit to force power up ecc internal memory
1557  */
1558 #define PCR_ECC_MEM_FORCE_PU    (BIT(1))
1559 #define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
1560 #define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
1561 #define PCR_ECC_MEM_FORCE_PU_S  1
1562 /** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
1563  *  Set this bit to force power down ecc internal memory.
1564  */
1565 #define PCR_ECC_MEM_FORCE_PD    (BIT(2))
1566 #define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
1567 #define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
1568 #define PCR_ECC_MEM_FORCE_PD_S  2
1569 
1570 /** PCR_DS_CONF_REG register
1571  *  DS configuration register
1572  */
1573 #define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc)
1574 /** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
1575  *  Set 1 to enable ds clock
1576  */
1577 #define PCR_DS_CLK_EN    (BIT(0))
1578 #define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
1579 #define PCR_DS_CLK_EN_V  0x00000001U
1580 #define PCR_DS_CLK_EN_S  0
1581 /** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
1582  *  Set 0 to reset ds module
1583  */
1584 #define PCR_DS_RST_EN    (BIT(1))
1585 #define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
1586 #define PCR_DS_RST_EN_V  0x00000001U
1587 #define PCR_DS_RST_EN_S  1
1588 /** PCR_DS_READY : RO; bitpos: [2]; default: 1;
1589  *  Query this field after reset ds module
1590  */
1591 #define PCR_DS_READY    (BIT(2))
1592 #define PCR_DS_READY_M  (PCR_DS_READY_V << PCR_DS_READY_S)
1593 #define PCR_DS_READY_V  0x00000001U
1594 #define PCR_DS_READY_S  2
1595 
1596 /** PCR_HMAC_CONF_REG register
1597  *  HMAC configuration register
1598  */
1599 #define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0)
1600 /** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
1601  *  Set 1 to enable hmac clock
1602  */
1603 #define PCR_HMAC_CLK_EN    (BIT(0))
1604 #define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
1605 #define PCR_HMAC_CLK_EN_V  0x00000001U
1606 #define PCR_HMAC_CLK_EN_S  0
1607 /** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
1608  *  Set 0 to reset hmac module
1609  */
1610 #define PCR_HMAC_RST_EN    (BIT(1))
1611 #define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
1612 #define PCR_HMAC_RST_EN_V  0x00000001U
1613 #define PCR_HMAC_RST_EN_S  1
1614 /** PCR_HMAC_READY : RO; bitpos: [2]; default: 1;
1615  *  Query this field after reset hmac module
1616  */
1617 #define PCR_HMAC_READY    (BIT(2))
1618 #define PCR_HMAC_READY_M  (PCR_HMAC_READY_V << PCR_HMAC_READY_S)
1619 #define PCR_HMAC_READY_V  0x00000001U
1620 #define PCR_HMAC_READY_S  2
1621 
1622 /** PCR_ECDSA_CONF_REG register
1623  *  ECDSA configuration register
1624  */
1625 #define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4)
1626 /** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1;
1627  *  Set 1 to enable ecdsa clock
1628  */
1629 #define PCR_ECDSA_CLK_EN    (BIT(0))
1630 #define PCR_ECDSA_CLK_EN_M  (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S)
1631 #define PCR_ECDSA_CLK_EN_V  0x00000001U
1632 #define PCR_ECDSA_CLK_EN_S  0
1633 /** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0;
1634  *  Set 0 to reset ecdsa module
1635  */
1636 #define PCR_ECDSA_RST_EN    (BIT(1))
1637 #define PCR_ECDSA_RST_EN_M  (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S)
1638 #define PCR_ECDSA_RST_EN_V  0x00000001U
1639 #define PCR_ECDSA_RST_EN_S  1
1640 /** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1;
1641  *  Query this field after reset ecdsa module
1642  */
1643 #define PCR_ECDSA_READY    (BIT(2))
1644 #define PCR_ECDSA_READY_M  (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S)
1645 #define PCR_ECDSA_READY_V  0x00000001U
1646 #define PCR_ECDSA_READY_S  2
1647 
1648 /** PCR_IOMUX_CONF_REG register
1649  *  IOMUX configuration register
1650  */
1651 #define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
1652 /** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
1653  *  Set 1 to enable iomux apb clock
1654  */
1655 #define PCR_IOMUX_CLK_EN    (BIT(0))
1656 #define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
1657 #define PCR_IOMUX_CLK_EN_V  0x00000001U
1658 #define PCR_IOMUX_CLK_EN_S  0
1659 /** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
1660  *  Set 0 to reset iomux module
1661  */
1662 #define PCR_IOMUX_RST_EN    (BIT(1))
1663 #define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
1664 #define PCR_IOMUX_RST_EN_V  0x00000001U
1665 #define PCR_IOMUX_RST_EN_S  1
1666 
1667 /** PCR_IOMUX_CLK_CONF_REG register
1668  *  IOMUX_CLK configuration register
1669  */
1670 #define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
1671 /** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
1672  *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
1673  *  FOSC, 3(default): XTAL.
1674  */
1675 #define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
1676 #define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
1677 #define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
1678 #define PCR_IOMUX_FUNC_CLK_SEL_S  20
1679 /** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
1680  *  Set 1 to enable iomux function clock
1681  */
1682 #define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
1683 #define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
1684 #define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
1685 #define PCR_IOMUX_FUNC_CLK_EN_S  22
1686 
1687 /** PCR_MEM_MONITOR_CONF_REG register
1688  *  MEM_MONITOR configuration register
1689  */
1690 #define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
1691 /** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
1692  *  Set 1 to enable mem_monitor clock
1693  */
1694 #define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
1695 #define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
1696 #define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
1697 #define PCR_MEM_MONITOR_CLK_EN_S  0
1698 /** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
1699  *  Set 0 to reset mem_monitor module
1700  */
1701 #define PCR_MEM_MONITOR_RST_EN    (BIT(1))
1702 #define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
1703 #define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
1704 #define PCR_MEM_MONITOR_RST_EN_S  1
1705 /** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1;
1706  *  Query this field after reset mem_monitor module
1707  */
1708 #define PCR_MEM_MONITOR_READY    (BIT(2))
1709 #define PCR_MEM_MONITOR_READY_M  (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S)
1710 #define PCR_MEM_MONITOR_READY_V  0x00000001U
1711 #define PCR_MEM_MONITOR_READY_S  2
1712 
1713 /** PCR_REGDMA_CONF_REG register
1714  *  REGDMA configuration register
1715  */
1716 #define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
1717 /** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
1718  *  Set 1 to enable regdma clock
1719  */
1720 #define PCR_REGDMA_CLK_EN    (BIT(0))
1721 #define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
1722 #define PCR_REGDMA_CLK_EN_V  0x00000001U
1723 #define PCR_REGDMA_CLK_EN_S  0
1724 /** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
1725  *  Set 0 to reset regdma module
1726  */
1727 #define PCR_REGDMA_RST_EN    (BIT(1))
1728 #define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
1729 #define PCR_REGDMA_RST_EN_V  0x00000001U
1730 #define PCR_REGDMA_RST_EN_S  1
1731 
1732 /** PCR_TRACE_CONF_REG register
1733  *  TRACE configuration register
1734  */
1735 #define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8)
1736 /** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
1737  *  Set 1 to enable trace clock
1738  */
1739 #define PCR_TRACE_CLK_EN    (BIT(0))
1740 #define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
1741 #define PCR_TRACE_CLK_EN_V  0x00000001U
1742 #define PCR_TRACE_CLK_EN_S  0
1743 /** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
1744  *  Set 0 to reset trace module
1745  */
1746 #define PCR_TRACE_RST_EN    (BIT(1))
1747 #define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
1748 #define PCR_TRACE_RST_EN_V  0x00000001U
1749 #define PCR_TRACE_RST_EN_S  1
1750 
1751 /** PCR_ASSIST_CONF_REG register
1752  *  ASSIST configuration register
1753  */
1754 #define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc)
1755 /** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
1756  *  Set 1 to enable assist clock
1757  */
1758 #define PCR_ASSIST_CLK_EN    (BIT(0))
1759 #define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
1760 #define PCR_ASSIST_CLK_EN_V  0x00000001U
1761 #define PCR_ASSIST_CLK_EN_S  0
1762 /** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
1763  *  Set 0 to reset assist module
1764  */
1765 #define PCR_ASSIST_RST_EN    (BIT(1))
1766 #define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
1767 #define PCR_ASSIST_RST_EN_V  0x00000001U
1768 #define PCR_ASSIST_RST_EN_S  1
1769 
1770 /** PCR_CACHE_CONF_REG register
1771  *  CACHE configuration register
1772  */
1773 #define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100)
1774 /** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
1775  *  Set 1 to enable cache clock
1776  */
1777 #define PCR_CACHE_CLK_EN    (BIT(0))
1778 #define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
1779 #define PCR_CACHE_CLK_EN_V  0x00000001U
1780 #define PCR_CACHE_CLK_EN_S  0
1781 /** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
1782  *  Set 0 to reset cache module
1783  */
1784 #define PCR_CACHE_RST_EN    (BIT(1))
1785 #define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
1786 #define PCR_CACHE_RST_EN_V  0x00000001U
1787 #define PCR_CACHE_RST_EN_S  1
1788 
1789 /** PCR_MODEM_CONF_REG register
1790  *  MODEM_APB configuration register
1791  */
1792 #define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104)
1793 /** PCR_MODEM_CLK_SEL : R/W; bitpos: [0]; default: 0;
1794  *  xxxx
1795  */
1796 #define PCR_MODEM_CLK_SEL    (BIT(0))
1797 #define PCR_MODEM_CLK_SEL_M  (PCR_MODEM_CLK_SEL_V << PCR_MODEM_CLK_SEL_S)
1798 #define PCR_MODEM_CLK_SEL_V  0x00000001U
1799 #define PCR_MODEM_CLK_SEL_S  0
1800 /** PCR_MODEM_CLK_EN : R/W; bitpos: [1]; default: 1;
1801  *  xxxx
1802  */
1803 #define PCR_MODEM_CLK_EN    (BIT(1))
1804 #define PCR_MODEM_CLK_EN_M  (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S)
1805 #define PCR_MODEM_CLK_EN_V  0x00000001U
1806 #define PCR_MODEM_CLK_EN_S  1
1807 /** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0;
1808  *  Set this file as 1 to reset modem-subsystem.
1809  */
1810 #define PCR_MODEM_RST_EN    (BIT(2))
1811 #define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
1812 #define PCR_MODEM_RST_EN_V  0x00000001U
1813 #define PCR_MODEM_RST_EN_S  2
1814 
1815 /** PCR_TIMEOUT_CONF_REG register
1816  *  TIMEOUT configuration register
1817  */
1818 #define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108)
1819 /** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
1820  *  Set 0 to reset cpu_peri timeout module
1821  */
1822 #define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
1823 #define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
1824 #define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
1825 #define PCR_CPU_TIMEOUT_RST_EN_S  1
1826 /** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
1827  *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
1828  */
1829 #define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
1830 #define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
1831 #define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
1832 #define PCR_HP_TIMEOUT_RST_EN_S  2
1833 
1834 /** PCR_SYSCLK_CONF_REG register
1835  *  SYSCLK configuration register
1836  */
1837 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c)
1838 /** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
1839  *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
1840  *  clock-source such as XTAL/FOSC.
1841  */
1842 #define PCR_LS_DIV_NUM    0x000000FFU
1843 #define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
1844 #define PCR_LS_DIV_NUM_V  0x000000FFU
1845 #define PCR_LS_DIV_NUM_S  0
1846 /** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
1847  *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
1848  */
1849 #define PCR_HS_DIV_NUM    0x000000FFU
1850 #define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
1851 #define PCR_HS_DIV_NUM_V  0x000000FFU
1852 #define PCR_HS_DIV_NUM_S  8
1853 /** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
1854  *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
1855  */
1856 #define PCR_SOC_CLK_SEL    0x00000003U
1857 #define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
1858 #define PCR_SOC_CLK_SEL_V  0x00000003U
1859 #define PCR_SOC_CLK_SEL_S  16
1860 /** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 32;
1861  *  This field indicates the frequency(MHz) of XTAL.
1862  */
1863 #define PCR_CLK_XTAL_FREQ    0x0000007FU
1864 #define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
1865 #define PCR_CLK_XTAL_FREQ_V  0x0000007FU
1866 #define PCR_CLK_XTAL_FREQ_S  24
1867 
1868 /** PCR_CPU_WAITI_CONF_REG register
1869  *  CPU_WAITI configuration register
1870  */
1871 #define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110)
1872 /** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
1873  *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
1874  */
1875 #define PCR_CPUPERIOD_SEL    0x00000003U
1876 #define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
1877 #define PCR_CPUPERIOD_SEL_V  0x00000003U
1878 #define PCR_CPUPERIOD_SEL_S  0
1879 /** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
1880  *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
1881  */
1882 #define PCR_PLL_FREQ_SEL    (BIT(2))
1883 #define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
1884 #define PCR_PLL_FREQ_SEL_V  0x00000001U
1885 #define PCR_PLL_FREQ_SEL_S  2
1886 /** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
1887  *  Set 1 to force cpu_waiti_clk enable.
1888  */
1889 #define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
1890 #define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
1891 #define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
1892 #define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
1893 /** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
1894  *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
1895  *  will close
1896  */
1897 #define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
1898 #define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
1899 #define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
1900 #define PCR_CPU_WAITI_DELAY_NUM_S  4
1901 
1902 /** PCR_CPU_FREQ_CONF_REG register
1903  *  CPU_FREQ configuration register
1904  */
1905 #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114)
1906 /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
1907  *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
1908  *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
1909  *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
1910  */
1911 #define PCR_CPU_DIV_NUM    0x000000FFU
1912 #define PCR_CPU_DIV_NUM_M  (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S)
1913 #define PCR_CPU_DIV_NUM_V  0x000000FFU
1914 #define PCR_CPU_DIV_NUM_S  0
1915 
1916 /** PCR_AHB_FREQ_CONF_REG register
1917  *  AHB_FREQ configuration register
1918  */
1919 #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
1920 /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
1921  *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
1922  *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
1923  *  low-speed clock-source such as XTAL/FOSC, and should be used together with
1924  *  PCR_CPU_DIV_NUM.
1925  */
1926 #define PCR_AHB_DIV_NUM    0x000000FFU
1927 #define PCR_AHB_DIV_NUM_M  (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S)
1928 #define PCR_AHB_DIV_NUM_V  0x000000FFU
1929 #define PCR_AHB_DIV_NUM_S  0
1930 
1931 /** PCR_APB_FREQ_CONF_REG register
1932  *  APB_FREQ configuration register
1933  */
1934 #define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
1935 /** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
1936  *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
1937  *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
1938  *  recover to the previous frequency when a new access appears on apb-bus. Set as one
1939  *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
1940  *  that enable this function will reduce performance. Users can set this field as zero
1941  *  to disable the auto-decrease-apb-freq function. By default, this function is
1942  *  disable.
1943  */
1944 #define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
1945 #define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
1946 #define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
1947 #define PCR_APB_DECREASE_DIV_NUM_S  0
1948 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
1949  *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
1950  *  div1(default)/div2/div4 of clk_ahb.
1951  */
1952 #define PCR_APB_DIV_NUM    0x000000FFU
1953 #define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
1954 #define PCR_APB_DIV_NUM_V  0x000000FFU
1955 #define PCR_APB_DIV_NUM_S  8
1956 
1957 /** PCR_SYSCLK_FREQ_QUERY_0_REG register
1958  *  SYSCLK frequency query 0 register
1959  */
1960 #define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120)
1961 /** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8;
1962  *  This field indicates the frequency(MHz) of FOSC.
1963  */
1964 #define PCR_FOSC_FREQ    0x000000FFU
1965 #define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
1966 #define PCR_FOSC_FREQ_V  0x000000FFU
1967 #define PCR_FOSC_FREQ_S  0
1968 /** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96;
1969  *  This field indicates the frequency(MHz) of SPLL.
1970  */
1971 #define PCR_PLL_FREQ    0x000003FFU
1972 #define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
1973 #define PCR_PLL_FREQ_V  0x000003FFU
1974 #define PCR_PLL_FREQ_S  8
1975 
1976 /** PCR_PLL_DIV_CLK_EN_REG register
1977  *  SPLL DIV clock-gating configuration register
1978  */
1979 #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124)
1980 /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
1981  *  This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1:
1982  *  open(default). Only avaliable when high-speed clock-source SPLL is active.
1983  */
1984 #define PCR_PLL_240M_CLK_EN    (BIT(0))
1985 #define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
1986 #define PCR_PLL_240M_CLK_EN_V  0x00000001U
1987 #define PCR_PLL_240M_CLK_EN_S  0
1988 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
1989  *  This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
1990  *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
1991  */
1992 #define PCR_PLL_160M_CLK_EN    (BIT(1))
1993 #define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
1994 #define PCR_PLL_160M_CLK_EN_V  0x00000001U
1995 #define PCR_PLL_160M_CLK_EN_S  1
1996 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
1997  *  This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
1998  *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
1999  */
2000 #define PCR_PLL_120M_CLK_EN    (BIT(2))
2001 #define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
2002 #define PCR_PLL_120M_CLK_EN_V  0x00000001U
2003 #define PCR_PLL_120M_CLK_EN_S  2
2004 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
2005  *  This field is used to open 32 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
2006  *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
2007  */
2008 #define PCR_PLL_80M_CLK_EN    (BIT(3))
2009 #define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
2010 #define PCR_PLL_80M_CLK_EN_V  0x00000001U
2011 #define PCR_PLL_80M_CLK_EN_S  3
2012 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
2013  *  This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
2014  *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
2015  */
2016 #define PCR_PLL_48M_CLK_EN    (BIT(4))
2017 #define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
2018 #define PCR_PLL_48M_CLK_EN_V  0x00000001U
2019 #define PCR_PLL_48M_CLK_EN_S  4
2020 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
2021  *  This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
2022  *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
2023  */
2024 #define PCR_PLL_40M_CLK_EN    (BIT(5))
2025 #define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
2026 #define PCR_PLL_40M_CLK_EN_V  0x00000001U
2027 #define PCR_PLL_40M_CLK_EN_S  5
2028 
2029 /** PCR_CTRL_CLK_OUT_EN_REG register
2030  *  CLK_OUT_EN configuration register
2031  */
2032 #define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128)
2033 /** PCR_CLK8_OEN : R/W; bitpos: [0]; default: 1;
2034  *  Set 1 to enable 8m clock
2035  */
2036 #define PCR_CLK8_OEN    (BIT(0))
2037 #define PCR_CLK8_OEN_M  (PCR_CLK8_OEN_V << PCR_CLK8_OEN_S)
2038 #define PCR_CLK8_OEN_V  0x00000001U
2039 #define PCR_CLK8_OEN_S  0
2040 /** PCR_CLK16_OEN : R/W; bitpos: [1]; default: 1;
2041  *  Set 1 to enable 16m clock
2042  */
2043 #define PCR_CLK16_OEN    (BIT(1))
2044 #define PCR_CLK16_OEN_M  (PCR_CLK16_OEN_V << PCR_CLK16_OEN_S)
2045 #define PCR_CLK16_OEN_V  0x00000001U
2046 #define PCR_CLK16_OEN_S  1
2047 /** PCR_CLK32_OEN : R/W; bitpos: [2]; default: 1;
2048  *  Set 1 to enable 32m clock
2049  */
2050 #define PCR_CLK32_OEN    (BIT(2))
2051 #define PCR_CLK32_OEN_M  (PCR_CLK32_OEN_V << PCR_CLK32_OEN_S)
2052 #define PCR_CLK32_OEN_V  0x00000001U
2053 #define PCR_CLK32_OEN_S  2
2054 /** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [3]; default: 1;
2055  *  Reserved
2056  */
2057 #define PCR_CLK_ADC_INF_OEN    (BIT(3))
2058 #define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
2059 #define PCR_CLK_ADC_INF_OEN_V  0x00000001U
2060 #define PCR_CLK_ADC_INF_OEN_S  3
2061 /** PCR_CLK_DFM_INF_OEN : R/W; bitpos: [4]; default: 1;
2062  *  Reserved
2063  */
2064 #define PCR_CLK_DFM_INF_OEN    (BIT(4))
2065 #define PCR_CLK_DFM_INF_OEN_M  (PCR_CLK_DFM_INF_OEN_V << PCR_CLK_DFM_INF_OEN_S)
2066 #define PCR_CLK_DFM_INF_OEN_V  0x00000001U
2067 #define PCR_CLK_DFM_INF_OEN_S  4
2068 /** PCR_CLK_SDM_MOD_OEN : R/W; bitpos: [5]; default: 1;
2069  *  Reserved
2070  */
2071 #define PCR_CLK_SDM_MOD_OEN    (BIT(5))
2072 #define PCR_CLK_SDM_MOD_OEN_M  (PCR_CLK_SDM_MOD_OEN_V << PCR_CLK_SDM_MOD_OEN_S)
2073 #define PCR_CLK_SDM_MOD_OEN_V  0x00000001U
2074 #define PCR_CLK_SDM_MOD_OEN_S  5
2075 /** PCR_CLK_XTAL_OEN : R/W; bitpos: [6]; default: 1;
2076  *  Set 1 to enable xtal clock
2077  */
2078 #define PCR_CLK_XTAL_OEN    (BIT(6))
2079 #define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
2080 #define PCR_CLK_XTAL_OEN_V  0x00000001U
2081 #define PCR_CLK_XTAL_OEN_S  6
2082 
2083 /** PCR_CTRL_TICK_CONF_REG register
2084  *  TICK configuration register
2085  */
2086 #define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c)
2087 /** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
2088  *  ******* Description ***********
2089  */
2090 #define PCR_XTAL_TICK_NUM    0x000000FFU
2091 #define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
2092 #define PCR_XTAL_TICK_NUM_V  0x000000FFU
2093 #define PCR_XTAL_TICK_NUM_S  0
2094 /** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
2095  *  ******* Description ***********
2096  */
2097 #define PCR_FOSC_TICK_NUM    0x000000FFU
2098 #define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
2099 #define PCR_FOSC_TICK_NUM_V  0x000000FFU
2100 #define PCR_FOSC_TICK_NUM_S  8
2101 /** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
2102  *  ******* Description ***********
2103  */
2104 #define PCR_TICK_ENABLE    (BIT(16))
2105 #define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
2106 #define PCR_TICK_ENABLE_V  0x00000001U
2107 #define PCR_TICK_ENABLE_S  16
2108 /** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
2109  *  ******* Description ***********
2110  */
2111 #define PCR_RST_TICK_CNT    (BIT(17))
2112 #define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
2113 #define PCR_RST_TICK_CNT_V  0x00000001U
2114 #define PCR_RST_TICK_CNT_S  17
2115 
2116 /** PCR_CTRL_32K_CONF_REG register
2117  *  32KHz clock configuration register
2118  */
2119 #define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130)
2120 /** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
2121  *  This field indicates which one 32KHz clock will be used by timergroup. 0:
2122  *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
2123  */
2124 #define PCR_32K_SEL    0x00000003U
2125 #define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
2126 #define PCR_32K_SEL_V  0x00000003U
2127 #define PCR_32K_SEL_S  0
2128 /** PCR_32K_MODEM_SEL : R/W; bitpos: [3:2]; default: 0;
2129  *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0:
2130  *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
2131  */
2132 #define PCR_32K_MODEM_SEL    0x00000003U
2133 #define PCR_32K_MODEM_SEL_M  (PCR_32K_MODEM_SEL_V << PCR_32K_MODEM_SEL_S)
2134 #define PCR_32K_MODEM_SEL_V  0x00000003U
2135 #define PCR_32K_MODEM_SEL_S  2
2136 
2137 /** PCR_SRAM_POWER_CONF_0_REG register
2138  *  HP SRAM/ROM configuration register
2139  */
2140 #define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134)
2141 /** PCR_ROM_FORCE_PU : R/W; bitpos: [14:13]; default: 3;
2142  *  Set this bit to force power up ROM
2143  */
2144 #define PCR_ROM_FORCE_PU    0x00000003U
2145 #define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
2146 #define PCR_ROM_FORCE_PU_V  0x00000003U
2147 #define PCR_ROM_FORCE_PU_S  13
2148 /** PCR_ROM_FORCE_PD : R/W; bitpos: [16:15]; default: 0;
2149  *  Set this bit to force power down ROM.
2150  */
2151 #define PCR_ROM_FORCE_PD    0x00000003U
2152 #define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
2153 #define PCR_ROM_FORCE_PD_V  0x00000003U
2154 #define PCR_ROM_FORCE_PD_S  15
2155 /** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [18:17]; default: 0;
2156  *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
2157  *  gate-clock will be used when accessing the ROM.
2158  */
2159 #define PCR_ROM_CLKGATE_FORCE_ON    0x00000003U
2160 #define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
2161 #define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000003U
2162 #define PCR_ROM_CLKGATE_FORCE_ON_S  17
2163 
2164 /** PCR_SRAM_POWER_CONF_1_REG register
2165  *  HP SRAM/ROM configuration register
2166  */
2167 #define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138)
2168 /** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31;
2169  *  Set this bit to force power up SRAM
2170  */
2171 #define PCR_SRAM_FORCE_PU    0x0000001FU
2172 #define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
2173 #define PCR_SRAM_FORCE_PU_V  0x0000001FU
2174 #define PCR_SRAM_FORCE_PU_S  0
2175 /** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0;
2176  *  Set this bit to force power down SRAM.
2177  */
2178 #define PCR_SRAM_FORCE_PD    0x0000001FU
2179 #define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
2180 #define PCR_SRAM_FORCE_PD_V  0x0000001FU
2181 #define PCR_SRAM_FORCE_PD_S  10
2182 /** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [29:25]; default: 0;
2183  *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
2184  *  gate-clock will be used when accessing the SRAM.
2185  */
2186 #define PCR_SRAM_CLKGATE_FORCE_ON    0x0000001FU
2187 #define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
2188 #define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000001FU
2189 #define PCR_SRAM_CLKGATE_FORCE_ON_S  25
2190 
2191 /** PCR_SEC_CONF_REG register
2192  *  xxxx
2193  */
2194 #define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c)
2195 /** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
2196  *  xxxx
2197  */
2198 #define PCR_SEC_CLK_SEL    0x00000003U
2199 #define PCR_SEC_CLK_SEL_M  (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S)
2200 #define PCR_SEC_CLK_SEL_V  0x00000003U
2201 #define PCR_SEC_CLK_SEL_S  0
2202 
2203 /** PCR_ADC_INV_PHASE_CONF_REG register
2204  *  xxxx
2205  */
2206 #define PCR_ADC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140)
2207 /** PCR_CLK_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
2208  *  xxxx
2209  */
2210 #define PCR_CLK_ADC_INV_PHASE_ENA    (BIT(0))
2211 #define PCR_CLK_ADC_INV_PHASE_ENA_M  (PCR_CLK_ADC_INV_PHASE_ENA_V << PCR_CLK_ADC_INV_PHASE_ENA_S)
2212 #define PCR_CLK_ADC_INV_PHASE_ENA_V  0x00000001U
2213 #define PCR_CLK_ADC_INV_PHASE_ENA_S  0
2214 
2215 /** PCR_SDM_INV_PHASE_CONF_REG register
2216  *  xxxx
2217  */
2218 #define PCR_SDM_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x144)
2219 /** PCR_CLK_SDM_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
2220  *  xxxx
2221  */
2222 #define PCR_CLK_SDM_INV_PHASE_ENA    (BIT(0))
2223 #define PCR_CLK_SDM_INV_PHASE_ENA_M  (PCR_CLK_SDM_INV_PHASE_ENA_V << PCR_CLK_SDM_INV_PHASE_ENA_S)
2224 #define PCR_CLK_SDM_INV_PHASE_ENA_V  0x00000001U
2225 #define PCR_CLK_SDM_INV_PHASE_ENA_S  0
2226 /** PCR_CLK_SDM_INV_PHASE_SEL : R/W; bitpos: [3:1]; default: 0;
2227  *  xxxx
2228  */
2229 #define PCR_CLK_SDM_INV_PHASE_SEL    0x00000007U
2230 #define PCR_CLK_SDM_INV_PHASE_SEL_M  (PCR_CLK_SDM_INV_PHASE_SEL_V << PCR_CLK_SDM_INV_PHASE_SEL_S)
2231 #define PCR_CLK_SDM_INV_PHASE_SEL_V  0x00000007U
2232 #define PCR_CLK_SDM_INV_PHASE_SEL_S  1
2233 
2234 /** PCR_BUS_CLK_UPDATE_REG register
2235  *  xxxx
2236  */
2237 #define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148)
2238 /** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0;
2239  *  xxxx
2240  */
2241 #define PCR_BUS_CLOCK_UPDATE    (BIT(0))
2242 #define PCR_BUS_CLOCK_UPDATE_M  (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S)
2243 #define PCR_BUS_CLOCK_UPDATE_V  0x00000001U
2244 #define PCR_BUS_CLOCK_UPDATE_S  0
2245 
2246 /** PCR_SAR_CLK_DIV_REG register
2247  *  xxxx
2248  */
2249 #define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c)
2250 /** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
2251  *  xxxx
2252  */
2253 #define PCR_SAR2_CLK_DIV_NUM    0x000000FFU
2254 #define PCR_SAR2_CLK_DIV_NUM_M  (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S)
2255 #define PCR_SAR2_CLK_DIV_NUM_V  0x000000FFU
2256 #define PCR_SAR2_CLK_DIV_NUM_S  0
2257 /** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
2258  *  xxxx
2259  */
2260 #define PCR_SAR1_CLK_DIV_NUM    0x000000FFU
2261 #define PCR_SAR1_CLK_DIV_NUM_M  (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S)
2262 #define PCR_SAR1_CLK_DIV_NUM_V  0x000000FFU
2263 #define PCR_SAR1_CLK_DIV_NUM_S  8
2264 
2265 /** PCR_PWDET_SAR_CLK_CONF_REG register
2266  *  xxxx
2267  */
2268 #define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150)
2269 /** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7;
2270  *  xxxx
2271  */
2272 #define PCR_PWDET_SAR_CLK_DIV_NUM    0x000000FFU
2273 #define PCR_PWDET_SAR_CLK_DIV_NUM_M  (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S)
2274 #define PCR_PWDET_SAR_CLK_DIV_NUM_V  0x000000FFU
2275 #define PCR_PWDET_SAR_CLK_DIV_NUM_S  0
2276 /** PCR_PWDET_SAR_READER_EN : R/W; bitpos: [8]; default: 1;
2277  *  xxxx
2278  */
2279 #define PCR_PWDET_SAR_READER_EN    (BIT(8))
2280 #define PCR_PWDET_SAR_READER_EN_M  (PCR_PWDET_SAR_READER_EN_V << PCR_PWDET_SAR_READER_EN_S)
2281 #define PCR_PWDET_SAR_READER_EN_V  0x00000001U
2282 #define PCR_PWDET_SAR_READER_EN_S  8
2283 
2284 /** PCR_RESET_EVENT_BYPASS_REG register
2285  *  reset event bypass backdoor configuration register
2286  */
2287 #define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
2288 /** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
2289  *  This field is used to control reset event relationship for
2290  *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
2291  *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
2292  *  will not only be reset by power-reset, but also some reset event.
2293  */
2294 #define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
2295 #define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
2296 #define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
2297 #define PCR_RESET_EVENT_BYPASS_APM_S  0
2298 /** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
2299  *  This field is used to control reset event relationship for system-bus. 1: system
2300  *  bus (including arbiter/router) will only be reset by power-reset. some reset event
2301  *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
2302  *  power-reset, but also some reset event.
2303  */
2304 #define PCR_RESET_EVENT_BYPASS    (BIT(1))
2305 #define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
2306 #define PCR_RESET_EVENT_BYPASS_V  0x00000001U
2307 #define PCR_RESET_EVENT_BYPASS_S  1
2308 
2309 /** PCR_FPGA_DEBUG_REG register
2310  *  fpga debug register
2311  */
2312 #define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
2313 /** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
2314  *  Only used in fpga debug.
2315  */
2316 #define PCR_FPGA_DEBUG    0xFFFFFFFFU
2317 #define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
2318 #define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
2319 #define PCR_FPGA_DEBUG_S  0
2320 
2321 /** PCR_CLOCK_GATE_REG register
2322  *  PCR clock gating configure register
2323  */
2324 #define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
2325 /** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
2326  *  Set this bit as 1 to force on clock gating.
2327  */
2328 #define PCR_CLK_EN    (BIT(0))
2329 #define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
2330 #define PCR_CLK_EN_V  0x00000001U
2331 #define PCR_CLK_EN_S  0
2332 
2333 /** PCR_DATE_REG register
2334  *  Date register.
2335  */
2336 #define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
2337 /** PCR_DATE : R/W; bitpos: [27:0]; default: 35717248;
2338  *  PCR version information.
2339  */
2340 #define PCR_DATE    0x0FFFFFFFU
2341 #define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
2342 #define PCR_DATE_V  0x0FFFFFFFU
2343 #define PCR_DATE_S  0
2344 
2345 #ifdef __cplusplus
2346 }
2347 #endif
2348