Searched refs:MMU_VALID_VAL_MASK (Results 1 – 17 of 17) sorted by relevance
239 ret = mmu_raw_value & MMU_VALID_VAL_MASK; in mmu_ll_read_entry()333 return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) << shift_code; in mmu_ll_entry_id_to_paddr_base()354 if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
23 #define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
87 #define MMU_VALID_VAL_MASK 0x3f macro
77 #define MMU_VALID_VAL_MASK 0xff macro
77 #define MMU_VALID_VAL_MASK 0x3fff macro
106 #define MMU_VALID_VAL_MASK 0x3fff macro
271 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16; in mmu_ll_entry_id_to_paddr_base()291 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
270 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16; in mmu_ll_entry_id_to_paddr_base()290 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
317 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << shift_code; in mmu_ll_entry_id_to_paddr_base()337 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
291 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16; in mmu_ll_entry_id_to_paddr_base()311 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
171 instr_start_page &= MMU_VALID_VAL_MASK; in instruction_flash_page_info_init()224 rodata_start_page &= MMU_VALID_VAL_MASK; in rodata_flash_page_info_init()
359 return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) << shift_code; in mmu_ll_entry_id_to_paddr_base()380 if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
80 #define MMU_VALID_VAL_MASK 0x1ff macro