Searched refs:MMU_MAX_PADDR_PAGE_NUM (Results 1 – 14 of 14) sorted by relevance
124 return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()125 (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()126 ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)); in mmu_ll_check_valid_paddr_region()
123 return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()124 (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()125 ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)); in mmu_ll_check_valid_paddr_region()
122 return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()123 (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()124 ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)); in mmu_ll_check_valid_paddr_region()
126 return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()127 (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()128 ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)); in mmu_ll_check_valid_paddr_region()
129 return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()130 (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && in mmu_ll_check_valid_paddr_region()131 ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)); in mmu_ll_check_valid_paddr_region()
47 #define MMU_MAX_PADDR_PAGE_NUM 256 macro
83 #define MMU_MAX_PADDR_PAGE_NUM 256 macro
86 #define MMU_MAX_PADDR_PAGE_NUM 256 macro
83 #define MMU_MAX_PADDR_PAGE_NUM 16384 macro
94 #define MMU_MAX_PADDR_PAGE_NUM 64 macro
112 #define MMU_MAX_PADDR_PAGE_NUM 16384 macro