Searched refs:MMU_ENTRY_NUM (Results 1 – 14 of 14) sorted by relevance
175 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()192 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()207 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()220 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_unmap_all()236 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()252 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_get_entry_target()269 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()288 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_find_entry_id_based_on_map_value()
176 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()192 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()207 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()220 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_unmap_all()236 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()252 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_get_entry_target()268 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()287 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_find_entry_id_based_on_map_value()
209 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()225 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()240 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()253 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_unmap_all()269 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()299 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()334 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_find_entry_id_based_on_map_value()
193 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()210 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()225 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()238 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_unmap_all()254 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()308 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_find_entry_id_based_on_map_value()
24 …ACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))88 #define MMU_ENTRY_NUM 256 macro94 #define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
269 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()292 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_unmap_all()308 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()327 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_get_entry_target()344 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()371 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_find_entry_id_based_on_map_value()
29 …_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 6…35 …_HIGH (DRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 6…101 #define MMU_ENTRY_NUM 64 macro
264 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_unmap_all()280 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()311 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()350 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_find_entry_id_based_on_map_value()
290 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_unmap_all()306 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()337 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()376 for (int i = 0; i < MMU_ENTRY_NUM; i++) { in mmu_ll_find_entry_id_based_on_map_value()
54 #define MMU_ENTRY_NUM 384 macro
90 #define MMU_ENTRY_NUM 128 macro
90 #define MMU_ENTRY_NUM 512 macro
119 #define MMU_ENTRY_NUM 384 macro
