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Searched refs:MEMCTL_DCWU_MASK (Results 1 – 1 of 1) sorted by relevance

/hal_espressif-latest/components/xtensa/include/xtensa/
Dcorebits.h184 #define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */ macro
187 #define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)