1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** LP_UART_FIFO_REG register 15 * FIFO data register 16 */ 17 #define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0) 18 /** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; 19 * UART $n accesses FIFO via this register. 20 */ 21 #define LP_UART_RXFIFO_RD_BYTE 0x000000FFU 22 #define LP_UART_RXFIFO_RD_BYTE_M (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S) 23 #define LP_UART_RXFIFO_RD_BYTE_V 0x000000FFU 24 #define LP_UART_RXFIFO_RD_BYTE_S 0 25 26 /** LP_UART_INT_RAW_REG register 27 * Raw interrupt status 28 */ 29 #define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4) 30 /** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; 31 * This interrupt raw bit turns to high level when receiver receives more data than 32 * what rxfifo_full_thrhd specifies. 33 */ 34 #define LP_UART_RXFIFO_FULL_INT_RAW (BIT(0)) 35 #define LP_UART_RXFIFO_FULL_INT_RAW_M (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S) 36 #define LP_UART_RXFIFO_FULL_INT_RAW_V 0x00000001U 37 #define LP_UART_RXFIFO_FULL_INT_RAW_S 0 38 /** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; 39 * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is 40 * less than what txfifo_empty_thrhd specifies . 41 */ 42 #define LP_UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) 43 #define LP_UART_TXFIFO_EMPTY_INT_RAW_M (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S) 44 #define LP_UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U 45 #define LP_UART_TXFIFO_EMPTY_INT_RAW_S 1 46 /** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; 47 * This interrupt raw bit turns to high level when receiver detects a parity error in 48 * the data. 49 */ 50 #define LP_UART_PARITY_ERR_INT_RAW (BIT(2)) 51 #define LP_UART_PARITY_ERR_INT_RAW_M (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S) 52 #define LP_UART_PARITY_ERR_INT_RAW_V 0x00000001U 53 #define LP_UART_PARITY_ERR_INT_RAW_S 2 54 /** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; 55 * This interrupt raw bit turns to high level when receiver detects a data frame error 56 * . 57 */ 58 #define LP_UART_FRM_ERR_INT_RAW (BIT(3)) 59 #define LP_UART_FRM_ERR_INT_RAW_M (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S) 60 #define LP_UART_FRM_ERR_INT_RAW_V 0x00000001U 61 #define LP_UART_FRM_ERR_INT_RAW_S 3 62 /** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; 63 * This interrupt raw bit turns to high level when receiver receives more data than 64 * the FIFO can store. 65 */ 66 #define LP_UART_RXFIFO_OVF_INT_RAW (BIT(4)) 67 #define LP_UART_RXFIFO_OVF_INT_RAW_M (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S) 68 #define LP_UART_RXFIFO_OVF_INT_RAW_V 0x00000001U 69 #define LP_UART_RXFIFO_OVF_INT_RAW_S 4 70 /** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; 71 * This interrupt raw bit turns to high level when receiver detects the edge change of 72 * DSRn signal. 73 */ 74 #define LP_UART_DSR_CHG_INT_RAW (BIT(5)) 75 #define LP_UART_DSR_CHG_INT_RAW_M (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S) 76 #define LP_UART_DSR_CHG_INT_RAW_V 0x00000001U 77 #define LP_UART_DSR_CHG_INT_RAW_S 5 78 /** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; 79 * This interrupt raw bit turns to high level when receiver detects the edge change of 80 * CTSn signal. 81 */ 82 #define LP_UART_CTS_CHG_INT_RAW (BIT(6)) 83 #define LP_UART_CTS_CHG_INT_RAW_M (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S) 84 #define LP_UART_CTS_CHG_INT_RAW_V 0x00000001U 85 #define LP_UART_CTS_CHG_INT_RAW_S 6 86 /** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; 87 * This interrupt raw bit turns to high level when receiver detects a 0 after the stop 88 * bit. 89 */ 90 #define LP_UART_BRK_DET_INT_RAW (BIT(7)) 91 #define LP_UART_BRK_DET_INT_RAW_M (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S) 92 #define LP_UART_BRK_DET_INT_RAW_V 0x00000001U 93 #define LP_UART_BRK_DET_INT_RAW_S 7 94 /** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; 95 * This interrupt raw bit turns to high level when receiver takes more time than 96 * rx_tout_thrhd to receive a byte. 97 */ 98 #define LP_UART_RXFIFO_TOUT_INT_RAW (BIT(8)) 99 #define LP_UART_RXFIFO_TOUT_INT_RAW_M (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S) 100 #define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U 101 #define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 102 /** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; 103 * This interrupt raw bit turns to high level when receiver recevies Xon char when 104 * uart_sw_flow_con_en is set to 1. 105 */ 106 #define LP_UART_SW_XON_INT_RAW (BIT(9)) 107 #define LP_UART_SW_XON_INT_RAW_M (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S) 108 #define LP_UART_SW_XON_INT_RAW_V 0x00000001U 109 #define LP_UART_SW_XON_INT_RAW_S 9 110 /** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; 111 * This interrupt raw bit turns to high level when receiver receives Xoff char when 112 * uart_sw_flow_con_en is set to 1. 113 */ 114 #define LP_UART_SW_XOFF_INT_RAW (BIT(10)) 115 #define LP_UART_SW_XOFF_INT_RAW_M (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S) 116 #define LP_UART_SW_XOFF_INT_RAW_V 0x00000001U 117 #define LP_UART_SW_XOFF_INT_RAW_S 10 118 /** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; 119 * This interrupt raw bit turns to high level when receiver detects a glitch in the 120 * middle of a start bit. 121 */ 122 #define LP_UART_GLITCH_DET_INT_RAW (BIT(11)) 123 #define LP_UART_GLITCH_DET_INT_RAW_M (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S) 124 #define LP_UART_GLITCH_DET_INT_RAW_V 0x00000001U 125 #define LP_UART_GLITCH_DET_INT_RAW_S 11 126 /** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; 127 * This interrupt raw bit turns to high level when transmitter completes sending 128 * NULL characters after all data in Tx-FIFO are sent. 129 */ 130 #define LP_UART_TX_BRK_DONE_INT_RAW (BIT(12)) 131 #define LP_UART_TX_BRK_DONE_INT_RAW_M (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S) 132 #define LP_UART_TX_BRK_DONE_INT_RAW_V 0x00000001U 133 #define LP_UART_TX_BRK_DONE_INT_RAW_S 12 134 /** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; 135 * This interrupt raw bit turns to high level when transmitter has kept the shortest 136 * duration after sending the last data. 137 */ 138 #define LP_UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) 139 #define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S) 140 #define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U 141 #define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 142 /** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; 143 * This interrupt raw bit turns to high level when transmitter has send out all data 144 * in FIFO. 145 */ 146 #define LP_UART_TX_DONE_INT_RAW (BIT(14)) 147 #define LP_UART_TX_DONE_INT_RAW_M (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S) 148 #define LP_UART_TX_DONE_INT_RAW_V 0x00000001U 149 #define LP_UART_TX_DONE_INT_RAW_S 14 150 /** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; 151 * This interrupt raw bit turns to high level when receiver detects the configured 152 * at_cmd char. 153 */ 154 #define LP_UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) 155 #define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S) 156 #define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U 157 #define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S 18 158 /** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; 159 * This interrupt raw bit turns to high level when input rxd edge changes more times 160 * than what reg_active_threshold specifies in light sleeping mode. 161 */ 162 #define LP_UART_WAKEUP_INT_RAW (BIT(19)) 163 #define LP_UART_WAKEUP_INT_RAW_M (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S) 164 #define LP_UART_WAKEUP_INT_RAW_V 0x00000001U 165 #define LP_UART_WAKEUP_INT_RAW_S 19 166 167 /** LP_UART_INT_ST_REG register 168 * Masked interrupt status 169 */ 170 #define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8) 171 /** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; 172 * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 173 */ 174 #define LP_UART_RXFIFO_FULL_INT_ST (BIT(0)) 175 #define LP_UART_RXFIFO_FULL_INT_ST_M (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S) 176 #define LP_UART_RXFIFO_FULL_INT_ST_V 0x00000001U 177 #define LP_UART_RXFIFO_FULL_INT_ST_S 0 178 /** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; 179 * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set 180 * to 1. 181 */ 182 #define LP_UART_TXFIFO_EMPTY_INT_ST (BIT(1)) 183 #define LP_UART_TXFIFO_EMPTY_INT_ST_M (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S) 184 #define LP_UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U 185 #define LP_UART_TXFIFO_EMPTY_INT_ST_S 1 186 /** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; 187 * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 188 */ 189 #define LP_UART_PARITY_ERR_INT_ST (BIT(2)) 190 #define LP_UART_PARITY_ERR_INT_ST_M (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S) 191 #define LP_UART_PARITY_ERR_INT_ST_V 0x00000001U 192 #define LP_UART_PARITY_ERR_INT_ST_S 2 193 /** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; 194 * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 195 */ 196 #define LP_UART_FRM_ERR_INT_ST (BIT(3)) 197 #define LP_UART_FRM_ERR_INT_ST_M (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S) 198 #define LP_UART_FRM_ERR_INT_ST_V 0x00000001U 199 #define LP_UART_FRM_ERR_INT_ST_S 3 200 /** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; 201 * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 202 */ 203 #define LP_UART_RXFIFO_OVF_INT_ST (BIT(4)) 204 #define LP_UART_RXFIFO_OVF_INT_ST_M (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S) 205 #define LP_UART_RXFIFO_OVF_INT_ST_V 0x00000001U 206 #define LP_UART_RXFIFO_OVF_INT_ST_S 4 207 /** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; 208 * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 209 */ 210 #define LP_UART_DSR_CHG_INT_ST (BIT(5)) 211 #define LP_UART_DSR_CHG_INT_ST_M (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S) 212 #define LP_UART_DSR_CHG_INT_ST_V 0x00000001U 213 #define LP_UART_DSR_CHG_INT_ST_S 5 214 /** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; 215 * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 216 */ 217 #define LP_UART_CTS_CHG_INT_ST (BIT(6)) 218 #define LP_UART_CTS_CHG_INT_ST_M (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S) 219 #define LP_UART_CTS_CHG_INT_ST_V 0x00000001U 220 #define LP_UART_CTS_CHG_INT_ST_S 6 221 /** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; 222 * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 223 */ 224 #define LP_UART_BRK_DET_INT_ST (BIT(7)) 225 #define LP_UART_BRK_DET_INT_ST_M (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S) 226 #define LP_UART_BRK_DET_INT_ST_V 0x00000001U 227 #define LP_UART_BRK_DET_INT_ST_S 7 228 /** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; 229 * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 230 */ 231 #define LP_UART_RXFIFO_TOUT_INT_ST (BIT(8)) 232 #define LP_UART_RXFIFO_TOUT_INT_ST_M (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S) 233 #define LP_UART_RXFIFO_TOUT_INT_ST_V 0x00000001U 234 #define LP_UART_RXFIFO_TOUT_INT_ST_S 8 235 /** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; 236 * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 237 */ 238 #define LP_UART_SW_XON_INT_ST (BIT(9)) 239 #define LP_UART_SW_XON_INT_ST_M (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S) 240 #define LP_UART_SW_XON_INT_ST_V 0x00000001U 241 #define LP_UART_SW_XON_INT_ST_S 9 242 /** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; 243 * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 244 */ 245 #define LP_UART_SW_XOFF_INT_ST (BIT(10)) 246 #define LP_UART_SW_XOFF_INT_ST_M (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S) 247 #define LP_UART_SW_XOFF_INT_ST_V 0x00000001U 248 #define LP_UART_SW_XOFF_INT_ST_S 10 249 /** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; 250 * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 251 */ 252 #define LP_UART_GLITCH_DET_INT_ST (BIT(11)) 253 #define LP_UART_GLITCH_DET_INT_ST_M (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S) 254 #define LP_UART_GLITCH_DET_INT_ST_V 0x00000001U 255 #define LP_UART_GLITCH_DET_INT_ST_S 11 256 /** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; 257 * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 258 */ 259 #define LP_UART_TX_BRK_DONE_INT_ST (BIT(12)) 260 #define LP_UART_TX_BRK_DONE_INT_ST_M (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S) 261 #define LP_UART_TX_BRK_DONE_INT_ST_V 0x00000001U 262 #define LP_UART_TX_BRK_DONE_INT_ST_S 12 263 /** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; 264 * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena 265 * is set to 1. 266 */ 267 #define LP_UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) 268 #define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S) 269 #define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U 270 #define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S 13 271 /** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; 272 * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 273 */ 274 #define LP_UART_TX_DONE_INT_ST (BIT(14)) 275 #define LP_UART_TX_DONE_INT_ST_M (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S) 276 #define LP_UART_TX_DONE_INT_ST_V 0x00000001U 277 #define LP_UART_TX_DONE_INT_ST_S 14 278 /** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; 279 * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set 280 * to 1. 281 */ 282 #define LP_UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) 283 #define LP_UART_AT_CMD_CHAR_DET_INT_ST_M (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S) 284 #define LP_UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U 285 #define LP_UART_AT_CMD_CHAR_DET_INT_ST_S 18 286 /** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; 287 * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. 288 */ 289 #define LP_UART_WAKEUP_INT_ST (BIT(19)) 290 #define LP_UART_WAKEUP_INT_ST_M (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S) 291 #define LP_UART_WAKEUP_INT_ST_V 0x00000001U 292 #define LP_UART_WAKEUP_INT_ST_S 19 293 294 /** LP_UART_INT_ENA_REG register 295 * Interrupt enable bits 296 */ 297 #define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc) 298 /** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; 299 * This is the enable bit for rxfifo_full_int_st register. 300 */ 301 #define LP_UART_RXFIFO_FULL_INT_ENA (BIT(0)) 302 #define LP_UART_RXFIFO_FULL_INT_ENA_M (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S) 303 #define LP_UART_RXFIFO_FULL_INT_ENA_V 0x00000001U 304 #define LP_UART_RXFIFO_FULL_INT_ENA_S 0 305 /** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; 306 * This is the enable bit for txfifo_empty_int_st register. 307 */ 308 #define LP_UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) 309 #define LP_UART_TXFIFO_EMPTY_INT_ENA_M (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S) 310 #define LP_UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U 311 #define LP_UART_TXFIFO_EMPTY_INT_ENA_S 1 312 /** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; 313 * This is the enable bit for parity_err_int_st register. 314 */ 315 #define LP_UART_PARITY_ERR_INT_ENA (BIT(2)) 316 #define LP_UART_PARITY_ERR_INT_ENA_M (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S) 317 #define LP_UART_PARITY_ERR_INT_ENA_V 0x00000001U 318 #define LP_UART_PARITY_ERR_INT_ENA_S 2 319 /** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; 320 * This is the enable bit for frm_err_int_st register. 321 */ 322 #define LP_UART_FRM_ERR_INT_ENA (BIT(3)) 323 #define LP_UART_FRM_ERR_INT_ENA_M (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S) 324 #define LP_UART_FRM_ERR_INT_ENA_V 0x00000001U 325 #define LP_UART_FRM_ERR_INT_ENA_S 3 326 /** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; 327 * This is the enable bit for rxfifo_ovf_int_st register. 328 */ 329 #define LP_UART_RXFIFO_OVF_INT_ENA (BIT(4)) 330 #define LP_UART_RXFIFO_OVF_INT_ENA_M (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S) 331 #define LP_UART_RXFIFO_OVF_INT_ENA_V 0x00000001U 332 #define LP_UART_RXFIFO_OVF_INT_ENA_S 4 333 /** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; 334 * This is the enable bit for dsr_chg_int_st register. 335 */ 336 #define LP_UART_DSR_CHG_INT_ENA (BIT(5)) 337 #define LP_UART_DSR_CHG_INT_ENA_M (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S) 338 #define LP_UART_DSR_CHG_INT_ENA_V 0x00000001U 339 #define LP_UART_DSR_CHG_INT_ENA_S 5 340 /** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; 341 * This is the enable bit for cts_chg_int_st register. 342 */ 343 #define LP_UART_CTS_CHG_INT_ENA (BIT(6)) 344 #define LP_UART_CTS_CHG_INT_ENA_M (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S) 345 #define LP_UART_CTS_CHG_INT_ENA_V 0x00000001U 346 #define LP_UART_CTS_CHG_INT_ENA_S 6 347 /** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; 348 * This is the enable bit for brk_det_int_st register. 349 */ 350 #define LP_UART_BRK_DET_INT_ENA (BIT(7)) 351 #define LP_UART_BRK_DET_INT_ENA_M (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S) 352 #define LP_UART_BRK_DET_INT_ENA_V 0x00000001U 353 #define LP_UART_BRK_DET_INT_ENA_S 7 354 /** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; 355 * This is the enable bit for rxfifo_tout_int_st register. 356 */ 357 #define LP_UART_RXFIFO_TOUT_INT_ENA (BIT(8)) 358 #define LP_UART_RXFIFO_TOUT_INT_ENA_M (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S) 359 #define LP_UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U 360 #define LP_UART_RXFIFO_TOUT_INT_ENA_S 8 361 /** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; 362 * This is the enable bit for sw_xon_int_st register. 363 */ 364 #define LP_UART_SW_XON_INT_ENA (BIT(9)) 365 #define LP_UART_SW_XON_INT_ENA_M (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S) 366 #define LP_UART_SW_XON_INT_ENA_V 0x00000001U 367 #define LP_UART_SW_XON_INT_ENA_S 9 368 /** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; 369 * This is the enable bit for sw_xoff_int_st register. 370 */ 371 #define LP_UART_SW_XOFF_INT_ENA (BIT(10)) 372 #define LP_UART_SW_XOFF_INT_ENA_M (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S) 373 #define LP_UART_SW_XOFF_INT_ENA_V 0x00000001U 374 #define LP_UART_SW_XOFF_INT_ENA_S 10 375 /** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; 376 * This is the enable bit for glitch_det_int_st register. 377 */ 378 #define LP_UART_GLITCH_DET_INT_ENA (BIT(11)) 379 #define LP_UART_GLITCH_DET_INT_ENA_M (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S) 380 #define LP_UART_GLITCH_DET_INT_ENA_V 0x00000001U 381 #define LP_UART_GLITCH_DET_INT_ENA_S 11 382 /** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; 383 * This is the enable bit for tx_brk_done_int_st register. 384 */ 385 #define LP_UART_TX_BRK_DONE_INT_ENA (BIT(12)) 386 #define LP_UART_TX_BRK_DONE_INT_ENA_M (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S) 387 #define LP_UART_TX_BRK_DONE_INT_ENA_V 0x00000001U 388 #define LP_UART_TX_BRK_DONE_INT_ENA_S 12 389 /** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; 390 * This is the enable bit for tx_brk_idle_done_int_st register. 391 */ 392 #define LP_UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) 393 #define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S) 394 #define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U 395 #define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 396 /** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; 397 * This is the enable bit for tx_done_int_st register. 398 */ 399 #define LP_UART_TX_DONE_INT_ENA (BIT(14)) 400 #define LP_UART_TX_DONE_INT_ENA_M (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S) 401 #define LP_UART_TX_DONE_INT_ENA_V 0x00000001U 402 #define LP_UART_TX_DONE_INT_ENA_S 14 403 /** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; 404 * This is the enable bit for at_cmd_char_det_int_st register. 405 */ 406 #define LP_UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) 407 #define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S) 408 #define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U 409 #define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S 18 410 /** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; 411 * This is the enable bit for uart_wakeup_int_st register. 412 */ 413 #define LP_UART_WAKEUP_INT_ENA (BIT(19)) 414 #define LP_UART_WAKEUP_INT_ENA_M (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S) 415 #define LP_UART_WAKEUP_INT_ENA_V 0x00000001U 416 #define LP_UART_WAKEUP_INT_ENA_S 19 417 418 /** LP_UART_INT_CLR_REG register 419 * Interrupt clear bits 420 */ 421 #define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10) 422 /** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; 423 * Set this bit to clear the rxfifo_full_int_raw interrupt. 424 */ 425 #define LP_UART_RXFIFO_FULL_INT_CLR (BIT(0)) 426 #define LP_UART_RXFIFO_FULL_INT_CLR_M (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S) 427 #define LP_UART_RXFIFO_FULL_INT_CLR_V 0x00000001U 428 #define LP_UART_RXFIFO_FULL_INT_CLR_S 0 429 /** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; 430 * Set this bit to clear txfifo_empty_int_raw interrupt. 431 */ 432 #define LP_UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) 433 #define LP_UART_TXFIFO_EMPTY_INT_CLR_M (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S) 434 #define LP_UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U 435 #define LP_UART_TXFIFO_EMPTY_INT_CLR_S 1 436 /** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; 437 * Set this bit to clear parity_err_int_raw interrupt. 438 */ 439 #define LP_UART_PARITY_ERR_INT_CLR (BIT(2)) 440 #define LP_UART_PARITY_ERR_INT_CLR_M (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S) 441 #define LP_UART_PARITY_ERR_INT_CLR_V 0x00000001U 442 #define LP_UART_PARITY_ERR_INT_CLR_S 2 443 /** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; 444 * Set this bit to clear frm_err_int_raw interrupt. 445 */ 446 #define LP_UART_FRM_ERR_INT_CLR (BIT(3)) 447 #define LP_UART_FRM_ERR_INT_CLR_M (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S) 448 #define LP_UART_FRM_ERR_INT_CLR_V 0x00000001U 449 #define LP_UART_FRM_ERR_INT_CLR_S 3 450 /** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; 451 * Set this bit to clear rxfifo_ovf_int_raw interrupt. 452 */ 453 #define LP_UART_RXFIFO_OVF_INT_CLR (BIT(4)) 454 #define LP_UART_RXFIFO_OVF_INT_CLR_M (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S) 455 #define LP_UART_RXFIFO_OVF_INT_CLR_V 0x00000001U 456 #define LP_UART_RXFIFO_OVF_INT_CLR_S 4 457 /** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; 458 * Set this bit to clear the dsr_chg_int_raw interrupt. 459 */ 460 #define LP_UART_DSR_CHG_INT_CLR (BIT(5)) 461 #define LP_UART_DSR_CHG_INT_CLR_M (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S) 462 #define LP_UART_DSR_CHG_INT_CLR_V 0x00000001U 463 #define LP_UART_DSR_CHG_INT_CLR_S 5 464 /** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; 465 * Set this bit to clear the cts_chg_int_raw interrupt. 466 */ 467 #define LP_UART_CTS_CHG_INT_CLR (BIT(6)) 468 #define LP_UART_CTS_CHG_INT_CLR_M (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S) 469 #define LP_UART_CTS_CHG_INT_CLR_V 0x00000001U 470 #define LP_UART_CTS_CHG_INT_CLR_S 6 471 /** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; 472 * Set this bit to clear the brk_det_int_raw interrupt. 473 */ 474 #define LP_UART_BRK_DET_INT_CLR (BIT(7)) 475 #define LP_UART_BRK_DET_INT_CLR_M (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S) 476 #define LP_UART_BRK_DET_INT_CLR_V 0x00000001U 477 #define LP_UART_BRK_DET_INT_CLR_S 7 478 /** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; 479 * Set this bit to clear the rxfifo_tout_int_raw interrupt. 480 */ 481 #define LP_UART_RXFIFO_TOUT_INT_CLR (BIT(8)) 482 #define LP_UART_RXFIFO_TOUT_INT_CLR_M (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S) 483 #define LP_UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U 484 #define LP_UART_RXFIFO_TOUT_INT_CLR_S 8 485 /** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; 486 * Set this bit to clear the sw_xon_int_raw interrupt. 487 */ 488 #define LP_UART_SW_XON_INT_CLR (BIT(9)) 489 #define LP_UART_SW_XON_INT_CLR_M (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S) 490 #define LP_UART_SW_XON_INT_CLR_V 0x00000001U 491 #define LP_UART_SW_XON_INT_CLR_S 9 492 /** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; 493 * Set this bit to clear the sw_xoff_int_raw interrupt. 494 */ 495 #define LP_UART_SW_XOFF_INT_CLR (BIT(10)) 496 #define LP_UART_SW_XOFF_INT_CLR_M (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S) 497 #define LP_UART_SW_XOFF_INT_CLR_V 0x00000001U 498 #define LP_UART_SW_XOFF_INT_CLR_S 10 499 /** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; 500 * Set this bit to clear the glitch_det_int_raw interrupt. 501 */ 502 #define LP_UART_GLITCH_DET_INT_CLR (BIT(11)) 503 #define LP_UART_GLITCH_DET_INT_CLR_M (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S) 504 #define LP_UART_GLITCH_DET_INT_CLR_V 0x00000001U 505 #define LP_UART_GLITCH_DET_INT_CLR_S 11 506 /** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; 507 * Set this bit to clear the tx_brk_done_int_raw interrupt.. 508 */ 509 #define LP_UART_TX_BRK_DONE_INT_CLR (BIT(12)) 510 #define LP_UART_TX_BRK_DONE_INT_CLR_M (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S) 511 #define LP_UART_TX_BRK_DONE_INT_CLR_V 0x00000001U 512 #define LP_UART_TX_BRK_DONE_INT_CLR_S 12 513 /** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; 514 * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 515 */ 516 #define LP_UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) 517 #define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S) 518 #define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U 519 #define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 520 /** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; 521 * Set this bit to clear the tx_done_int_raw interrupt. 522 */ 523 #define LP_UART_TX_DONE_INT_CLR (BIT(14)) 524 #define LP_UART_TX_DONE_INT_CLR_M (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S) 525 #define LP_UART_TX_DONE_INT_CLR_V 0x00000001U 526 #define LP_UART_TX_DONE_INT_CLR_S 14 527 /** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; 528 * Set this bit to clear the at_cmd_char_det_int_raw interrupt. 529 */ 530 #define LP_UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) 531 #define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S) 532 #define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U 533 #define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S 18 534 /** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; 535 * Set this bit to clear the uart_wakeup_int_raw interrupt. 536 */ 537 #define LP_UART_WAKEUP_INT_CLR (BIT(19)) 538 #define LP_UART_WAKEUP_INT_CLR_M (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S) 539 #define LP_UART_WAKEUP_INT_CLR_V 0x00000001U 540 #define LP_UART_WAKEUP_INT_CLR_S 19 541 542 /** LP_UART_CLKDIV_SYNC_REG register 543 * Clock divider configuration 544 */ 545 #define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14) 546 /** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; 547 * The integral part of the frequency divider factor. 548 */ 549 #define LP_UART_CLKDIV 0x00000FFFU 550 #define LP_UART_CLKDIV_M (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S) 551 #define LP_UART_CLKDIV_V 0x00000FFFU 552 #define LP_UART_CLKDIV_S 0 553 /** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; 554 * The decimal part of the frequency divider factor. 555 */ 556 #define LP_UART_CLKDIV_FRAG 0x0000000FU 557 #define LP_UART_CLKDIV_FRAG_M (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S) 558 #define LP_UART_CLKDIV_FRAG_V 0x0000000FU 559 #define LP_UART_CLKDIV_FRAG_S 20 560 561 /** LP_UART_RX_FILT_REG register 562 * Rx Filter configuration 563 */ 564 #define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18) 565 /** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; 566 * when input pulse width is lower than this value the pulse is ignored. 567 */ 568 #define LP_UART_GLITCH_FILT 0x000000FFU 569 #define LP_UART_GLITCH_FILT_M (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S) 570 #define LP_UART_GLITCH_FILT_V 0x000000FFU 571 #define LP_UART_GLITCH_FILT_S 0 572 /** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; 573 * Set this bit to enable Rx signal filter. 574 */ 575 #define LP_UART_GLITCH_FILT_EN (BIT(8)) 576 #define LP_UART_GLITCH_FILT_EN_M (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S) 577 #define LP_UART_GLITCH_FILT_EN_V 0x00000001U 578 #define LP_UART_GLITCH_FILT_EN_S 8 579 580 /** LP_UART_STATUS_REG register 581 * UART status register 582 */ 583 #define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c) 584 /** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0; 585 * Stores the byte number of valid data in Rx-FIFO. 586 */ 587 #define LP_UART_RXFIFO_CNT 0x0000001FU 588 #define LP_UART_RXFIFO_CNT_M (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S) 589 #define LP_UART_RXFIFO_CNT_V 0x0000001FU 590 #define LP_UART_RXFIFO_CNT_S 3 591 /** LP_UART_DSRN : RO; bitpos: [13]; default: 0; 592 * The register represent the level value of the internal uart dsr signal. 593 */ 594 #define LP_UART_DSRN (BIT(13)) 595 #define LP_UART_DSRN_M (LP_UART_DSRN_V << LP_UART_DSRN_S) 596 #define LP_UART_DSRN_V 0x00000001U 597 #define LP_UART_DSRN_S 13 598 /** LP_UART_CTSN : RO; bitpos: [14]; default: 1; 599 * This register represent the level value of the internal uart cts signal. 600 */ 601 #define LP_UART_CTSN (BIT(14)) 602 #define LP_UART_CTSN_M (LP_UART_CTSN_V << LP_UART_CTSN_S) 603 #define LP_UART_CTSN_V 0x00000001U 604 #define LP_UART_CTSN_S 14 605 /** LP_UART_RXD : RO; bitpos: [15]; default: 1; 606 * This register represent the level value of the internal uart rxd signal. 607 */ 608 #define LP_UART_RXD (BIT(15)) 609 #define LP_UART_RXD_M (LP_UART_RXD_V << LP_UART_RXD_S) 610 #define LP_UART_RXD_V 0x00000001U 611 #define LP_UART_RXD_S 15 612 /** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0; 613 * Stores the byte number of data in Tx-FIFO. 614 */ 615 #define LP_UART_TXFIFO_CNT 0x0000001FU 616 #define LP_UART_TXFIFO_CNT_M (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S) 617 #define LP_UART_TXFIFO_CNT_V 0x0000001FU 618 #define LP_UART_TXFIFO_CNT_S 19 619 /** LP_UART_DTRN : RO; bitpos: [29]; default: 1; 620 * This bit represents the level of the internal uart dtr signal. 621 */ 622 #define LP_UART_DTRN (BIT(29)) 623 #define LP_UART_DTRN_M (LP_UART_DTRN_V << LP_UART_DTRN_S) 624 #define LP_UART_DTRN_V 0x00000001U 625 #define LP_UART_DTRN_S 29 626 /** LP_UART_RTSN : RO; bitpos: [30]; default: 1; 627 * This bit represents the level of the internal uart rts signal. 628 */ 629 #define LP_UART_RTSN (BIT(30)) 630 #define LP_UART_RTSN_M (LP_UART_RTSN_V << LP_UART_RTSN_S) 631 #define LP_UART_RTSN_V 0x00000001U 632 #define LP_UART_RTSN_S 30 633 /** LP_UART_TXD : RO; bitpos: [31]; default: 1; 634 * This bit represents the level of the internal uart txd signal. 635 */ 636 #define LP_UART_TXD (BIT(31)) 637 #define LP_UART_TXD_M (LP_UART_TXD_V << LP_UART_TXD_S) 638 #define LP_UART_TXD_V 0x00000001U 639 #define LP_UART_TXD_S 31 640 641 /** LP_UART_CONF0_SYNC_REG register 642 * Configuration register 0 643 */ 644 #define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20) 645 /** LP_UART_PARITY : R/W; bitpos: [0]; default: 0; 646 * This register is used to configure the parity check mode. 647 */ 648 #define LP_UART_PARITY (BIT(0)) 649 #define LP_UART_PARITY_M (LP_UART_PARITY_V << LP_UART_PARITY_S) 650 #define LP_UART_PARITY_V 0x00000001U 651 #define LP_UART_PARITY_S 0 652 /** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0; 653 * Set this bit to enable uart parity check. 654 */ 655 #define LP_UART_PARITY_EN (BIT(1)) 656 #define LP_UART_PARITY_EN_M (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S) 657 #define LP_UART_PARITY_EN_V 0x00000001U 658 #define LP_UART_PARITY_EN_S 1 659 /** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; 660 * This register is used to set the length of data. 661 */ 662 #define LP_UART_BIT_NUM 0x00000003U 663 #define LP_UART_BIT_NUM_M (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S) 664 #define LP_UART_BIT_NUM_V 0x00000003U 665 #define LP_UART_BIT_NUM_S 2 666 /** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; 667 * This register is used to set the length of stop bit. 668 */ 669 #define LP_UART_STOP_BIT_NUM 0x00000003U 670 #define LP_UART_STOP_BIT_NUM_M (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S) 671 #define LP_UART_STOP_BIT_NUM_V 0x00000003U 672 #define LP_UART_STOP_BIT_NUM_S 4 673 /** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; 674 * Set this bit to enbale transmitter to send NULL when the process of sending data 675 * is done. 676 */ 677 #define LP_UART_TXD_BRK (BIT(6)) 678 #define LP_UART_TXD_BRK_M (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S) 679 #define LP_UART_TXD_BRK_V 0x00000001U 680 #define LP_UART_TXD_BRK_S 6 681 /** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0; 682 * Set this bit to enable uart loopback test mode. 683 */ 684 #define LP_UART_LOOPBACK (BIT(12)) 685 #define LP_UART_LOOPBACK_M (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S) 686 #define LP_UART_LOOPBACK_V 0x00000001U 687 #define LP_UART_LOOPBACK_S 12 688 /** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; 689 * Set this bit to enable flow control function for transmitter. 690 */ 691 #define LP_UART_TX_FLOW_EN (BIT(13)) 692 #define LP_UART_TX_FLOW_EN_M (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S) 693 #define LP_UART_TX_FLOW_EN_V 0x00000001U 694 #define LP_UART_TX_FLOW_EN_S 13 695 /** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0; 696 * Set this bit to inverse the level value of uart rxd signal. 697 */ 698 #define LP_UART_RXD_INV (BIT(15)) 699 #define LP_UART_RXD_INV_M (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S) 700 #define LP_UART_RXD_INV_V 0x00000001U 701 #define LP_UART_RXD_INV_S 15 702 /** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0; 703 * Set this bit to inverse the level value of uart txd signal. 704 */ 705 #define LP_UART_TXD_INV (BIT(16)) 706 #define LP_UART_TXD_INV_M (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S) 707 #define LP_UART_TXD_INV_V 0x00000001U 708 #define LP_UART_TXD_INV_S 16 709 /** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; 710 * Disable UART Rx data overflow detect. 711 */ 712 #define LP_UART_DIS_RX_DAT_OVF (BIT(17)) 713 #define LP_UART_DIS_RX_DAT_OVF_M (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S) 714 #define LP_UART_DIS_RX_DAT_OVF_V 0x00000001U 715 #define LP_UART_DIS_RX_DAT_OVF_S 17 716 /** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; 717 * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver 718 * stores the data even if the received data is wrong. 719 */ 720 #define LP_UART_ERR_WR_MASK (BIT(18)) 721 #define LP_UART_ERR_WR_MASK_M (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S) 722 #define LP_UART_ERR_WR_MASK_V 0x00000001U 723 #define LP_UART_ERR_WR_MASK_S 18 724 /** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; 725 * UART memory clock gate enable signal. 726 */ 727 #define LP_UART_MEM_CLK_EN (BIT(20)) 728 #define LP_UART_MEM_CLK_EN_M (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S) 729 #define LP_UART_MEM_CLK_EN_V 0x00000001U 730 #define LP_UART_MEM_CLK_EN_S 20 731 /** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0; 732 * This register is used to configure the software rts signal which is used in 733 * software flow control. 734 */ 735 #define LP_UART_SW_RTS (BIT(21)) 736 #define LP_UART_SW_RTS_M (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S) 737 #define LP_UART_SW_RTS_V 0x00000001U 738 #define LP_UART_SW_RTS_S 21 739 /** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; 740 * Set this bit to reset the uart receive-FIFO. 741 */ 742 #define LP_UART_RXFIFO_RST (BIT(22)) 743 #define LP_UART_RXFIFO_RST_M (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S) 744 #define LP_UART_RXFIFO_RST_V 0x00000001U 745 #define LP_UART_RXFIFO_RST_S 22 746 /** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; 747 * Set this bit to reset the uart transmit-FIFO. 748 */ 749 #define LP_UART_TXFIFO_RST (BIT(23)) 750 #define LP_UART_TXFIFO_RST_M (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S) 751 #define LP_UART_TXFIFO_RST_V 0x00000001U 752 #define LP_UART_TXFIFO_RST_S 23 753 754 /** LP_UART_CONF1_REG register 755 * Configuration register 1 756 */ 757 #define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24) 758 /** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12; 759 * It will produce rxfifo_full_int interrupt when receiver receives more data than 760 * this register value. 761 */ 762 #define LP_UART_RXFIFO_FULL_THRHD 0x0000001FU 763 #define LP_UART_RXFIFO_FULL_THRHD_M (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S) 764 #define LP_UART_RXFIFO_FULL_THRHD_V 0x0000001FU 765 #define LP_UART_RXFIFO_FULL_THRHD_S 3 766 /** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12; 767 * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less 768 * than this register value. 769 */ 770 #define LP_UART_TXFIFO_EMPTY_THRHD 0x0000001FU 771 #define LP_UART_TXFIFO_EMPTY_THRHD_M (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S) 772 #define LP_UART_TXFIFO_EMPTY_THRHD_V 0x0000001FU 773 #define LP_UART_TXFIFO_EMPTY_THRHD_S 11 774 /** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0; 775 * Set this bit to inverse the level value of uart cts signal. 776 */ 777 #define LP_UART_CTS_INV (BIT(16)) 778 #define LP_UART_CTS_INV_M (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S) 779 #define LP_UART_CTS_INV_V 0x00000001U 780 #define LP_UART_CTS_INV_S 16 781 /** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0; 782 * Set this bit to inverse the level value of uart dsr signal. 783 */ 784 #define LP_UART_DSR_INV (BIT(17)) 785 #define LP_UART_DSR_INV_M (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S) 786 #define LP_UART_DSR_INV_V 0x00000001U 787 #define LP_UART_DSR_INV_S 17 788 /** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0; 789 * Set this bit to inverse the level value of uart rts signal. 790 */ 791 #define LP_UART_RTS_INV (BIT(18)) 792 #define LP_UART_RTS_INV_M (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S) 793 #define LP_UART_RTS_INV_V 0x00000001U 794 #define LP_UART_RTS_INV_S 18 795 /** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0; 796 * Set this bit to inverse the level value of uart dtr signal. 797 */ 798 #define LP_UART_DTR_INV (BIT(19)) 799 #define LP_UART_DTR_INV_M (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S) 800 #define LP_UART_DTR_INV_V 0x00000001U 801 #define LP_UART_DTR_INV_S 19 802 /** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0; 803 * This register is used to configure the software dtr signal which is used in 804 * software flow control. 805 */ 806 #define LP_UART_SW_DTR (BIT(20)) 807 #define LP_UART_SW_DTR_M (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S) 808 #define LP_UART_SW_DTR_V 0x00000001U 809 #define LP_UART_SW_DTR_S 20 810 /** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0; 811 * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes 812 * registers. 813 */ 814 #define LP_UART_CLK_EN (BIT(21)) 815 #define LP_UART_CLK_EN_M (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S) 816 #define LP_UART_CLK_EN_V 0x00000001U 817 #define LP_UART_CLK_EN_S 21 818 819 /** LP_UART_HWFC_CONF_SYNC_REG register 820 * Hardware flow-control configuration 821 */ 822 #define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c) 823 /** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0; 824 * This register is used to configure the maximum amount of data that can be received 825 * when hardware flow control works. 826 */ 827 #define LP_UART_RX_FLOW_THRHD 0x0000001FU 828 #define LP_UART_RX_FLOW_THRHD_M (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S) 829 #define LP_UART_RX_FLOW_THRHD_V 0x0000001FU 830 #define LP_UART_RX_FLOW_THRHD_S 3 831 /** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; 832 * This is the flow enable bit for UART receiver. 833 */ 834 #define LP_UART_RX_FLOW_EN (BIT(8)) 835 #define LP_UART_RX_FLOW_EN_M (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S) 836 #define LP_UART_RX_FLOW_EN_V 0x00000001U 837 #define LP_UART_RX_FLOW_EN_S 8 838 839 /** LP_UART_SLEEP_CONF0_REG register 840 * UART sleep configure register 0 841 */ 842 #define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30) 843 /** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; 844 * This register restores the specified wake up char1 to wake up 845 */ 846 #define LP_UART_WK_CHAR1 0x000000FFU 847 #define LP_UART_WK_CHAR1_M (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S) 848 #define LP_UART_WK_CHAR1_V 0x000000FFU 849 #define LP_UART_WK_CHAR1_S 0 850 /** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; 851 * This register restores the specified wake up char2 to wake up 852 */ 853 #define LP_UART_WK_CHAR2 0x000000FFU 854 #define LP_UART_WK_CHAR2_M (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S) 855 #define LP_UART_WK_CHAR2_V 0x000000FFU 856 #define LP_UART_WK_CHAR2_S 8 857 /** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; 858 * This register restores the specified wake up char3 to wake up 859 */ 860 #define LP_UART_WK_CHAR3 0x000000FFU 861 #define LP_UART_WK_CHAR3_M (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S) 862 #define LP_UART_WK_CHAR3_V 0x000000FFU 863 #define LP_UART_WK_CHAR3_S 16 864 /** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; 865 * This register restores the specified wake up char4 to wake up 866 */ 867 #define LP_UART_WK_CHAR4 0x000000FFU 868 #define LP_UART_WK_CHAR4_M (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S) 869 #define LP_UART_WK_CHAR4_V 0x000000FFU 870 #define LP_UART_WK_CHAR4_S 24 871 872 /** LP_UART_SLEEP_CONF1_REG register 873 * UART sleep configure register 1 874 */ 875 #define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34) 876 /** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; 877 * This register restores the specified char0 to wake up 878 */ 879 #define LP_UART_WK_CHAR0 0x000000FFU 880 #define LP_UART_WK_CHAR0_M (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S) 881 #define LP_UART_WK_CHAR0_V 0x000000FFU 882 #define LP_UART_WK_CHAR0_S 0 883 884 /** LP_UART_SLEEP_CONF2_REG register 885 * UART sleep configure register 2 886 */ 887 #define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38) 888 /** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; 889 * The uart is activated from light sleeping mode when the input rxd edge changes more 890 * times than this register value. 891 */ 892 #define LP_UART_ACTIVE_THRESHOLD 0x000003FFU 893 #define LP_UART_ACTIVE_THRESHOLD_M (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S) 894 #define LP_UART_ACTIVE_THRESHOLD_V 0x000003FFU 895 #define LP_UART_ACTIVE_THRESHOLD_S 0 896 /** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1; 897 * In wake up mode 1 this field is used to set the received data number threshold to 898 * wake up chip. 899 */ 900 #define LP_UART_RX_WAKE_UP_THRHD 0x0000001FU 901 #define LP_UART_RX_WAKE_UP_THRHD_M (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S) 902 #define LP_UART_RX_WAKE_UP_THRHD_V 0x0000001FU 903 #define LP_UART_RX_WAKE_UP_THRHD_S 13 904 /** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; 905 * This register is used to select number of wake up char. 906 */ 907 #define LP_UART_WK_CHAR_NUM 0x00000007U 908 #define LP_UART_WK_CHAR_NUM_M (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S) 909 #define LP_UART_WK_CHAR_NUM_V 0x00000007U 910 #define LP_UART_WK_CHAR_NUM_S 18 911 /** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; 912 * This register is used to mask wake up char. 913 */ 914 #define LP_UART_WK_CHAR_MASK 0x0000001FU 915 #define LP_UART_WK_CHAR_MASK_M (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S) 916 #define LP_UART_WK_CHAR_MASK_V 0x0000001FU 917 #define LP_UART_WK_CHAR_MASK_S 21 918 /** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; 919 * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: 920 * received data number larger than 921 */ 922 #define LP_UART_WK_MODE_SEL 0x00000003U 923 #define LP_UART_WK_MODE_SEL_M (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S) 924 #define LP_UART_WK_MODE_SEL_V 0x00000003U 925 #define LP_UART_WK_MODE_SEL_S 26 926 927 /** LP_UART_SWFC_CONF0_SYNC_REG register 928 * Software flow-control character configuration 929 */ 930 #define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c) 931 /** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; 932 * This register stores the Xon flow control char. 933 */ 934 #define LP_UART_XON_CHAR 0x000000FFU 935 #define LP_UART_XON_CHAR_M (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S) 936 #define LP_UART_XON_CHAR_V 0x000000FFU 937 #define LP_UART_XON_CHAR_S 0 938 /** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; 939 * This register stores the Xoff flow control char. 940 */ 941 #define LP_UART_XOFF_CHAR 0x000000FFU 942 #define LP_UART_XOFF_CHAR_M (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S) 943 #define LP_UART_XOFF_CHAR_V 0x000000FFU 944 #define LP_UART_XOFF_CHAR_S 8 945 /** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; 946 * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In 947 * this status, UART Tx can not transmit XOFF even the received data number is larger 948 * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when 949 * UART Tx is disabled. 950 */ 951 #define LP_UART_XON_XOFF_STILL_SEND (BIT(16)) 952 #define LP_UART_XON_XOFF_STILL_SEND_M (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S) 953 #define LP_UART_XON_XOFF_STILL_SEND_V 0x00000001U 954 #define LP_UART_XON_XOFF_STILL_SEND_S 16 955 /** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; 956 * Set this bit to enable software flow control. It is used with register sw_xon or 957 * sw_xoff. 958 */ 959 #define LP_UART_SW_FLOW_CON_EN (BIT(17)) 960 #define LP_UART_SW_FLOW_CON_EN_M (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S) 961 #define LP_UART_SW_FLOW_CON_EN_V 0x00000001U 962 #define LP_UART_SW_FLOW_CON_EN_S 17 963 /** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; 964 * Set this bit to remove flow control char from the received data. 965 */ 966 #define LP_UART_XONOFF_DEL (BIT(18)) 967 #define LP_UART_XONOFF_DEL_M (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S) 968 #define LP_UART_XONOFF_DEL_V 0x00000001U 969 #define LP_UART_XONOFF_DEL_S 18 970 /** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0; 971 * Set this bit to enable the transmitter to go on sending data. 972 */ 973 #define LP_UART_FORCE_XON (BIT(19)) 974 #define LP_UART_FORCE_XON_M (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S) 975 #define LP_UART_FORCE_XON_V 0x00000001U 976 #define LP_UART_FORCE_XON_S 19 977 /** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; 978 * Set this bit to stop the transmitter from sending data. 979 */ 980 #define LP_UART_FORCE_XOFF (BIT(20)) 981 #define LP_UART_FORCE_XOFF_M (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S) 982 #define LP_UART_FORCE_XOFF_V 0x00000001U 983 #define LP_UART_FORCE_XOFF_S 20 984 /** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; 985 * Set this bit to send Xon char. It is cleared by hardware automatically. 986 */ 987 #define LP_UART_SEND_XON (BIT(21)) 988 #define LP_UART_SEND_XON_M (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S) 989 #define LP_UART_SEND_XON_V 0x00000001U 990 #define LP_UART_SEND_XON_S 21 991 /** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; 992 * Set this bit to send Xoff char. It is cleared by hardware automatically. 993 */ 994 #define LP_UART_SEND_XOFF (BIT(22)) 995 #define LP_UART_SEND_XOFF_M (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S) 996 #define LP_UART_SEND_XOFF_V 0x00000001U 997 #define LP_UART_SEND_XOFF_S 22 998 999 /** LP_UART_SWFC_CONF1_REG register 1000 * Software flow-control character configuration 1001 */ 1002 #define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40) 1003 /** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0; 1004 * When the data amount in Rx-FIFO is less than this register value with 1005 * uart_sw_flow_con_en set to 1 it will send a Xon char. 1006 */ 1007 #define LP_UART_XON_THRESHOLD 0x0000001FU 1008 #define LP_UART_XON_THRESHOLD_M (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S) 1009 #define LP_UART_XON_THRESHOLD_V 0x0000001FU 1010 #define LP_UART_XON_THRESHOLD_S 3 1011 /** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12; 1012 * When the data amount in Rx-FIFO is more than this register value with 1013 * uart_sw_flow_con_en set to 1 it will send a Xoff char. 1014 */ 1015 #define LP_UART_XOFF_THRESHOLD 0x0000001FU 1016 #define LP_UART_XOFF_THRESHOLD_M (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S) 1017 #define LP_UART_XOFF_THRESHOLD_V 0x0000001FU 1018 #define LP_UART_XOFF_THRESHOLD_S 11 1019 1020 /** LP_UART_TXBRK_CONF_SYNC_REG register 1021 * Tx Break character configuration 1022 */ 1023 #define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44) 1024 /** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; 1025 * This register is used to configure the number of 0 to be sent after the process of 1026 * sending data is done. It is active when txd_brk is set to 1. 1027 */ 1028 #define LP_UART_TX_BRK_NUM 0x000000FFU 1029 #define LP_UART_TX_BRK_NUM_M (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S) 1030 #define LP_UART_TX_BRK_NUM_V 0x000000FFU 1031 #define LP_UART_TX_BRK_NUM_S 0 1032 1033 /** LP_UART_IDLE_CONF_SYNC_REG register 1034 * Frame-end idle configuration 1035 */ 1036 #define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48) 1037 /** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; 1038 * It will produce frame end signal when receiver takes more time to receive one byte 1039 * data than this register value. 1040 */ 1041 #define LP_UART_RX_IDLE_THRHD 0x000003FFU 1042 #define LP_UART_RX_IDLE_THRHD_M (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S) 1043 #define LP_UART_RX_IDLE_THRHD_V 0x000003FFU 1044 #define LP_UART_RX_IDLE_THRHD_S 0 1045 /** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; 1046 * This register is used to configure the duration time between transfers. 1047 */ 1048 #define LP_UART_TX_IDLE_NUM 0x000003FFU 1049 #define LP_UART_TX_IDLE_NUM_M (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S) 1050 #define LP_UART_TX_IDLE_NUM_V 0x000003FFU 1051 #define LP_UART_TX_IDLE_NUM_S 10 1052 1053 /** LP_UART_RS485_CONF_SYNC_REG register 1054 * RS485 mode configuration 1055 */ 1056 #define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c) 1057 /** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0; 1058 * Set this bit to delay the stop bit by 1 bit. 1059 */ 1060 #define LP_UART_DL0_EN (BIT(1)) 1061 #define LP_UART_DL0_EN_M (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S) 1062 #define LP_UART_DL0_EN_V 0x00000001U 1063 #define LP_UART_DL0_EN_S 1 1064 /** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0; 1065 * Set this bit to delay the stop bit by 1 bit. 1066 */ 1067 #define LP_UART_DL1_EN (BIT(2)) 1068 #define LP_UART_DL1_EN_M (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S) 1069 #define LP_UART_DL1_EN_V 0x00000001U 1070 #define LP_UART_DL1_EN_S 2 1071 1072 /** LP_UART_AT_CMD_PRECNT_SYNC_REG register 1073 * Pre-sequence timing configuration 1074 */ 1075 #define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50) 1076 /** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; 1077 * This register is used to configure the idle duration time before the first at_cmd 1078 * is received by receiver. 1079 */ 1080 #define LP_UART_PRE_IDLE_NUM 0x0000FFFFU 1081 #define LP_UART_PRE_IDLE_NUM_M (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S) 1082 #define LP_UART_PRE_IDLE_NUM_V 0x0000FFFFU 1083 #define LP_UART_PRE_IDLE_NUM_S 0 1084 1085 /** LP_UART_AT_CMD_POSTCNT_SYNC_REG register 1086 * Post-sequence timing configuration 1087 */ 1088 #define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54) 1089 /** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; 1090 * This register is used to configure the duration time between the last at_cmd and 1091 * the next data. 1092 */ 1093 #define LP_UART_POST_IDLE_NUM 0x0000FFFFU 1094 #define LP_UART_POST_IDLE_NUM_M (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S) 1095 #define LP_UART_POST_IDLE_NUM_V 0x0000FFFFU 1096 #define LP_UART_POST_IDLE_NUM_S 0 1097 1098 /** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register 1099 * Timeout configuration 1100 */ 1101 #define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58) 1102 /** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; 1103 * This register is used to configure the duration time between the at_cmd chars. 1104 */ 1105 #define LP_UART_RX_GAP_TOUT 0x0000FFFFU 1106 #define LP_UART_RX_GAP_TOUT_M (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S) 1107 #define LP_UART_RX_GAP_TOUT_V 0x0000FFFFU 1108 #define LP_UART_RX_GAP_TOUT_S 0 1109 1110 /** LP_UART_AT_CMD_CHAR_SYNC_REG register 1111 * AT escape sequence detection configuration 1112 */ 1113 #define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c) 1114 /** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; 1115 * This register is used to configure the content of at_cmd char. 1116 */ 1117 #define LP_UART_AT_CMD_CHAR 0x000000FFU 1118 #define LP_UART_AT_CMD_CHAR_M (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S) 1119 #define LP_UART_AT_CMD_CHAR_V 0x000000FFU 1120 #define LP_UART_AT_CMD_CHAR_S 0 1121 /** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; 1122 * This register is used to configure the num of continuous at_cmd chars received by 1123 * receiver. 1124 */ 1125 #define LP_UART_CHAR_NUM 0x000000FFU 1126 #define LP_UART_CHAR_NUM_M (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S) 1127 #define LP_UART_CHAR_NUM_V 0x000000FFU 1128 #define LP_UART_CHAR_NUM_S 8 1129 1130 /** LP_UART_MEM_CONF_REG register 1131 * UART memory power configuration 1132 */ 1133 #define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60) 1134 /** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; 1135 * Set this bit to force power down UART memory. 1136 */ 1137 #define LP_UART_MEM_FORCE_PD (BIT(25)) 1138 #define LP_UART_MEM_FORCE_PD_M (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S) 1139 #define LP_UART_MEM_FORCE_PD_V 0x00000001U 1140 #define LP_UART_MEM_FORCE_PD_S 25 1141 /** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; 1142 * Set this bit to force power up UART memory. 1143 */ 1144 #define LP_UART_MEM_FORCE_PU (BIT(26)) 1145 #define LP_UART_MEM_FORCE_PU_M (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S) 1146 #define LP_UART_MEM_FORCE_PU_V 0x00000001U 1147 #define LP_UART_MEM_FORCE_PU_S 26 1148 1149 /** LP_UART_TOUT_CONF_SYNC_REG register 1150 * UART threshold and allocation configuration 1151 */ 1152 #define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) 1153 /** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; 1154 * This is the enble bit for uart receiver's timeout function. 1155 */ 1156 #define LP_UART_RX_TOUT_EN (BIT(0)) 1157 #define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) 1158 #define LP_UART_RX_TOUT_EN_V 0x00000001U 1159 #define LP_UART_RX_TOUT_EN_S 0 1160 /** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; 1161 * Set this bit to stop accumulating idle_cnt when hardware flow control works. 1162 */ 1163 #define LP_UART_RX_TOUT_FLOW_DIS (BIT(1)) 1164 #define LP_UART_RX_TOUT_FLOW_DIS_M (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S) 1165 #define LP_UART_RX_TOUT_FLOW_DIS_V 0x00000001U 1166 #define LP_UART_RX_TOUT_FLOW_DIS_S 1 1167 /** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; 1168 * This register is used to configure the threshold time that receiver takes to 1169 * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver 1170 * takes more time to receive one byte with rx_tout_en set to 1. 1171 */ 1172 #define LP_UART_RX_TOUT_THRHD 0x000003FFU 1173 #define LP_UART_RX_TOUT_THRHD_M (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S) 1174 #define LP_UART_RX_TOUT_THRHD_V 0x000003FFU 1175 #define LP_UART_RX_TOUT_THRHD_S 2 1176 1177 /** LP_UART_MEM_TX_STATUS_REG register 1178 * Tx-SRAM write and read offset address. 1179 */ 1180 #define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68) 1181 /** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0; 1182 * This register stores the offset write address in Tx-SRAM. 1183 */ 1184 #define LP_UART_TX_SRAM_WADDR 0x0000001FU 1185 #define LP_UART_TX_SRAM_WADDR_M (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S) 1186 #define LP_UART_TX_SRAM_WADDR_V 0x0000001FU 1187 #define LP_UART_TX_SRAM_WADDR_S 3 1188 /** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0; 1189 * This register stores the offset read address in Tx-SRAM. 1190 */ 1191 #define LP_UART_TX_SRAM_RADDR 0x0000001FU 1192 #define LP_UART_TX_SRAM_RADDR_M (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S) 1193 #define LP_UART_TX_SRAM_RADDR_V 0x0000001FU 1194 #define LP_UART_TX_SRAM_RADDR_S 12 1195 1196 /** LP_UART_MEM_RX_STATUS_REG register 1197 * Rx-SRAM write and read offset address. 1198 */ 1199 #define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c) 1200 /** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16; 1201 * This register stores the offset read address in RX-SRAM. 1202 */ 1203 #define LP_UART_RX_SRAM_RADDR 0x0000001FU 1204 #define LP_UART_RX_SRAM_RADDR_M (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S) 1205 #define LP_UART_RX_SRAM_RADDR_V 0x0000001FU 1206 #define LP_UART_RX_SRAM_RADDR_S 3 1207 /** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16; 1208 * This register stores the offset write address in Rx-SRAM. 1209 */ 1210 #define LP_UART_RX_SRAM_WADDR 0x0000001FU 1211 #define LP_UART_RX_SRAM_WADDR_M (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S) 1212 #define LP_UART_RX_SRAM_WADDR_V 0x0000001FU 1213 #define LP_UART_RX_SRAM_WADDR_S 12 1214 1215 /** LP_UART_FSM_STATUS_REG register 1216 * UART transmit and receive status. 1217 */ 1218 #define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70) 1219 /** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; 1220 * This is the status register of receiver. 1221 */ 1222 #define LP_UART_ST_URX_OUT 0x0000000FU 1223 #define LP_UART_ST_URX_OUT_M (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S) 1224 #define LP_UART_ST_URX_OUT_V 0x0000000FU 1225 #define LP_UART_ST_URX_OUT_S 0 1226 /** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; 1227 * This is the status register of transmitter. 1228 */ 1229 #define LP_UART_ST_UTX_OUT 0x0000000FU 1230 #define LP_UART_ST_UTX_OUT_M (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S) 1231 #define LP_UART_ST_UTX_OUT_V 0x0000000FU 1232 #define LP_UART_ST_UTX_OUT_S 4 1233 1234 /** LP_UART_CLK_CONF_REG register 1235 * UART core clock configuration 1236 */ 1237 #define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88) 1238 /** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; 1239 * The denominator of the frequency divider factor. 1240 */ 1241 #define LP_UART_SCLK_DIV_B 0x0000003FU 1242 #define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S) 1243 #define LP_UART_SCLK_DIV_B_V 0x0000003FU 1244 #define LP_UART_SCLK_DIV_B_S 0 1245 /** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; 1246 * The numerator of the frequency divider factor. 1247 */ 1248 #define LP_UART_SCLK_DIV_A 0x0000003FU 1249 #define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S) 1250 #define LP_UART_SCLK_DIV_A_V 0x0000003FU 1251 #define LP_UART_SCLK_DIV_A_S 6 1252 /** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; 1253 * The integral part of the frequency divider factor. 1254 */ 1255 #define LP_UART_SCLK_DIV_NUM 0x000000FFU 1256 #define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S) 1257 #define LP_UART_SCLK_DIV_NUM_V 0x000000FFU 1258 #define LP_UART_SCLK_DIV_NUM_S 12 1259 /** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; 1260 * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. 1261 */ 1262 #define LP_UART_SCLK_SEL 0x00000003U 1263 #define LP_UART_SCLK_SEL_M (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S) 1264 #define LP_UART_SCLK_SEL_V 0x00000003U 1265 #define LP_UART_SCLK_SEL_S 20 1266 /** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1; 1267 * Set this bit to enable UART Tx/Rx clock. 1268 */ 1269 #define LP_UART_SCLK_EN (BIT(22)) 1270 #define LP_UART_SCLK_EN_M (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S) 1271 #define LP_UART_SCLK_EN_V 0x00000001U 1272 #define LP_UART_SCLK_EN_S 22 1273 /** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0; 1274 * Write 1 then write 0 to this bit to reset UART Tx/Rx. 1275 */ 1276 #define LP_UART_RST_CORE (BIT(23)) 1277 #define LP_UART_RST_CORE_M (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S) 1278 #define LP_UART_RST_CORE_V 0x00000001U 1279 #define LP_UART_RST_CORE_S 23 1280 /** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; 1281 * Set this bit to enable UART Tx clock. 1282 */ 1283 #define LP_UART_TX_SCLK_EN (BIT(24)) 1284 #define LP_UART_TX_SCLK_EN_M (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S) 1285 #define LP_UART_TX_SCLK_EN_V 0x00000001U 1286 #define LP_UART_TX_SCLK_EN_S 24 1287 /** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; 1288 * Set this bit to enable UART Rx clock. 1289 */ 1290 #define LP_UART_RX_SCLK_EN (BIT(25)) 1291 #define LP_UART_RX_SCLK_EN_M (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S) 1292 #define LP_UART_RX_SCLK_EN_V 0x00000001U 1293 #define LP_UART_RX_SCLK_EN_S 25 1294 /** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; 1295 * Write 1 then write 0 to this bit to reset UART Tx. 1296 */ 1297 #define LP_UART_TX_RST_CORE (BIT(26)) 1298 #define LP_UART_TX_RST_CORE_M (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S) 1299 #define LP_UART_TX_RST_CORE_V 0x00000001U 1300 #define LP_UART_TX_RST_CORE_S 26 1301 /** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; 1302 * Write 1 then write 0 to this bit to reset UART Rx. 1303 */ 1304 #define LP_UART_RX_RST_CORE (BIT(27)) 1305 #define LP_UART_RX_RST_CORE_M (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S) 1306 #define LP_UART_RX_RST_CORE_V 0x00000001U 1307 #define LP_UART_RX_RST_CORE_S 27 1308 1309 /** LP_UART_DATE_REG register 1310 * UART Version register 1311 */ 1312 #define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c) 1313 /** LP_UART_DATE : R/W; bitpos: [31:0]; default: 35656288; 1314 * This is the version register. 1315 */ 1316 #define LP_UART_DATE 0xFFFFFFFFU 1317 #define LP_UART_DATE_M (LP_UART_DATE_V << LP_UART_DATE_S) 1318 #define LP_UART_DATE_V 0xFFFFFFFFU 1319 #define LP_UART_DATE_S 0 1320 1321 /** LP_UART_AFIFO_STATUS_REG register 1322 * UART AFIFO Status 1323 */ 1324 #define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90) 1325 /** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; 1326 * Full signal of APB TX AFIFO. 1327 */ 1328 #define LP_UART_TX_AFIFO_FULL (BIT(0)) 1329 #define LP_UART_TX_AFIFO_FULL_M (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S) 1330 #define LP_UART_TX_AFIFO_FULL_V 0x00000001U 1331 #define LP_UART_TX_AFIFO_FULL_S 0 1332 /** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; 1333 * Empty signal of APB TX AFIFO. 1334 */ 1335 #define LP_UART_TX_AFIFO_EMPTY (BIT(1)) 1336 #define LP_UART_TX_AFIFO_EMPTY_M (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S) 1337 #define LP_UART_TX_AFIFO_EMPTY_V 0x00000001U 1338 #define LP_UART_TX_AFIFO_EMPTY_S 1 1339 /** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; 1340 * Full signal of APB RX AFIFO. 1341 */ 1342 #define LP_UART_RX_AFIFO_FULL (BIT(2)) 1343 #define LP_UART_RX_AFIFO_FULL_M (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S) 1344 #define LP_UART_RX_AFIFO_FULL_V 0x00000001U 1345 #define LP_UART_RX_AFIFO_FULL_S 2 1346 /** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; 1347 * Empty signal of APB RX AFIFO. 1348 */ 1349 #define LP_UART_RX_AFIFO_EMPTY (BIT(3)) 1350 #define LP_UART_RX_AFIFO_EMPTY_M (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S) 1351 #define LP_UART_RX_AFIFO_EMPTY_V 0x00000001U 1352 #define LP_UART_RX_AFIFO_EMPTY_S 3 1353 1354 /** LP_UART_REG_UPDATE_REG register 1355 * UART Registers Configuration Update register 1356 */ 1357 #define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98) 1358 /** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; 1359 * Software write 1 would synchronize registers into UART Core clock domain and would 1360 * be cleared by hardware after synchronization is done. 1361 */ 1362 #define LP_UART_REG_UPDATE (BIT(0)) 1363 #define LP_UART_REG_UPDATE_M (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S) 1364 #define LP_UART_REG_UPDATE_V 0x00000001U 1365 #define LP_UART_REG_UPDATE_S 0 1366 1367 /** LP_UART_ID_REG register 1368 * UART ID register 1369 */ 1370 #define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c) 1371 /** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280; 1372 * This register is used to configure the uart_id. 1373 */ 1374 #define LP_UART_ID 0xFFFFFFFFU 1375 #define LP_UART_ID_M (LP_UART_ID_V << LP_UART_ID_S) 1376 #define LP_UART_ID_V 0xFFFFFFFFU 1377 #define LP_UART_ID_S 0 1378 1379 #ifdef __cplusplus 1380 } 1381 #endif 1382
