1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** LP_TIMER_TAR0_LOW_REG register 15 * need_des 16 */ 17 #define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) 18 /** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; 19 * need_des 20 */ 21 #define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU 22 #define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) 23 #define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU 24 #define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 25 26 /** LP_TIMER_TAR0_HIGH_REG register 27 * need_des 28 */ 29 #define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) 30 /** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; 31 * need_des 32 */ 33 #define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU 34 #define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) 35 #define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU 36 #define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 37 /** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; 38 * need_des 39 */ 40 #define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) 41 #define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) 42 #define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U 43 #define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 44 45 /** LP_TIMER_TAR1_LOW_REG register 46 * need_des 47 */ 48 #define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) 49 /** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; 50 * need_des 51 */ 52 #define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU 53 #define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) 54 #define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU 55 #define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 56 57 /** LP_TIMER_TAR1_HIGH_REG register 58 * need_des 59 */ 60 #define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) 61 /** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; 62 * need_des 63 */ 64 #define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU 65 #define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) 66 #define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU 67 #define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 68 /** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; 69 * need_des 70 */ 71 #define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) 72 #define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) 73 #define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U 74 #define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 75 76 /** LP_TIMER_UPDATE_REG register 77 * need_des 78 */ 79 #define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) 80 /** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; 81 * need_des 82 */ 83 #define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) 84 #define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) 85 #define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U 86 #define LP_TIMER_MAIN_TIMER_UPDATE_S 28 87 /** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; 88 * need_des 89 */ 90 #define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) 91 #define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) 92 #define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U 93 #define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 94 /** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; 95 * need_des 96 */ 97 #define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) 98 #define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) 99 #define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U 100 #define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 101 /** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; 102 * need_des 103 */ 104 #define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) 105 #define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) 106 #define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U 107 #define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 108 109 /** LP_TIMER_MAIN_BUF0_LOW_REG register 110 * need_des 111 */ 112 #define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) 113 /** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; 114 * need_des 115 */ 116 #define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU 117 #define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) 118 #define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU 119 #define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 120 121 /** LP_TIMER_MAIN_BUF0_HIGH_REG register 122 * need_des 123 */ 124 #define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) 125 /** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; 126 * need_des 127 */ 128 #define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU 129 #define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) 130 #define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU 131 #define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 132 133 /** LP_TIMER_MAIN_BUF1_LOW_REG register 134 * need_des 135 */ 136 #define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) 137 /** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; 138 * need_des 139 */ 140 #define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU 141 #define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) 142 #define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU 143 #define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 144 145 /** LP_TIMER_MAIN_BUF1_HIGH_REG register 146 * need_des 147 */ 148 #define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) 149 /** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; 150 * need_des 151 */ 152 #define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU 153 #define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) 154 #define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU 155 #define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 156 157 /** LP_TIMER_MAIN_OVERFLOW_REG register 158 * need_des 159 */ 160 #define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) 161 /** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; 162 * need_des 163 */ 164 #define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) 165 #define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) 166 #define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U 167 #define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 168 169 /** LP_TIMER_INT_RAW_REG register 170 * need_des 171 */ 172 #define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) 173 /** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; 174 * need_des 175 */ 176 #define LP_TIMER_OVERFLOW_RAW (BIT(30)) 177 #define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) 178 #define LP_TIMER_OVERFLOW_RAW_V 0x00000001U 179 #define LP_TIMER_OVERFLOW_RAW_S 30 180 /** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; 181 * need_des 182 */ 183 #define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) 184 #define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) 185 #define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U 186 #define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 187 188 /** LP_TIMER_INT_ST_REG register 189 * need_des 190 */ 191 #define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) 192 /** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; 193 * need_des 194 */ 195 #define LP_TIMER_OVERFLOW_ST (BIT(30)) 196 #define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) 197 #define LP_TIMER_OVERFLOW_ST_V 0x00000001U 198 #define LP_TIMER_OVERFLOW_ST_S 30 199 /** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; 200 * need_des 201 */ 202 #define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) 203 #define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) 204 #define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U 205 #define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 206 207 /** LP_TIMER_INT_ENA_REG register 208 * need_des 209 */ 210 #define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) 211 /** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; 212 * need_des 213 */ 214 #define LP_TIMER_OVERFLOW_ENA (BIT(30)) 215 #define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) 216 #define LP_TIMER_OVERFLOW_ENA_V 0x00000001U 217 #define LP_TIMER_OVERFLOW_ENA_S 30 218 /** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; 219 * need_des 220 */ 221 #define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) 222 #define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) 223 #define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U 224 #define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 225 226 /** LP_TIMER_INT_CLR_REG register 227 * need_des 228 */ 229 #define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) 230 /** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; 231 * need_des 232 */ 233 #define LP_TIMER_OVERFLOW_CLR (BIT(30)) 234 #define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) 235 #define LP_TIMER_OVERFLOW_CLR_V 0x00000001U 236 #define LP_TIMER_OVERFLOW_CLR_S 30 237 /** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; 238 * need_des 239 */ 240 #define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) 241 #define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) 242 #define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U 243 #define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 244 245 /** LP_TIMER_LP_INT_RAW_REG register 246 * need_des 247 */ 248 #define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) 249 /** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; 250 * need_des 251 */ 252 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) 253 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) 254 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U 255 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 256 /** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; 257 * need_des 258 */ 259 #define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) 260 #define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) 261 #define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U 262 #define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 263 264 /** LP_TIMER_LP_INT_ST_REG register 265 * need_des 266 */ 267 #define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) 268 /** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; 269 * need_des 270 */ 271 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) 272 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) 273 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U 274 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 275 /** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; 276 * need_des 277 */ 278 #define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) 279 #define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) 280 #define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U 281 #define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 282 283 /** LP_TIMER_LP_INT_ENA_REG register 284 * need_des 285 */ 286 #define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) 287 /** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; 288 * need_des 289 */ 290 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) 291 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) 292 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U 293 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 294 /** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; 295 * need_des 296 */ 297 #define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) 298 #define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) 299 #define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U 300 #define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 301 302 /** LP_TIMER_LP_INT_CLR_REG register 303 * need_des 304 */ 305 #define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) 306 /** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; 307 * need_des 308 */ 309 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) 310 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) 311 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U 312 #define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 313 /** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; 314 * need_des 315 */ 316 #define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) 317 #define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) 318 #define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U 319 #define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 320 321 /** LP_TIMER_DATE_REG register 322 * need_des 323 */ 324 #define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) 325 /** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; 326 * need_des 327 */ 328 #define LP_TIMER_DATE 0x7FFFFFFFU 329 #define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) 330 #define LP_TIMER_DATE_V 0x7FFFFFFFU 331 #define LP_TIMER_DATE_S 0 332 /** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; 333 * need_des 334 */ 335 #define LP_TIMER_CLK_EN (BIT(31)) 336 #define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) 337 #define LP_TIMER_CLK_EN_V 0x00000001U 338 #define LP_TIMER_CLK_EN_S 31 339 340 #ifdef __cplusplus 341 } 342 #endif 343
