1 /* 2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** LCD_CAM_LCD_CLOCK_REG register 15 * LCD clock register 16 */ 17 #define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x0) 18 /** LCD_CAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3; 19 * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. 20 */ 21 #define LCD_CAM_LCD_CLKCNT_N 0x0000003FU 22 #define LCD_CAM_LCD_CLKCNT_N_M (LCD_CAM_LCD_CLKCNT_N_V << LCD_CAM_LCD_CLKCNT_N_S) 23 #define LCD_CAM_LCD_CLKCNT_N_V 0x0000003FU 24 #define LCD_CAM_LCD_CLKCNT_N_S 0 25 /** LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1; 26 * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). 27 */ 28 #define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6)) 29 #define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (LCD_CAM_LCD_CLK_EQU_SYSCLK_V << LCD_CAM_LCD_CLK_EQU_SYSCLK_S) 30 #define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x00000001U 31 #define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6 32 /** LCD_CAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0; 33 * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. 34 */ 35 #define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7)) 36 #define LCD_CAM_LCD_CK_IDLE_EDGE_M (LCD_CAM_LCD_CK_IDLE_EDGE_V << LCD_CAM_LCD_CK_IDLE_EDGE_S) 37 #define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x00000001U 38 #define LCD_CAM_LCD_CK_IDLE_EDGE_S 7 39 /** LCD_CAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0; 40 * 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock 41 * cycle. 42 */ 43 #define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8)) 44 #define LCD_CAM_LCD_CK_OUT_EDGE_M (LCD_CAM_LCD_CK_OUT_EDGE_V << LCD_CAM_LCD_CK_OUT_EDGE_S) 45 #define LCD_CAM_LCD_CK_OUT_EDGE_V 0x00000001U 46 #define LCD_CAM_LCD_CK_OUT_EDGE_S 8 47 /** LCD_CAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; 48 * Integral LCD clock divider value 49 */ 50 #define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FFU 51 #define LCD_CAM_LCD_CLKM_DIV_NUM_M (LCD_CAM_LCD_CLKM_DIV_NUM_V << LCD_CAM_LCD_CLKM_DIV_NUM_S) 52 #define LCD_CAM_LCD_CLKM_DIV_NUM_V 0x000000FFU 53 #define LCD_CAM_LCD_CLKM_DIV_NUM_S 9 54 /** LCD_CAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; 55 * Fractional clock divider numerator value 56 */ 57 #define LCD_CAM_LCD_CLKM_DIV_B 0x0000003FU 58 #define LCD_CAM_LCD_CLKM_DIV_B_M (LCD_CAM_LCD_CLKM_DIV_B_V << LCD_CAM_LCD_CLKM_DIV_B_S) 59 #define LCD_CAM_LCD_CLKM_DIV_B_V 0x0000003FU 60 #define LCD_CAM_LCD_CLKM_DIV_B_S 17 61 /** LCD_CAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; 62 * Fractional clock divider denominator value 63 */ 64 #define LCD_CAM_LCD_CLKM_DIV_A 0x0000003FU 65 #define LCD_CAM_LCD_CLKM_DIV_A_M (LCD_CAM_LCD_CLKM_DIV_A_V << LCD_CAM_LCD_CLKM_DIV_A_S) 66 #define LCD_CAM_LCD_CLKM_DIV_A_V 0x0000003FU 67 #define LCD_CAM_LCD_CLKM_DIV_A_S 23 68 /** LCD_CAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0; 69 * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. 70 */ 71 #define LCD_CAM_LCD_CLK_SEL 0x00000003U 72 #define LCD_CAM_LCD_CLK_SEL_M (LCD_CAM_LCD_CLK_SEL_V << LCD_CAM_LCD_CLK_SEL_S) 73 #define LCD_CAM_LCD_CLK_SEL_V 0x00000003U 74 #define LCD_CAM_LCD_CLK_SEL_S 29 75 /** LCD_CAM_CLK_EN : R/W; bitpos: [31]; default: 0; 76 * Set this bit to enable clk gate 77 */ 78 #define LCD_CAM_CLK_EN (BIT(31)) 79 #define LCD_CAM_CLK_EN_M (LCD_CAM_CLK_EN_V << LCD_CAM_CLK_EN_S) 80 #define LCD_CAM_CLK_EN_V 0x00000001U 81 #define LCD_CAM_CLK_EN_S 31 82 83 /** LCD_CAM_CAM_CTRL_REG register 84 * Camera configuration register 85 */ 86 #define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x4) 87 /** LCD_CAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0; 88 * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. 89 */ 90 #define LCD_CAM_CAM_STOP_EN (BIT(0)) 91 #define LCD_CAM_CAM_STOP_EN_M (LCD_CAM_CAM_STOP_EN_V << LCD_CAM_CAM_STOP_EN_S) 92 #define LCD_CAM_CAM_STOP_EN_V 0x00000001U 93 #define LCD_CAM_CAM_STOP_EN_S 0 94 /** LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0; 95 * Filter threshold value for CAM_VSYNC signal. 96 */ 97 #define LCD_CAM_CAM_VSYNC_FILTER_THRES 0x00000007U 98 #define LCD_CAM_CAM_VSYNC_FILTER_THRES_M (LCD_CAM_CAM_VSYNC_FILTER_THRES_V << LCD_CAM_CAM_VSYNC_FILTER_THRES_S) 99 #define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x00000007U 100 #define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1 101 /** LCD_CAM_CAM_UPDATE_REG : R/W; bitpos: [4]; default: 0; 102 * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. 103 */ 104 #define LCD_CAM_CAM_UPDATE_REG (BIT(4)) 105 #define LCD_CAM_CAM_UPDATE_REG_M (LCD_CAM_CAM_UPDATE_REG_V << LCD_CAM_CAM_UPDATE_REG_S) 106 #define LCD_CAM_CAM_UPDATE_REG_V 0x00000001U 107 #define LCD_CAM_CAM_UPDATE_REG_S 4 108 /** LCD_CAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0; 109 * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte 110 * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. 111 */ 112 #define LCD_CAM_CAM_BYTE_ORDER (BIT(5)) 113 #define LCD_CAM_CAM_BYTE_ORDER_M (LCD_CAM_CAM_BYTE_ORDER_V << LCD_CAM_CAM_BYTE_ORDER_S) 114 #define LCD_CAM_CAM_BYTE_ORDER_V 0x00000001U 115 #define LCD_CAM_CAM_BYTE_ORDER_S 5 116 /** LCD_CAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0; 117 * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. 118 */ 119 #define LCD_CAM_CAM_BIT_ORDER (BIT(6)) 120 #define LCD_CAM_CAM_BIT_ORDER_M (LCD_CAM_CAM_BIT_ORDER_V << LCD_CAM_CAM_BIT_ORDER_S) 121 #define LCD_CAM_CAM_BIT_ORDER_V 0x00000001U 122 #define LCD_CAM_CAM_BIT_ORDER_S 6 123 /** LCD_CAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0; 124 * 1: Enable to generate CAM_HS_INT. 0: Disable. 125 */ 126 #define LCD_CAM_CAM_LINE_INT_EN (BIT(7)) 127 #define LCD_CAM_CAM_LINE_INT_EN_M (LCD_CAM_CAM_LINE_INT_EN_V << LCD_CAM_CAM_LINE_INT_EN_S) 128 #define LCD_CAM_CAM_LINE_INT_EN_V 0x00000001U 129 #define LCD_CAM_CAM_LINE_INT_EN_S 7 130 /** LCD_CAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0; 131 * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by 132 * reg_cam_rec_data_cyclelen. 133 */ 134 #define LCD_CAM_CAM_VS_EOF_EN (BIT(8)) 135 #define LCD_CAM_CAM_VS_EOF_EN_M (LCD_CAM_CAM_VS_EOF_EN_V << LCD_CAM_CAM_VS_EOF_EN_S) 136 #define LCD_CAM_CAM_VS_EOF_EN_V 0x00000001U 137 #define LCD_CAM_CAM_VS_EOF_EN_S 8 138 /** LCD_CAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; 139 * Integral Camera clock divider value 140 */ 141 #define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FFU 142 #define LCD_CAM_CAM_CLKM_DIV_NUM_M (LCD_CAM_CAM_CLKM_DIV_NUM_V << LCD_CAM_CAM_CLKM_DIV_NUM_S) 143 #define LCD_CAM_CAM_CLKM_DIV_NUM_V 0x000000FFU 144 #define LCD_CAM_CAM_CLKM_DIV_NUM_S 9 145 /** LCD_CAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; 146 * Fractional clock divider numerator value 147 */ 148 #define LCD_CAM_CAM_CLKM_DIV_B 0x0000003FU 149 #define LCD_CAM_CAM_CLKM_DIV_B_M (LCD_CAM_CAM_CLKM_DIV_B_V << LCD_CAM_CAM_CLKM_DIV_B_S) 150 #define LCD_CAM_CAM_CLKM_DIV_B_V 0x0000003FU 151 #define LCD_CAM_CAM_CLKM_DIV_B_S 17 152 /** LCD_CAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; 153 * Fractional clock divider denominator value 154 */ 155 #define LCD_CAM_CAM_CLKM_DIV_A 0x0000003FU 156 #define LCD_CAM_CAM_CLKM_DIV_A_M (LCD_CAM_CAM_CLKM_DIV_A_V << LCD_CAM_CAM_CLKM_DIV_A_S) 157 #define LCD_CAM_CAM_CLKM_DIV_A_V 0x0000003FU 158 #define LCD_CAM_CAM_CLKM_DIV_A_S 23 159 /** LCD_CAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0; 160 * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. 161 */ 162 #define LCD_CAM_CAM_CLK_SEL 0x00000003U 163 #define LCD_CAM_CAM_CLK_SEL_M (LCD_CAM_CAM_CLK_SEL_V << LCD_CAM_CAM_CLK_SEL_S) 164 #define LCD_CAM_CAM_CLK_SEL_V 0x00000003U 165 #define LCD_CAM_CAM_CLK_SEL_S 29 166 167 /** LCD_CAM_CAM_CTRL1_REG register 168 * Camera configuration register 169 */ 170 #define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x8) 171 /** LCD_CAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0; 172 * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. 173 */ 174 #define LCD_CAM_CAM_REC_DATA_BYTELEN 0x0000FFFFU 175 #define LCD_CAM_CAM_REC_DATA_BYTELEN_M (LCD_CAM_CAM_REC_DATA_BYTELEN_V << LCD_CAM_CAM_REC_DATA_BYTELEN_S) 176 #define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0x0000FFFFU 177 #define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0 178 /** LCD_CAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0; 179 * The line number minus 1 to generate cam_hs_int. 180 */ 181 #define LCD_CAM_CAM_LINE_INT_NUM 0x0000003FU 182 #define LCD_CAM_CAM_LINE_INT_NUM_M (LCD_CAM_CAM_LINE_INT_NUM_V << LCD_CAM_CAM_LINE_INT_NUM_S) 183 #define LCD_CAM_CAM_LINE_INT_NUM_V 0x0000003FU 184 #define LCD_CAM_CAM_LINE_INT_NUM_S 16 185 /** LCD_CAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0; 186 * 1: Invert the input signal CAM_PCLK. 0: Not invert. 187 */ 188 #define LCD_CAM_CAM_CLK_INV (BIT(22)) 189 #define LCD_CAM_CAM_CLK_INV_M (LCD_CAM_CAM_CLK_INV_V << LCD_CAM_CAM_CLK_INV_S) 190 #define LCD_CAM_CAM_CLK_INV_V 0x00000001U 191 #define LCD_CAM_CAM_CLK_INV_S 22 192 /** LCD_CAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0; 193 * 1: Enable CAM_VSYNC filter function. 0: bypass. 194 */ 195 #define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23)) 196 #define LCD_CAM_CAM_VSYNC_FILTER_EN_M (LCD_CAM_CAM_VSYNC_FILTER_EN_V << LCD_CAM_CAM_VSYNC_FILTER_EN_S) 197 #define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x00000001U 198 #define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23 199 /** LCD_CAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0; 200 * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. 201 */ 202 #define LCD_CAM_CAM_2BYTE_EN (BIT(24)) 203 #define LCD_CAM_CAM_2BYTE_EN_M (LCD_CAM_CAM_2BYTE_EN_V << LCD_CAM_CAM_2BYTE_EN_S) 204 #define LCD_CAM_CAM_2BYTE_EN_V 0x00000001U 205 #define LCD_CAM_CAM_2BYTE_EN_S 24 206 /** LCD_CAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0; 207 * CAM_DE invert enable signal, valid in high level. 208 */ 209 #define LCD_CAM_CAM_DE_INV (BIT(25)) 210 #define LCD_CAM_CAM_DE_INV_M (LCD_CAM_CAM_DE_INV_V << LCD_CAM_CAM_DE_INV_S) 211 #define LCD_CAM_CAM_DE_INV_V 0x00000001U 212 #define LCD_CAM_CAM_DE_INV_S 25 213 /** LCD_CAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0; 214 * CAM_HSYNC invert enable signal, valid in high level. 215 */ 216 #define LCD_CAM_CAM_HSYNC_INV (BIT(26)) 217 #define LCD_CAM_CAM_HSYNC_INV_M (LCD_CAM_CAM_HSYNC_INV_V << LCD_CAM_CAM_HSYNC_INV_S) 218 #define LCD_CAM_CAM_HSYNC_INV_V 0x00000001U 219 #define LCD_CAM_CAM_HSYNC_INV_S 26 220 /** LCD_CAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0; 221 * CAM_VSYNC invert enable signal, valid in high level. 222 */ 223 #define LCD_CAM_CAM_VSYNC_INV (BIT(27)) 224 #define LCD_CAM_CAM_VSYNC_INV_M (LCD_CAM_CAM_VSYNC_INV_V << LCD_CAM_CAM_VSYNC_INV_S) 225 #define LCD_CAM_CAM_VSYNC_INV_V 0x00000001U 226 #define LCD_CAM_CAM_VSYNC_INV_S 27 227 /** LCD_CAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0; 228 * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control 229 * signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. 230 */ 231 #define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28)) 232 #define LCD_CAM_CAM_VH_DE_MODE_EN_M (LCD_CAM_CAM_VH_DE_MODE_EN_V << LCD_CAM_CAM_VH_DE_MODE_EN_S) 233 #define LCD_CAM_CAM_VH_DE_MODE_EN_V 0x00000001U 234 #define LCD_CAM_CAM_VH_DE_MODE_EN_S 28 235 /** LCD_CAM_CAM_START : R/W; bitpos: [29]; default: 0; 236 * Camera module start signal. 237 */ 238 #define LCD_CAM_CAM_START (BIT(29)) 239 #define LCD_CAM_CAM_START_M (LCD_CAM_CAM_START_V << LCD_CAM_CAM_START_S) 240 #define LCD_CAM_CAM_START_V 0x00000001U 241 #define LCD_CAM_CAM_START_S 29 242 /** LCD_CAM_CAM_RESET : WO; bitpos: [30]; default: 0; 243 * Camera module reset signal. 244 */ 245 #define LCD_CAM_CAM_RESET (BIT(30)) 246 #define LCD_CAM_CAM_RESET_M (LCD_CAM_CAM_RESET_V << LCD_CAM_CAM_RESET_S) 247 #define LCD_CAM_CAM_RESET_V 0x00000001U 248 #define LCD_CAM_CAM_RESET_S 30 249 /** LCD_CAM_CAM_AFIFO_RESET : WO; bitpos: [31]; default: 0; 250 * Camera AFIFO reset signal. 251 */ 252 #define LCD_CAM_CAM_AFIFO_RESET (BIT(31)) 253 #define LCD_CAM_CAM_AFIFO_RESET_M (LCD_CAM_CAM_AFIFO_RESET_V << LCD_CAM_CAM_AFIFO_RESET_S) 254 #define LCD_CAM_CAM_AFIFO_RESET_V 0x00000001U 255 #define LCD_CAM_CAM_AFIFO_RESET_S 31 256 257 /** LCD_CAM_CAM_RGB_YUV_REG register 258 * Camera configuration register 259 */ 260 #define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0xc) 261 /** LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0; 262 * 1:invert every two 8bits input data. 2. disabled. 263 */ 264 #define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) 265 #define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (LCD_CAM_CAM_CONV_8BITS_DATA_INV_V << LCD_CAM_CAM_CONV_8BITS_DATA_INV_S) 266 #define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x00000001U 267 #define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21 268 /** LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; 269 * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, 270 * trans_mode must be set to 1. 271 */ 272 #define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003U 273 #define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M (LCD_CAM_CAM_CONV_YUV2YUV_MODE_V << LCD_CAM_CAM_CONV_YUV2YUV_MODE_S) 274 #define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x00000003U 275 #define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22 276 /** LCD_CAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; 277 * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv 278 * mode of Data_in 279 */ 280 #define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003U 281 #define LCD_CAM_CAM_CONV_YUV_MODE_M (LCD_CAM_CAM_CONV_YUV_MODE_V << LCD_CAM_CAM_CONV_YUV_MODE_S) 282 #define LCD_CAM_CAM_CONV_YUV_MODE_V 0x00000003U 283 #define LCD_CAM_CAM_CONV_YUV_MODE_S 24 284 /** LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; 285 * 0:BT601. 1:BT709. 286 */ 287 #define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) 288 #define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (LCD_CAM_CAM_CONV_PROTOCOL_MODE_V << LCD_CAM_CAM_CONV_PROTOCOL_MODE_S) 289 #define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x00000001U 290 #define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26 291 /** LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; 292 * LIMIT or FULL mode of Data out. 0: limit. 1: full 293 */ 294 #define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) 295 #define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (LCD_CAM_CAM_CONV_DATA_OUT_MODE_V << LCD_CAM_CAM_CONV_DATA_OUT_MODE_S) 296 #define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x00000001U 297 #define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27 298 /** LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; 299 * LIMIT or FULL mode of Data in. 0: limit. 1: full 300 */ 301 #define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28)) 302 #define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (LCD_CAM_CAM_CONV_DATA_IN_MODE_V << LCD_CAM_CAM_CONV_DATA_IN_MODE_S) 303 #define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x00000001U 304 #define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28 305 /** LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; 306 * 0: 16bits mode. 1: 8bits mode. 307 */ 308 #define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) 309 #define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (LCD_CAM_CAM_CONV_MODE_8BITS_ON_V << LCD_CAM_CAM_CONV_MODE_8BITS_ON_S) 310 #define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x00000001U 311 #define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29 312 /** LCD_CAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; 313 * 0: YUV to RGB. 1: RGB to YUV. 314 */ 315 #define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30)) 316 #define LCD_CAM_CAM_CONV_TRANS_MODE_M (LCD_CAM_CAM_CONV_TRANS_MODE_V << LCD_CAM_CAM_CONV_TRANS_MODE_S) 317 #define LCD_CAM_CAM_CONV_TRANS_MODE_V 0x00000001U 318 #define LCD_CAM_CAM_CONV_TRANS_MODE_S 30 319 /** LCD_CAM_CAM_CONV_BYPASS : R/W; bitpos: [31]; default: 0; 320 * 0: Bypass converter. 1: Enable converter. 321 */ 322 #define LCD_CAM_CAM_CONV_BYPASS (BIT(31)) 323 #define LCD_CAM_CAM_CONV_BYPASS_M (LCD_CAM_CAM_CONV_BYPASS_V << LCD_CAM_CAM_CONV_BYPASS_S) 324 #define LCD_CAM_CAM_CONV_BYPASS_V 0x00000001U 325 #define LCD_CAM_CAM_CONV_BYPASS_S 31 326 327 /** LCD_CAM_LCD_RGB_YUV_REG register 328 * LCD configuration register 329 */ 330 #define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x10) 331 /** LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0; 332 * 1:invert every two 8bits input data. 2. disabled. 333 */ 334 #define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) 335 #define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (LCD_CAM_LCD_CONV_8BITS_DATA_INV_V << LCD_CAM_LCD_CONV_8BITS_DATA_INV_S) 336 #define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V 0x00000001U 337 #define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S 20 338 /** LCD_CAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0; 339 * 0: txtorx mode off. 1: txtorx mode on. 340 */ 341 #define LCD_CAM_LCD_CONV_TXTORX (BIT(21)) 342 #define LCD_CAM_LCD_CONV_TXTORX_M (LCD_CAM_LCD_CONV_TXTORX_V << LCD_CAM_LCD_CONV_TXTORX_S) 343 #define LCD_CAM_LCD_CONV_TXTORX_V 0x00000001U 344 #define LCD_CAM_LCD_CONV_TXTORX_S 21 345 /** LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; 346 * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, 347 * trans_mode must be set to 1. 348 */ 349 #define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003U 350 #define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M (LCD_CAM_LCD_CONV_YUV2YUV_MODE_V << LCD_CAM_LCD_CONV_YUV2YUV_MODE_S) 351 #define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x00000003U 352 #define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22 353 /** LCD_CAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; 354 * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv 355 * mode of Data_in 356 */ 357 #define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003U 358 #define LCD_CAM_LCD_CONV_YUV_MODE_M (LCD_CAM_LCD_CONV_YUV_MODE_V << LCD_CAM_LCD_CONV_YUV_MODE_S) 359 #define LCD_CAM_LCD_CONV_YUV_MODE_V 0x00000003U 360 #define LCD_CAM_LCD_CONV_YUV_MODE_S 24 361 /** LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; 362 * 0:BT601. 1:BT709. 363 */ 364 #define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) 365 #define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (LCD_CAM_LCD_CONV_PROTOCOL_MODE_V << LCD_CAM_LCD_CONV_PROTOCOL_MODE_S) 366 #define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x00000001U 367 #define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26 368 /** LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; 369 * LIMIT or FULL mode of Data out. 0: limit. 1: full 370 */ 371 #define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) 372 #define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (LCD_CAM_LCD_CONV_DATA_OUT_MODE_V << LCD_CAM_LCD_CONV_DATA_OUT_MODE_S) 373 #define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x00000001U 374 #define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27 375 /** LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; 376 * LIMIT or FULL mode of Data in. 0: limit. 1: full 377 */ 378 #define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28)) 379 #define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (LCD_CAM_LCD_CONV_DATA_IN_MODE_V << LCD_CAM_LCD_CONV_DATA_IN_MODE_S) 380 #define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x00000001U 381 #define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28 382 /** LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; 383 * 0: 16bits mode. 1: 8bits mode. 384 */ 385 #define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) 386 #define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (LCD_CAM_LCD_CONV_MODE_8BITS_ON_V << LCD_CAM_LCD_CONV_MODE_8BITS_ON_S) 387 #define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x00000001U 388 #define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29 389 /** LCD_CAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; 390 * 0: YUV to RGB. 1: RGB to YUV. 391 */ 392 #define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30)) 393 #define LCD_CAM_LCD_CONV_TRANS_MODE_M (LCD_CAM_LCD_CONV_TRANS_MODE_V << LCD_CAM_LCD_CONV_TRANS_MODE_S) 394 #define LCD_CAM_LCD_CONV_TRANS_MODE_V 0x00000001U 395 #define LCD_CAM_LCD_CONV_TRANS_MODE_S 30 396 /** LCD_CAM_LCD_CONV_BYPASS : R/W; bitpos: [31]; default: 0; 397 * 0: Bypass converter. 1: Enable converter. 398 */ 399 #define LCD_CAM_LCD_CONV_BYPASS (BIT(31)) 400 #define LCD_CAM_LCD_CONV_BYPASS_M (LCD_CAM_LCD_CONV_BYPASS_V << LCD_CAM_LCD_CONV_BYPASS_S) 401 #define LCD_CAM_LCD_CONV_BYPASS_V 0x00000001U 402 #define LCD_CAM_LCD_CONV_BYPASS_S 31 403 404 /** LCD_CAM_LCD_USER_REG register 405 * LCD configuration register 406 */ 407 #define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x14) 408 /** LCD_CAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1; 409 * The output data cycles minus 1 of LCD module. 410 */ 411 #define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFFU 412 #define LCD_CAM_LCD_DOUT_CYCLELEN_M (LCD_CAM_LCD_DOUT_CYCLELEN_V << LCD_CAM_LCD_DOUT_CYCLELEN_S) 413 #define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x00001FFFU 414 #define LCD_CAM_LCD_DOUT_CYCLELEN_S 0 415 /** LCD_CAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0; 416 * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or 417 * reg_lcd_reset is set. 418 */ 419 #define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13)) 420 #define LCD_CAM_LCD_ALWAYS_OUT_EN_M (LCD_CAM_LCD_ALWAYS_OUT_EN_V << LCD_CAM_LCD_ALWAYS_OUT_EN_S) 421 #define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x00000001U 422 #define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13 423 /** LCD_CAM_LCD_8BITS_ORDER : R/W; bitpos: [19]; default: 0; 424 * 1: invert every two data byte, valid in 1 byte mode. 0: Not change. 425 */ 426 #define LCD_CAM_LCD_8BITS_ORDER (BIT(19)) 427 #define LCD_CAM_LCD_8BITS_ORDER_M (LCD_CAM_LCD_8BITS_ORDER_V << LCD_CAM_LCD_8BITS_ORDER_S) 428 #define LCD_CAM_LCD_8BITS_ORDER_V 0x00000001U 429 #define LCD_CAM_LCD_8BITS_ORDER_S 19 430 /** LCD_CAM_LCD_UPDATE_REG : R/W; bitpos: [20]; default: 0; 431 * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. 432 */ 433 #define LCD_CAM_LCD_UPDATE_REG (BIT(20)) 434 #define LCD_CAM_LCD_UPDATE_REG_M (LCD_CAM_LCD_UPDATE_REG_V << LCD_CAM_LCD_UPDATE_REG_S) 435 #define LCD_CAM_LCD_UPDATE_REG_V 0x00000001U 436 #define LCD_CAM_LCD_UPDATE_REG_S 20 437 /** LCD_CAM_LCD_BIT_ORDER : R/W; bitpos: [21]; default: 0; 438 * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte 439 * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. 440 */ 441 #define LCD_CAM_LCD_BIT_ORDER (BIT(21)) 442 #define LCD_CAM_LCD_BIT_ORDER_M (LCD_CAM_LCD_BIT_ORDER_V << LCD_CAM_LCD_BIT_ORDER_S) 443 #define LCD_CAM_LCD_BIT_ORDER_V 0x00000001U 444 #define LCD_CAM_LCD_BIT_ORDER_S 21 445 /** LCD_CAM_LCD_BYTE_ORDER : R/W; bitpos: [22]; default: 0; 446 * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. 447 */ 448 #define LCD_CAM_LCD_BYTE_ORDER (BIT(22)) 449 #define LCD_CAM_LCD_BYTE_ORDER_M (LCD_CAM_LCD_BYTE_ORDER_V << LCD_CAM_LCD_BYTE_ORDER_S) 450 #define LCD_CAM_LCD_BYTE_ORDER_V 0x00000001U 451 #define LCD_CAM_LCD_BYTE_ORDER_S 22 452 /** LCD_CAM_LCD_2BYTE_EN : R/W; bitpos: [23]; default: 0; 453 * 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data 454 * is 0~8. 455 */ 456 #define LCD_CAM_LCD_2BYTE_EN (BIT(23)) 457 #define LCD_CAM_LCD_2BYTE_EN_M (LCD_CAM_LCD_2BYTE_EN_V << LCD_CAM_LCD_2BYTE_EN_S) 458 #define LCD_CAM_LCD_2BYTE_EN_V 0x00000001U 459 #define LCD_CAM_LCD_2BYTE_EN_S 23 460 /** LCD_CAM_LCD_DOUT : R/W; bitpos: [24]; default: 0; 461 * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. 462 */ 463 #define LCD_CAM_LCD_DOUT (BIT(24)) 464 #define LCD_CAM_LCD_DOUT_M (LCD_CAM_LCD_DOUT_V << LCD_CAM_LCD_DOUT_S) 465 #define LCD_CAM_LCD_DOUT_V 0x00000001U 466 #define LCD_CAM_LCD_DOUT_S 24 467 /** LCD_CAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0; 468 * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. 469 */ 470 #define LCD_CAM_LCD_DUMMY (BIT(25)) 471 #define LCD_CAM_LCD_DUMMY_M (LCD_CAM_LCD_DUMMY_V << LCD_CAM_LCD_DUMMY_S) 472 #define LCD_CAM_LCD_DUMMY_V 0x00000001U 473 #define LCD_CAM_LCD_DUMMY_S 25 474 /** LCD_CAM_LCD_CMD : R/W; bitpos: [26]; default: 0; 475 * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. 476 */ 477 #define LCD_CAM_LCD_CMD (BIT(26)) 478 #define LCD_CAM_LCD_CMD_M (LCD_CAM_LCD_CMD_V << LCD_CAM_LCD_CMD_S) 479 #define LCD_CAM_LCD_CMD_V 0x00000001U 480 #define LCD_CAM_LCD_CMD_S 26 481 /** LCD_CAM_LCD_START : R/W; bitpos: [27]; default: 0; 482 * LCD start sending data enable signal, valid in high level. 483 */ 484 #define LCD_CAM_LCD_START (BIT(27)) 485 #define LCD_CAM_LCD_START_M (LCD_CAM_LCD_START_V << LCD_CAM_LCD_START_S) 486 #define LCD_CAM_LCD_START_V 0x00000001U 487 #define LCD_CAM_LCD_START_S 27 488 /** LCD_CAM_LCD_RESET : WO; bitpos: [28]; default: 0; 489 * The value of command. 490 */ 491 #define LCD_CAM_LCD_RESET (BIT(28)) 492 #define LCD_CAM_LCD_RESET_M (LCD_CAM_LCD_RESET_V << LCD_CAM_LCD_RESET_S) 493 #define LCD_CAM_LCD_RESET_V 0x00000001U 494 #define LCD_CAM_LCD_RESET_S 28 495 /** LCD_CAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0; 496 * The dummy cycle length minus 1. 497 */ 498 #define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003U 499 #define LCD_CAM_LCD_DUMMY_CYCLELEN_M (LCD_CAM_LCD_DUMMY_CYCLELEN_V << LCD_CAM_LCD_DUMMY_CYCLELEN_S) 500 #define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x00000003U 501 #define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29 502 /** LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0; 503 * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. 504 */ 505 #define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31)) 506 #define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (LCD_CAM_LCD_CMD_2_CYCLE_EN_V << LCD_CAM_LCD_CMD_2_CYCLE_EN_S) 507 #define LCD_CAM_LCD_CMD_2_CYCLE_EN_V 0x00000001U 508 #define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31 509 510 /** LCD_CAM_LCD_MISC_REG register 511 * LCD configuration register 512 */ 513 #define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x18) 514 /** LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W; bitpos: [5:1]; default: 11; 515 * The awfull threshold number of lcd_afifo. 516 */ 517 #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM 0x0000001FU 518 #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M (LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V << LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S) 519 #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V 0x0000001FU 520 #define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S 1 521 /** LCD_CAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3; 522 * The setup cycle length minus 1 in LCD non-RGB mode. 523 */ 524 #define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003FU 525 #define LCD_CAM_LCD_VFK_CYCLELEN_M (LCD_CAM_LCD_VFK_CYCLELEN_V << LCD_CAM_LCD_VFK_CYCLELEN_S) 526 #define LCD_CAM_LCD_VFK_CYCLELEN_V 0x0000003FU 527 #define LCD_CAM_LCD_VFK_CYCLELEN_S 6 528 /** LCD_CAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0; 529 * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold 530 * time cycle length in LCD non-RGB mode. 531 */ 532 #define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFFU 533 #define LCD_CAM_LCD_VBK_CYCLELEN_M (LCD_CAM_LCD_VBK_CYCLELEN_V << LCD_CAM_LCD_VBK_CYCLELEN_S) 534 #define LCD_CAM_LCD_VBK_CYCLELEN_V 0x00001FFFU 535 #define LCD_CAM_LCD_VBK_CYCLELEN_S 12 536 /** LCD_CAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0; 537 * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when 538 * the current frame is sent out. 539 */ 540 #define LCD_CAM_LCD_NEXT_FRAME_EN (BIT(25)) 541 #define LCD_CAM_LCD_NEXT_FRAME_EN_M (LCD_CAM_LCD_NEXT_FRAME_EN_V << LCD_CAM_LCD_NEXT_FRAME_EN_S) 542 #define LCD_CAM_LCD_NEXT_FRAME_EN_V 0x00000001U 543 #define LCD_CAM_LCD_NEXT_FRAME_EN_S 25 544 /** LCD_CAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0; 545 * 1: Enable blank region when LCD sends data out. 0: No blank region. 546 */ 547 #define LCD_CAM_LCD_BK_EN (BIT(26)) 548 #define LCD_CAM_LCD_BK_EN_M (LCD_CAM_LCD_BK_EN_V << LCD_CAM_LCD_BK_EN_S) 549 #define LCD_CAM_LCD_BK_EN_V 0x00000001U 550 #define LCD_CAM_LCD_BK_EN_S 26 551 /** LCD_CAM_LCD_AFIFO_RESET : WO; bitpos: [27]; default: 0; 552 * LCD AFIFO reset signal. 553 */ 554 #define LCD_CAM_LCD_AFIFO_RESET (BIT(27)) 555 #define LCD_CAM_LCD_AFIFO_RESET_M (LCD_CAM_LCD_AFIFO_RESET_V << LCD_CAM_LCD_AFIFO_RESET_S) 556 #define LCD_CAM_LCD_AFIFO_RESET_V 0x00000001U 557 #define LCD_CAM_LCD_AFIFO_RESET_S 27 558 /** LCD_CAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0; 559 * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = 560 * reg_cd_idle_edge. 561 */ 562 #define LCD_CAM_LCD_CD_DATA_SET (BIT(28)) 563 #define LCD_CAM_LCD_CD_DATA_SET_M (LCD_CAM_LCD_CD_DATA_SET_V << LCD_CAM_LCD_CD_DATA_SET_S) 564 #define LCD_CAM_LCD_CD_DATA_SET_V 0x00000001U 565 #define LCD_CAM_LCD_CD_DATA_SET_S 28 566 /** LCD_CAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0; 567 * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = 568 * reg_cd_idle_edge. 569 */ 570 #define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29)) 571 #define LCD_CAM_LCD_CD_DUMMY_SET_M (LCD_CAM_LCD_CD_DUMMY_SET_V << LCD_CAM_LCD_CD_DUMMY_SET_S) 572 #define LCD_CAM_LCD_CD_DUMMY_SET_V 0x00000001U 573 #define LCD_CAM_LCD_CD_DUMMY_SET_S 29 574 /** LCD_CAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0; 575 * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = 576 * reg_cd_idle_edge. 577 */ 578 #define LCD_CAM_LCD_CD_CMD_SET (BIT(30)) 579 #define LCD_CAM_LCD_CD_CMD_SET_M (LCD_CAM_LCD_CD_CMD_SET_V << LCD_CAM_LCD_CD_CMD_SET_S) 580 #define LCD_CAM_LCD_CD_CMD_SET_V 0x00000001U 581 #define LCD_CAM_LCD_CD_CMD_SET_S 30 582 /** LCD_CAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0; 583 * The default value of LCD_CD. 584 */ 585 #define LCD_CAM_LCD_CD_IDLE_EDGE (BIT(31)) 586 #define LCD_CAM_LCD_CD_IDLE_EDGE_M (LCD_CAM_LCD_CD_IDLE_EDGE_V << LCD_CAM_LCD_CD_IDLE_EDGE_S) 587 #define LCD_CAM_LCD_CD_IDLE_EDGE_V 0x00000001U 588 #define LCD_CAM_LCD_CD_IDLE_EDGE_S 31 589 590 /** LCD_CAM_LCD_CTRL_REG register 591 * LCD configuration register 592 */ 593 #define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x1c) 594 /** LCD_CAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0; 595 * It is the horizontal blank front porch of a frame. 596 */ 597 #define LCD_CAM_LCD_HB_FRONT 0x000007FFU 598 #define LCD_CAM_LCD_HB_FRONT_M (LCD_CAM_LCD_HB_FRONT_V << LCD_CAM_LCD_HB_FRONT_S) 599 #define LCD_CAM_LCD_HB_FRONT_V 0x000007FFU 600 #define LCD_CAM_LCD_HB_FRONT_S 0 601 /** LCD_CAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0; 602 * It is the vertical active height of a frame. 603 */ 604 #define LCD_CAM_LCD_VA_HEIGHT 0x000003FFU 605 #define LCD_CAM_LCD_VA_HEIGHT_M (LCD_CAM_LCD_VA_HEIGHT_V << LCD_CAM_LCD_VA_HEIGHT_S) 606 #define LCD_CAM_LCD_VA_HEIGHT_V 0x000003FFU 607 #define LCD_CAM_LCD_VA_HEIGHT_S 11 608 /** LCD_CAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0; 609 * It is the vertical total height of a frame. 610 */ 611 #define LCD_CAM_LCD_VT_HEIGHT 0x000003FFU 612 #define LCD_CAM_LCD_VT_HEIGHT_M (LCD_CAM_LCD_VT_HEIGHT_V << LCD_CAM_LCD_VT_HEIGHT_S) 613 #define LCD_CAM_LCD_VT_HEIGHT_V 0x000003FFU 614 #define LCD_CAM_LCD_VT_HEIGHT_S 21 615 /** LCD_CAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0; 616 * 1: Enable reg mode input vsync, hsync, de. 0: Disable. 617 */ 618 #define LCD_CAM_LCD_RGB_MODE_EN (BIT(31)) 619 #define LCD_CAM_LCD_RGB_MODE_EN_M (LCD_CAM_LCD_RGB_MODE_EN_V << LCD_CAM_LCD_RGB_MODE_EN_S) 620 #define LCD_CAM_LCD_RGB_MODE_EN_V 0x00000001U 621 #define LCD_CAM_LCD_RGB_MODE_EN_S 31 622 623 /** LCD_CAM_LCD_CTRL1_REG register 624 * LCD configuration register 625 */ 626 #define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x20) 627 /** LCD_CAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0; 628 * It is the vertical blank front porch of a frame. 629 */ 630 #define LCD_CAM_LCD_VB_FRONT 0x000000FFU 631 #define LCD_CAM_LCD_VB_FRONT_M (LCD_CAM_LCD_VB_FRONT_V << LCD_CAM_LCD_VB_FRONT_S) 632 #define LCD_CAM_LCD_VB_FRONT_V 0x000000FFU 633 #define LCD_CAM_LCD_VB_FRONT_S 0 634 /** LCD_CAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0; 635 * It is the horizontal active width of a frame. 636 */ 637 #define LCD_CAM_LCD_HA_WIDTH 0x00000FFFU 638 #define LCD_CAM_LCD_HA_WIDTH_M (LCD_CAM_LCD_HA_WIDTH_V << LCD_CAM_LCD_HA_WIDTH_S) 639 #define LCD_CAM_LCD_HA_WIDTH_V 0x00000FFFU 640 #define LCD_CAM_LCD_HA_WIDTH_S 8 641 /** LCD_CAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0; 642 * It is the horizontal total width of a frame. 643 */ 644 #define LCD_CAM_LCD_HT_WIDTH 0x00000FFFU 645 #define LCD_CAM_LCD_HT_WIDTH_M (LCD_CAM_LCD_HT_WIDTH_V << LCD_CAM_LCD_HT_WIDTH_S) 646 #define LCD_CAM_LCD_HT_WIDTH_V 0x00000FFFU 647 #define LCD_CAM_LCD_HT_WIDTH_S 20 648 649 /** LCD_CAM_LCD_CTRL2_REG register 650 * LCD configuration register 651 */ 652 #define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x24) 653 /** LCD_CAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1; 654 * It is the position of LCD_VSYNC active pulse in a line. 655 */ 656 #define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007FU 657 #define LCD_CAM_LCD_VSYNC_WIDTH_M (LCD_CAM_LCD_VSYNC_WIDTH_V << LCD_CAM_LCD_VSYNC_WIDTH_S) 658 #define LCD_CAM_LCD_VSYNC_WIDTH_V 0x0000007FU 659 #define LCD_CAM_LCD_VSYNC_WIDTH_S 0 660 /** LCD_CAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0; 661 * It is the idle value of LCD_VSYNC. 662 */ 663 #define LCD_CAM_LCD_VSYNC_IDLE_POL (BIT(7)) 664 #define LCD_CAM_LCD_VSYNC_IDLE_POL_M (LCD_CAM_LCD_VSYNC_IDLE_POL_V << LCD_CAM_LCD_VSYNC_IDLE_POL_S) 665 #define LCD_CAM_LCD_VSYNC_IDLE_POL_V 0x00000001U 666 #define LCD_CAM_LCD_VSYNC_IDLE_POL_S 7 667 /** LCD_CAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0; 668 * It is the idle value of LCD_DE. 669 */ 670 #define LCD_CAM_LCD_DE_IDLE_POL (BIT(8)) 671 #define LCD_CAM_LCD_DE_IDLE_POL_M (LCD_CAM_LCD_DE_IDLE_POL_V << LCD_CAM_LCD_DE_IDLE_POL_S) 672 #define LCD_CAM_LCD_DE_IDLE_POL_V 0x00000001U 673 #define LCD_CAM_LCD_DE_IDLE_POL_S 8 674 /** LCD_CAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0; 675 * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC 676 * pulse is valid only in active region lines in RGB mode. 677 */ 678 #define LCD_CAM_LCD_HS_BLANK_EN (BIT(9)) 679 #define LCD_CAM_LCD_HS_BLANK_EN_M (LCD_CAM_LCD_HS_BLANK_EN_V << LCD_CAM_LCD_HS_BLANK_EN_S) 680 #define LCD_CAM_LCD_HS_BLANK_EN_V 0x00000001U 681 #define LCD_CAM_LCD_HS_BLANK_EN_S 9 682 /** LCD_CAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1; 683 * It is the position of LCD_HSYNC active pulse in a line. 684 */ 685 #define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007FU 686 #define LCD_CAM_LCD_HSYNC_WIDTH_M (LCD_CAM_LCD_HSYNC_WIDTH_V << LCD_CAM_LCD_HSYNC_WIDTH_S) 687 #define LCD_CAM_LCD_HSYNC_WIDTH_V 0x0000007FU 688 #define LCD_CAM_LCD_HSYNC_WIDTH_S 16 689 /** LCD_CAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0; 690 * It is the idle value of LCD_HSYNC. 691 */ 692 #define LCD_CAM_LCD_HSYNC_IDLE_POL (BIT(23)) 693 #define LCD_CAM_LCD_HSYNC_IDLE_POL_M (LCD_CAM_LCD_HSYNC_IDLE_POL_V << LCD_CAM_LCD_HSYNC_IDLE_POL_S) 694 #define LCD_CAM_LCD_HSYNC_IDLE_POL_V 0x00000001U 695 #define LCD_CAM_LCD_HSYNC_IDLE_POL_S 23 696 /** LCD_CAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0; 697 * It is the position of LCD_HSYNC active pulse in a line. 698 */ 699 #define LCD_CAM_LCD_HSYNC_POSITION 0x000000FFU 700 #define LCD_CAM_LCD_HSYNC_POSITION_M (LCD_CAM_LCD_HSYNC_POSITION_V << LCD_CAM_LCD_HSYNC_POSITION_S) 701 #define LCD_CAM_LCD_HSYNC_POSITION_V 0x000000FFU 702 #define LCD_CAM_LCD_HSYNC_POSITION_S 24 703 704 /** LCD_CAM_LCD_CMD_VAL_REG register 705 * LCD configuration register 706 */ 707 #define LCD_CAM_LCD_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x28) 708 /** LCD_CAM_LCD_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; 709 * The LCD write command value. 710 */ 711 #define LCD_CAM_LCD_CMD_VALUE 0xFFFFFFFFU 712 #define LCD_CAM_LCD_CMD_VALUE_M (LCD_CAM_LCD_CMD_VALUE_V << LCD_CAM_LCD_CMD_VALUE_S) 713 #define LCD_CAM_LCD_CMD_VALUE_V 0xFFFFFFFFU 714 #define LCD_CAM_LCD_CMD_VALUE_S 0 715 716 /** LCD_CAM_LCD_DLY_MODE_REG register 717 * LCD configuration register 718 */ 719 #define LCD_CAM_LCD_DLY_MODE_REG (DR_REG_LCD_CAM_BASE + 0x30) 720 /** LCD_CAM_LCD_CD_MODE : R/W; bitpos: [1:0]; default: 0; 721 * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: 722 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 723 */ 724 #define LCD_CAM_LCD_CD_MODE 0x00000003U 725 #define LCD_CAM_LCD_CD_MODE_M (LCD_CAM_LCD_CD_MODE_V << LCD_CAM_LCD_CD_MODE_S) 726 #define LCD_CAM_LCD_CD_MODE_V 0x00000003U 727 #define LCD_CAM_LCD_CD_MODE_S 0 728 /** LCD_CAM_LCD_DE_MODE : R/W; bitpos: [3:2]; default: 0; 729 * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: 730 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 731 */ 732 #define LCD_CAM_LCD_DE_MODE 0x00000003U 733 #define LCD_CAM_LCD_DE_MODE_M (LCD_CAM_LCD_DE_MODE_V << LCD_CAM_LCD_DE_MODE_S) 734 #define LCD_CAM_LCD_DE_MODE_V 0x00000003U 735 #define LCD_CAM_LCD_DE_MODE_S 2 736 /** LCD_CAM_LCD_HSYNC_MODE : R/W; bitpos: [5:4]; default: 0; 737 * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 738 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 739 */ 740 #define LCD_CAM_LCD_HSYNC_MODE 0x00000003U 741 #define LCD_CAM_LCD_HSYNC_MODE_M (LCD_CAM_LCD_HSYNC_MODE_V << LCD_CAM_LCD_HSYNC_MODE_S) 742 #define LCD_CAM_LCD_HSYNC_MODE_V 0x00000003U 743 #define LCD_CAM_LCD_HSYNC_MODE_S 4 744 /** LCD_CAM_LCD_VSYNC_MODE : R/W; bitpos: [7:6]; default: 0; 745 * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 746 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. 747 */ 748 #define LCD_CAM_LCD_VSYNC_MODE 0x00000003U 749 #define LCD_CAM_LCD_VSYNC_MODE_M (LCD_CAM_LCD_VSYNC_MODE_V << LCD_CAM_LCD_VSYNC_MODE_S) 750 #define LCD_CAM_LCD_VSYNC_MODE_V 0x00000003U 751 #define LCD_CAM_LCD_VSYNC_MODE_S 6 752 753 /** LCD_CAM_LCD_DATA_DOUT_MODE_REG register 754 * LCD configuration register 755 */ 756 #define LCD_CAM_LCD_DATA_DOUT_MODE_REG (DR_REG_LCD_CAM_BASE + 0x38) 757 /** LCD_CAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0; 758 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 759 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 760 * LCD_CLK. 761 */ 762 #define LCD_CAM_DOUT0_MODE 0x00000003U 763 #define LCD_CAM_DOUT0_MODE_M (LCD_CAM_DOUT0_MODE_V << LCD_CAM_DOUT0_MODE_S) 764 #define LCD_CAM_DOUT0_MODE_V 0x00000003U 765 #define LCD_CAM_DOUT0_MODE_S 0 766 /** LCD_CAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0; 767 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 768 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 769 * LCD_CLK. 770 */ 771 #define LCD_CAM_DOUT1_MODE 0x00000003U 772 #define LCD_CAM_DOUT1_MODE_M (LCD_CAM_DOUT1_MODE_V << LCD_CAM_DOUT1_MODE_S) 773 #define LCD_CAM_DOUT1_MODE_V 0x00000003U 774 #define LCD_CAM_DOUT1_MODE_S 2 775 /** LCD_CAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0; 776 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 777 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 778 * LCD_CLK. 779 */ 780 #define LCD_CAM_DOUT2_MODE 0x00000003U 781 #define LCD_CAM_DOUT2_MODE_M (LCD_CAM_DOUT2_MODE_V << LCD_CAM_DOUT2_MODE_S) 782 #define LCD_CAM_DOUT2_MODE_V 0x00000003U 783 #define LCD_CAM_DOUT2_MODE_S 4 784 /** LCD_CAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0; 785 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 786 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 787 * LCD_CLK. 788 */ 789 #define LCD_CAM_DOUT3_MODE 0x00000003U 790 #define LCD_CAM_DOUT3_MODE_M (LCD_CAM_DOUT3_MODE_V << LCD_CAM_DOUT3_MODE_S) 791 #define LCD_CAM_DOUT3_MODE_V 0x00000003U 792 #define LCD_CAM_DOUT3_MODE_S 6 793 /** LCD_CAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0; 794 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 795 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 796 * LCD_CLK. 797 */ 798 #define LCD_CAM_DOUT4_MODE 0x00000003U 799 #define LCD_CAM_DOUT4_MODE_M (LCD_CAM_DOUT4_MODE_V << LCD_CAM_DOUT4_MODE_S) 800 #define LCD_CAM_DOUT4_MODE_V 0x00000003U 801 #define LCD_CAM_DOUT4_MODE_S 8 802 /** LCD_CAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0; 803 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 804 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 805 * LCD_CLK. 806 */ 807 #define LCD_CAM_DOUT5_MODE 0x00000003U 808 #define LCD_CAM_DOUT5_MODE_M (LCD_CAM_DOUT5_MODE_V << LCD_CAM_DOUT5_MODE_S) 809 #define LCD_CAM_DOUT5_MODE_V 0x00000003U 810 #define LCD_CAM_DOUT5_MODE_S 10 811 /** LCD_CAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0; 812 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 813 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 814 * LCD_CLK. 815 */ 816 #define LCD_CAM_DOUT6_MODE 0x00000003U 817 #define LCD_CAM_DOUT6_MODE_M (LCD_CAM_DOUT6_MODE_V << LCD_CAM_DOUT6_MODE_S) 818 #define LCD_CAM_DOUT6_MODE_V 0x00000003U 819 #define LCD_CAM_DOUT6_MODE_S 12 820 /** LCD_CAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0; 821 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 822 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 823 * LCD_CLK. 824 */ 825 #define LCD_CAM_DOUT7_MODE 0x00000003U 826 #define LCD_CAM_DOUT7_MODE_M (LCD_CAM_DOUT7_MODE_V << LCD_CAM_DOUT7_MODE_S) 827 #define LCD_CAM_DOUT7_MODE_V 0x00000003U 828 #define LCD_CAM_DOUT7_MODE_S 14 829 /** LCD_CAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0; 830 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 831 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 832 * LCD_CLK. 833 */ 834 #define LCD_CAM_DOUT8_MODE 0x00000003U 835 #define LCD_CAM_DOUT8_MODE_M (LCD_CAM_DOUT8_MODE_V << LCD_CAM_DOUT8_MODE_S) 836 #define LCD_CAM_DOUT8_MODE_V 0x00000003U 837 #define LCD_CAM_DOUT8_MODE_S 16 838 /** LCD_CAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0; 839 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 840 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 841 * LCD_CLK. 842 */ 843 #define LCD_CAM_DOUT9_MODE 0x00000003U 844 #define LCD_CAM_DOUT9_MODE_M (LCD_CAM_DOUT9_MODE_V << LCD_CAM_DOUT9_MODE_S) 845 #define LCD_CAM_DOUT9_MODE_V 0x00000003U 846 #define LCD_CAM_DOUT9_MODE_S 18 847 /** LCD_CAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0; 848 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 849 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 850 * LCD_CLK. 851 */ 852 #define LCD_CAM_DOUT10_MODE 0x00000003U 853 #define LCD_CAM_DOUT10_MODE_M (LCD_CAM_DOUT10_MODE_V << LCD_CAM_DOUT10_MODE_S) 854 #define LCD_CAM_DOUT10_MODE_V 0x00000003U 855 #define LCD_CAM_DOUT10_MODE_S 20 856 /** LCD_CAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0; 857 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 858 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 859 * LCD_CLK. 860 */ 861 #define LCD_CAM_DOUT11_MODE 0x00000003U 862 #define LCD_CAM_DOUT11_MODE_M (LCD_CAM_DOUT11_MODE_V << LCD_CAM_DOUT11_MODE_S) 863 #define LCD_CAM_DOUT11_MODE_V 0x00000003U 864 #define LCD_CAM_DOUT11_MODE_S 22 865 /** LCD_CAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0; 866 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 867 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 868 * LCD_CLK. 869 */ 870 #define LCD_CAM_DOUT12_MODE 0x00000003U 871 #define LCD_CAM_DOUT12_MODE_M (LCD_CAM_DOUT12_MODE_V << LCD_CAM_DOUT12_MODE_S) 872 #define LCD_CAM_DOUT12_MODE_V 0x00000003U 873 #define LCD_CAM_DOUT12_MODE_S 24 874 /** LCD_CAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0; 875 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 876 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 877 * LCD_CLK. 878 */ 879 #define LCD_CAM_DOUT13_MODE 0x00000003U 880 #define LCD_CAM_DOUT13_MODE_M (LCD_CAM_DOUT13_MODE_V << LCD_CAM_DOUT13_MODE_S) 881 #define LCD_CAM_DOUT13_MODE_V 0x00000003U 882 #define LCD_CAM_DOUT13_MODE_S 26 883 /** LCD_CAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0; 884 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 885 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 886 * LCD_CLK. 887 */ 888 #define LCD_CAM_DOUT14_MODE 0x00000003U 889 #define LCD_CAM_DOUT14_MODE_M (LCD_CAM_DOUT14_MODE_V << LCD_CAM_DOUT14_MODE_S) 890 #define LCD_CAM_DOUT14_MODE_V 0x00000003U 891 #define LCD_CAM_DOUT14_MODE_S 28 892 /** LCD_CAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0; 893 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without 894 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of 895 * LCD_CLK. 896 */ 897 #define LCD_CAM_DOUT15_MODE 0x00000003U 898 #define LCD_CAM_DOUT15_MODE_M (LCD_CAM_DOUT15_MODE_V << LCD_CAM_DOUT15_MODE_S) 899 #define LCD_CAM_DOUT15_MODE_V 0x00000003U 900 #define LCD_CAM_DOUT15_MODE_S 30 901 902 /** LCD_CAM_LC_DMA_INT_ENA_REG register 903 * LCD_camera DMA inturrupt enable register 904 */ 905 #define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x64) 906 /** LCD_CAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0; 907 * The enable bit for LCD frame end interrupt. 908 */ 909 #define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0)) 910 #define LCD_CAM_LCD_VSYNC_INT_ENA_M (LCD_CAM_LCD_VSYNC_INT_ENA_V << LCD_CAM_LCD_VSYNC_INT_ENA_S) 911 #define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x00000001U 912 #define LCD_CAM_LCD_VSYNC_INT_ENA_S 0 913 /** LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; 914 * The enable bit for lcd transfer end interrupt. 915 */ 916 #define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) 917 #define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (LCD_CAM_LCD_TRANS_DONE_INT_ENA_V << LCD_CAM_LCD_TRANS_DONE_INT_ENA_S) 918 #define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x00000001U 919 #define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1 920 /** LCD_CAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0; 921 * The enable bit for Camera frame end interrupt. 922 */ 923 #define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2)) 924 #define LCD_CAM_CAM_VSYNC_INT_ENA_M (LCD_CAM_CAM_VSYNC_INT_ENA_V << LCD_CAM_CAM_VSYNC_INT_ENA_S) 925 #define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x00000001U 926 #define LCD_CAM_CAM_VSYNC_INT_ENA_S 2 927 /** LCD_CAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0; 928 * The enable bit for Camera line interrupt. 929 */ 930 #define LCD_CAM_CAM_HS_INT_ENA (BIT(3)) 931 #define LCD_CAM_CAM_HS_INT_ENA_M (LCD_CAM_CAM_HS_INT_ENA_V << LCD_CAM_CAM_HS_INT_ENA_S) 932 #define LCD_CAM_CAM_HS_INT_ENA_V 0x00000001U 933 #define LCD_CAM_CAM_HS_INT_ENA_S 3 934 935 /** LCD_CAM_LC_DMA_INT_RAW_REG register 936 * LCD_camera DMA raw inturrupt status register 937 */ 938 #define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x68) 939 /** LCD_CAM_LCD_VSYNC_INT_RAW : RO; bitpos: [0]; default: 0; 940 * The raw bit for LCD frame end interrupt. 941 */ 942 #define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0)) 943 #define LCD_CAM_LCD_VSYNC_INT_RAW_M (LCD_CAM_LCD_VSYNC_INT_RAW_V << LCD_CAM_LCD_VSYNC_INT_RAW_S) 944 #define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x00000001U 945 #define LCD_CAM_LCD_VSYNC_INT_RAW_S 0 946 /** LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO; bitpos: [1]; default: 0; 947 * The raw bit for lcd transfer end interrupt. 948 */ 949 #define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) 950 #define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (LCD_CAM_LCD_TRANS_DONE_INT_RAW_V << LCD_CAM_LCD_TRANS_DONE_INT_RAW_S) 951 #define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x00000001U 952 #define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1 953 /** LCD_CAM_CAM_VSYNC_INT_RAW : RO; bitpos: [2]; default: 0; 954 * The raw bit for Camera frame end interrupt. 955 */ 956 #define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2)) 957 #define LCD_CAM_CAM_VSYNC_INT_RAW_M (LCD_CAM_CAM_VSYNC_INT_RAW_V << LCD_CAM_CAM_VSYNC_INT_RAW_S) 958 #define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x00000001U 959 #define LCD_CAM_CAM_VSYNC_INT_RAW_S 2 960 /** LCD_CAM_CAM_HS_INT_RAW : RO; bitpos: [3]; default: 0; 961 * The raw bit for Camera line interrupt. 962 */ 963 #define LCD_CAM_CAM_HS_INT_RAW (BIT(3)) 964 #define LCD_CAM_CAM_HS_INT_RAW_M (LCD_CAM_CAM_HS_INT_RAW_V << LCD_CAM_CAM_HS_INT_RAW_S) 965 #define LCD_CAM_CAM_HS_INT_RAW_V 0x00000001U 966 #define LCD_CAM_CAM_HS_INT_RAW_S 3 967 968 /** LCD_CAM_LC_DMA_INT_ST_REG register 969 * LCD_camera DMA masked inturrupt status register 970 */ 971 #define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x6c) 972 /** LCD_CAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0; 973 * The status bit for LCD frame end interrupt. 974 */ 975 #define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0)) 976 #define LCD_CAM_LCD_VSYNC_INT_ST_M (LCD_CAM_LCD_VSYNC_INT_ST_V << LCD_CAM_LCD_VSYNC_INT_ST_S) 977 #define LCD_CAM_LCD_VSYNC_INT_ST_V 0x00000001U 978 #define LCD_CAM_LCD_VSYNC_INT_ST_S 0 979 /** LCD_CAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0; 980 * The status bit for lcd transfer end interrupt. 981 */ 982 #define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1)) 983 #define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (LCD_CAM_LCD_TRANS_DONE_INT_ST_V << LCD_CAM_LCD_TRANS_DONE_INT_ST_S) 984 #define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x00000001U 985 #define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1 986 /** LCD_CAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0; 987 * The status bit for Camera frame end interrupt. 988 */ 989 #define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2)) 990 #define LCD_CAM_CAM_VSYNC_INT_ST_M (LCD_CAM_CAM_VSYNC_INT_ST_V << LCD_CAM_CAM_VSYNC_INT_ST_S) 991 #define LCD_CAM_CAM_VSYNC_INT_ST_V 0x00000001U 992 #define LCD_CAM_CAM_VSYNC_INT_ST_S 2 993 /** LCD_CAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0; 994 * The status bit for Camera transfer end interrupt. 995 */ 996 #define LCD_CAM_CAM_HS_INT_ST (BIT(3)) 997 #define LCD_CAM_CAM_HS_INT_ST_M (LCD_CAM_CAM_HS_INT_ST_V << LCD_CAM_CAM_HS_INT_ST_S) 998 #define LCD_CAM_CAM_HS_INT_ST_V 0x00000001U 999 #define LCD_CAM_CAM_HS_INT_ST_S 3 1000 1001 /** LCD_CAM_LC_DMA_INT_CLR_REG register 1002 * LCD_camera DMA inturrupt clear register 1003 */ 1004 #define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x70) 1005 /** LCD_CAM_LCD_VSYNC_INT_CLR : WO; bitpos: [0]; default: 0; 1006 * The clear bit for LCD frame end interrupt. 1007 */ 1008 #define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0)) 1009 #define LCD_CAM_LCD_VSYNC_INT_CLR_M (LCD_CAM_LCD_VSYNC_INT_CLR_V << LCD_CAM_LCD_VSYNC_INT_CLR_S) 1010 #define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x00000001U 1011 #define LCD_CAM_LCD_VSYNC_INT_CLR_S 0 1012 /** LCD_CAM_LCD_TRANS_DONE_INT_CLR : WO; bitpos: [1]; default: 0; 1013 * The clear bit for lcd transfer end interrupt. 1014 */ 1015 #define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) 1016 #define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (LCD_CAM_LCD_TRANS_DONE_INT_CLR_V << LCD_CAM_LCD_TRANS_DONE_INT_CLR_S) 1017 #define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x00000001U 1018 #define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1 1019 /** LCD_CAM_CAM_VSYNC_INT_CLR : WO; bitpos: [2]; default: 0; 1020 * The clear bit for Camera frame end interrupt. 1021 */ 1022 #define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2)) 1023 #define LCD_CAM_CAM_VSYNC_INT_CLR_M (LCD_CAM_CAM_VSYNC_INT_CLR_V << LCD_CAM_CAM_VSYNC_INT_CLR_S) 1024 #define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x00000001U 1025 #define LCD_CAM_CAM_VSYNC_INT_CLR_S 2 1026 /** LCD_CAM_CAM_HS_INT_CLR : WO; bitpos: [3]; default: 0; 1027 * The clear bit for Camera line interrupt. 1028 */ 1029 #define LCD_CAM_CAM_HS_INT_CLR (BIT(3)) 1030 #define LCD_CAM_CAM_HS_INT_CLR_M (LCD_CAM_CAM_HS_INT_CLR_V << LCD_CAM_CAM_HS_INT_CLR_S) 1031 #define LCD_CAM_CAM_HS_INT_CLR_V 0x00000001U 1032 #define LCD_CAM_CAM_HS_INT_CLR_S 3 1033 1034 /** LCD_CAM_LC_REG_DATE_REG register 1035 * Version register 1036 */ 1037 #define LCD_CAM_LC_REG_DATE_REG (DR_REG_LCD_CAM_BASE + 0xfc) 1038 /** LCD_CAM_LC_DATE : R/W; bitpos: [27:0]; default: 33566752; 1039 * LCD_CAM version control register 1040 */ 1041 #define LCD_CAM_LC_DATE 0x0FFFFFFFU 1042 #define LCD_CAM_LC_DATE_M (LCD_CAM_LC_DATE_V << LCD_CAM_LC_DATE_S) 1043 #define LCD_CAM_LC_DATE_V 0x0FFFFFFFU 1044 #define LCD_CAM_LC_DATE_S 0 1045 1046 #ifdef __cplusplus 1047 } 1048 #endif 1049
