1 /* 2 * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_I2S_REG_H_ 7 #define _SOC_I2S_REG_H_ 8 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #include "soc.h" 14 #define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) 15 /* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ 16 /*description: */ 17 #define I2S_RX_RESET_ST (BIT(29)) 18 #define I2S_RX_RESET_ST_M (BIT(29)) 19 #define I2S_RX_RESET_ST_V 0x1 20 #define I2S_RX_RESET_ST_S 29 21 /* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 22 /*description: */ 23 #define I2S_RX_BIG_ENDIAN (BIT(28)) 24 #define I2S_RX_BIG_ENDIAN_M (BIT(28)) 25 #define I2S_RX_BIG_ENDIAN_V 0x1 26 #define I2S_RX_BIG_ENDIAN_S 28 27 /* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[27] ;default: 1'b0 ; */ 28 /*description: */ 29 #define I2S_TX_BIG_ENDIAN (BIT(27)) 30 #define I2S_TX_BIG_ENDIAN_M (BIT(27)) 31 #define I2S_TX_BIG_ENDIAN_V 0x1 32 #define I2S_TX_BIG_ENDIAN_S 27 33 /* I2S_PRE_REQ_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 34 /*description: set this bit to enable i2s to prepare data earlier*/ 35 #define I2S_PRE_REQ_EN (BIT(26)) 36 #define I2S_PRE_REQ_EN_M (BIT(26)) 37 #define I2S_PRE_REQ_EN_V 0x1 38 #define I2S_PRE_REQ_EN_S 26 39 /* I2S_RX_DMA_EQUAL : R/W ;bitpos:[25] ;default: 1'b0 ; */ 40 /*description: 1:data in left channel is equal to data in right channel*/ 41 #define I2S_RX_DMA_EQUAL (BIT(25)) 42 #define I2S_RX_DMA_EQUAL_M (BIT(25)) 43 #define I2S_RX_DMA_EQUAL_V 0x1 44 #define I2S_RX_DMA_EQUAL_S 25 45 /* I2S_TX_DMA_EQUAL : R/W ;bitpos:[24] ;default: 1'b0 ; */ 46 /*description: 1:data in left channel is equal to data in right channel*/ 47 #define I2S_TX_DMA_EQUAL (BIT(24)) 48 #define I2S_TX_DMA_EQUAL_M (BIT(24)) 49 #define I2S_TX_DMA_EQUAL_V 0x1 50 #define I2S_TX_DMA_EQUAL_S 24 51 /* I2S_TX_RESET_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ 52 /*description: 1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok*/ 53 #define I2S_TX_RESET_ST (BIT(23)) 54 #define I2S_TX_RESET_ST_M (BIT(23)) 55 #define I2S_TX_RESET_ST_V 0x1 56 #define I2S_TX_RESET_ST_S 23 57 /* I2S_RX_FIFO_RESET_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ 58 /*description: 1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok*/ 59 #define I2S_RX_FIFO_RESET_ST (BIT(22)) 60 #define I2S_RX_FIFO_RESET_ST_M (BIT(22)) 61 #define I2S_RX_FIFO_RESET_ST_V 0x1 62 #define I2S_RX_FIFO_RESET_ST_S 22 63 /* I2S_TX_FIFO_RESET_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ 64 /*description: 1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok*/ 65 #define I2S_TX_FIFO_RESET_ST (BIT(21)) 66 #define I2S_TX_FIFO_RESET_ST_M (BIT(21)) 67 #define I2S_TX_FIFO_RESET_ST_V 0x1 68 #define I2S_TX_FIFO_RESET_ST_S 21 69 /* I2S_SIG_LOOPBACK : R/W ;bitpos:[20] ;default: 1'b0 ; */ 70 /*description: Enable signal loopback mode with transmitter module and receiver 71 module sharing the same WS and BCK signals.*/ 72 #define I2S_SIG_LOOPBACK (BIT(20)) 73 #define I2S_SIG_LOOPBACK_M (BIT(20)) 74 #define I2S_SIG_LOOPBACK_V 0x1 75 #define I2S_SIG_LOOPBACK_S 20 76 /* I2S_RX_LSB_FIRST_DMA : R/W ;bitpos:[19] ;default: 1'b1 ; */ 77 /*description: 1:the data in DMA/APB transform from low bits*/ 78 #define I2S_RX_LSB_FIRST_DMA (BIT(19)) 79 #define I2S_RX_LSB_FIRST_DMA_M (BIT(19)) 80 #define I2S_RX_LSB_FIRST_DMA_V 0x1 81 #define I2S_RX_LSB_FIRST_DMA_S 19 82 /* I2S_TX_LSB_FIRST_DMA : R/W ;bitpos:[18] ;default: 1'b1 ; */ 83 /*description: 1:the data in DMA/APB transform from low bits*/ 84 #define I2S_TX_LSB_FIRST_DMA (BIT(18)) 85 #define I2S_TX_LSB_FIRST_DMA_M (BIT(18)) 86 #define I2S_TX_LSB_FIRST_DMA_V 0x1 87 #define I2S_TX_LSB_FIRST_DMA_S 18 88 /* I2S_RX_MSB_RIGHT : R/W ;bitpos:[17] ;default: 1'b0 ; */ 89 /*description: Set this bit to place right channel data at the MSB in the receive FIFO.*/ 90 #define I2S_RX_MSB_RIGHT (BIT(17)) 91 #define I2S_RX_MSB_RIGHT_M (BIT(17)) 92 #define I2S_RX_MSB_RIGHT_V 0x1 93 #define I2S_RX_MSB_RIGHT_S 17 94 /* I2S_TX_MSB_RIGHT : R/W ;bitpos:[16] ;default: 1'b0 ; */ 95 /*description: Set this bit to place right channel data at the MSB in the transmit FIFO.*/ 96 #define I2S_TX_MSB_RIGHT (BIT(16)) 97 #define I2S_TX_MSB_RIGHT_M (BIT(16)) 98 #define I2S_TX_MSB_RIGHT_V 0x1 99 #define I2S_TX_MSB_RIGHT_S 16 100 /* I2S_RX_MONO : R/W ;bitpos:[15] ;default: 1'b0 ; */ 101 /*description: Set this bit to enable receiver in mono mode*/ 102 #define I2S_RX_MONO (BIT(15)) 103 #define I2S_RX_MONO_M (BIT(15)) 104 #define I2S_RX_MONO_V 0x1 105 #define I2S_RX_MONO_S 15 106 /* I2S_TX_MONO : R/W ;bitpos:[14] ;default: 1'b0 ; */ 107 /*description: Set this bit to enable transmitter in mono mode*/ 108 #define I2S_TX_MONO (BIT(14)) 109 #define I2S_TX_MONO_M (BIT(14)) 110 #define I2S_TX_MONO_V 0x1 111 #define I2S_TX_MONO_S 14 112 /* I2S_RX_SHORT_SYNC : R/W ;bitpos:[13] ;default: 1'b0 ; */ 113 /*description: Set this bit to enable receiver in PCM standard mode*/ 114 #define I2S_RX_SHORT_SYNC (BIT(13)) 115 #define I2S_RX_SHORT_SYNC_M (BIT(13)) 116 #define I2S_RX_SHORT_SYNC_V 0x1 117 #define I2S_RX_SHORT_SYNC_S 13 118 /* I2S_TX_SHORT_SYNC : R/W ;bitpos:[12] ;default: 1'b0 ; */ 119 /*description: Set this bit to enable transmitter in PCM standard mode*/ 120 #define I2S_TX_SHORT_SYNC (BIT(12)) 121 #define I2S_TX_SHORT_SYNC_M (BIT(12)) 122 #define I2S_TX_SHORT_SYNC_V 0x1 123 #define I2S_TX_SHORT_SYNC_S 12 124 /* I2S_RX_MSB_SHIFT : R/W ;bitpos:[11] ;default: 1'b0 ; */ 125 /*description: Set this bit to enable receiver in Phillips standard mode*/ 126 #define I2S_RX_MSB_SHIFT (BIT(11)) 127 #define I2S_RX_MSB_SHIFT_M (BIT(11)) 128 #define I2S_RX_MSB_SHIFT_V 0x1 129 #define I2S_RX_MSB_SHIFT_S 11 130 /* I2S_TX_MSB_SHIFT : R/W ;bitpos:[10] ;default: 1'b0 ; */ 131 /*description: Set this bit to enable transmitter in Phillips standard mode*/ 132 #define I2S_TX_MSB_SHIFT (BIT(10)) 133 #define I2S_TX_MSB_SHIFT_M (BIT(10)) 134 #define I2S_TX_MSB_SHIFT_V 0x1 135 #define I2S_TX_MSB_SHIFT_S 10 136 /* I2S_RX_RIGHT_FIRST : R/W ;bitpos:[9] ;default: 1'b1 ; */ 137 /*description: Set this bit to receive right channel data first*/ 138 #define I2S_RX_RIGHT_FIRST (BIT(9)) 139 #define I2S_RX_RIGHT_FIRST_M (BIT(9)) 140 #define I2S_RX_RIGHT_FIRST_V 0x1 141 #define I2S_RX_RIGHT_FIRST_S 9 142 /* I2S_TX_RIGHT_FIRST : R/W ;bitpos:[8] ;default: 1'b1 ; */ 143 /*description: Set this bit to transmit right channel data first*/ 144 #define I2S_TX_RIGHT_FIRST (BIT(8)) 145 #define I2S_TX_RIGHT_FIRST_M (BIT(8)) 146 #define I2S_TX_RIGHT_FIRST_V 0x1 147 #define I2S_TX_RIGHT_FIRST_S 8 148 /* I2S_RX_SLAVE_MOD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 149 /*description: Set this bit to enable slave receiver mode*/ 150 #define I2S_RX_SLAVE_MOD (BIT(7)) 151 #define I2S_RX_SLAVE_MOD_M (BIT(7)) 152 #define I2S_RX_SLAVE_MOD_V 0x1 153 #define I2S_RX_SLAVE_MOD_S 7 154 /* I2S_TX_SLAVE_MOD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 155 /*description: Set this bit to enable slave transmitter mode*/ 156 #define I2S_TX_SLAVE_MOD (BIT(6)) 157 #define I2S_TX_SLAVE_MOD_M (BIT(6)) 158 #define I2S_TX_SLAVE_MOD_V 0x1 159 #define I2S_TX_SLAVE_MOD_S 6 160 /* I2S_RX_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ 161 /*description: Set this bit to start receiving data*/ 162 #define I2S_RX_START (BIT(5)) 163 #define I2S_RX_START_M (BIT(5)) 164 #define I2S_RX_START_V 0x1 165 #define I2S_RX_START_S 5 166 /* I2S_TX_START : R/W ;bitpos:[4] ;default: 1'b0 ; */ 167 /*description: Set this bit to start transmitting data*/ 168 #define I2S_TX_START (BIT(4)) 169 #define I2S_TX_START_M (BIT(4)) 170 #define I2S_TX_START_V 0x1 171 #define I2S_TX_START_S 4 172 /* I2S_RX_FIFO_RESET : WO ;bitpos:[3] ;default: 1'b0 ; */ 173 /*description: Set this bit to reset rxFIFO*/ 174 #define I2S_RX_FIFO_RESET (BIT(3)) 175 #define I2S_RX_FIFO_RESET_M (BIT(3)) 176 #define I2S_RX_FIFO_RESET_V 0x1 177 #define I2S_RX_FIFO_RESET_S 3 178 /* I2S_TX_FIFO_RESET : WO ;bitpos:[2] ;default: 1'b0 ; */ 179 /*description: Set this bit to reset txFIFO*/ 180 #define I2S_TX_FIFO_RESET (BIT(2)) 181 #define I2S_TX_FIFO_RESET_M (BIT(2)) 182 #define I2S_TX_FIFO_RESET_V 0x1 183 #define I2S_TX_FIFO_RESET_S 2 184 /* I2S_RX_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ 185 /*description: Set this bit to reset receiver*/ 186 #define I2S_RX_RESET (BIT(1)) 187 #define I2S_RX_RESET_M (BIT(1)) 188 #define I2S_RX_RESET_V 0x1 189 #define I2S_RX_RESET_S 1 190 /* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ 191 /*description: Set this bit to reset transmitter*/ 192 #define I2S_TX_RESET (BIT(0)) 193 #define I2S_TX_RESET_M (BIT(0)) 194 #define I2S_TX_RESET_V 0x1 195 #define I2S_TX_RESET_S 0 196 197 #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) 198 /* I2S_V_SYNC_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ 199 /*description: The raw interrupt status bit for the i2s_v_sync_int interrupt*/ 200 #define I2S_V_SYNC_INT_RAW (BIT(17)) 201 #define I2S_V_SYNC_INT_RAW_M (BIT(17)) 202 #define I2S_V_SYNC_INT_RAW_V 0x1 203 #define I2S_V_SYNC_INT_RAW_S 17 204 /* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 205 /*description: The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/ 206 #define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16)) 207 #define I2S_OUT_TOTAL_EOF_INT_RAW_M (BIT(16)) 208 #define I2S_OUT_TOTAL_EOF_INT_RAW_V 0x1 209 #define I2S_OUT_TOTAL_EOF_INT_RAW_S 16 210 /* I2S_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 211 /*description: The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt*/ 212 #define I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15)) 213 #define I2S_IN_DSCR_EMPTY_INT_RAW_M (BIT(15)) 214 #define I2S_IN_DSCR_EMPTY_INT_RAW_V 0x1 215 #define I2S_IN_DSCR_EMPTY_INT_RAW_S 15 216 /* I2S_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ 217 /*description: The raw interrupt status bit for the i2s_out_dscr_err_int interrupt*/ 218 #define I2S_OUT_DSCR_ERR_INT_RAW (BIT(14)) 219 #define I2S_OUT_DSCR_ERR_INT_RAW_M (BIT(14)) 220 #define I2S_OUT_DSCR_ERR_INT_RAW_V 0x1 221 #define I2S_OUT_DSCR_ERR_INT_RAW_S 14 222 /* I2S_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ 223 /*description: The raw interrupt status bit for the i2s_in_dscr_err_int interrupt*/ 224 #define I2S_IN_DSCR_ERR_INT_RAW (BIT(13)) 225 #define I2S_IN_DSCR_ERR_INT_RAW_M (BIT(13)) 226 #define I2S_IN_DSCR_ERR_INT_RAW_V 0x1 227 #define I2S_IN_DSCR_ERR_INT_RAW_S 13 228 /* I2S_OUT_EOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 229 /*description: The raw interrupt status bit for the i2s_out_eof_int interrupt*/ 230 #define I2S_OUT_EOF_INT_RAW (BIT(12)) 231 #define I2S_OUT_EOF_INT_RAW_M (BIT(12)) 232 #define I2S_OUT_EOF_INT_RAW_V 0x1 233 #define I2S_OUT_EOF_INT_RAW_S 12 234 /* I2S_OUT_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 235 /*description: The raw interrupt status bit for the i2s_out_done_int interrupt*/ 236 #define I2S_OUT_DONE_INT_RAW (BIT(11)) 237 #define I2S_OUT_DONE_INT_RAW_M (BIT(11)) 238 #define I2S_OUT_DONE_INT_RAW_V 0x1 239 #define I2S_OUT_DONE_INT_RAW_S 11 240 /* I2S_IN_ERR_EOF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 241 /*description: don't use*/ 242 #define I2S_IN_ERR_EOF_INT_RAW (BIT(10)) 243 #define I2S_IN_ERR_EOF_INT_RAW_M (BIT(10)) 244 #define I2S_IN_ERR_EOF_INT_RAW_V 0x1 245 #define I2S_IN_ERR_EOF_INT_RAW_S 10 246 /* I2S_IN_SUC_EOF_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 247 /*description: The raw interrupt status bit for the i2s_in_suc_eof_int interrupt*/ 248 #define I2S_IN_SUC_EOF_INT_RAW (BIT(9)) 249 #define I2S_IN_SUC_EOF_INT_RAW_M (BIT(9)) 250 #define I2S_IN_SUC_EOF_INT_RAW_V 0x1 251 #define I2S_IN_SUC_EOF_INT_RAW_S 9 252 /* I2S_IN_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 253 /*description: The raw interrupt status bit for the i2s_in_done_int interrupt*/ 254 #define I2S_IN_DONE_INT_RAW (BIT(8)) 255 #define I2S_IN_DONE_INT_RAW_M (BIT(8)) 256 #define I2S_IN_DONE_INT_RAW_V 0x1 257 #define I2S_IN_DONE_INT_RAW_S 8 258 /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 259 /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ 260 #define I2S_TX_HUNG_INT_RAW (BIT(7)) 261 #define I2S_TX_HUNG_INT_RAW_M (BIT(7)) 262 #define I2S_TX_HUNG_INT_RAW_V 0x1 263 #define I2S_TX_HUNG_INT_RAW_S 7 264 /* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 265 /*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ 266 #define I2S_RX_HUNG_INT_RAW (BIT(6)) 267 #define I2S_RX_HUNG_INT_RAW_M (BIT(6)) 268 #define I2S_RX_HUNG_INT_RAW_V 0x1 269 #define I2S_RX_HUNG_INT_RAW_S 6 270 /* I2S_TX_REMPTY_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 271 /*description: The raw interrupt status bit for the i2s_tx_rempty_int interrupt*/ 272 #define I2S_TX_REMPTY_INT_RAW (BIT(5)) 273 #define I2S_TX_REMPTY_INT_RAW_M (BIT(5)) 274 #define I2S_TX_REMPTY_INT_RAW_V 0x1 275 #define I2S_TX_REMPTY_INT_RAW_S 5 276 /* I2S_TX_WFULL_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 277 /*description: The raw interrupt status bit for the i2s_tx_wfull_int interrupt*/ 278 #define I2S_TX_WFULL_INT_RAW (BIT(4)) 279 #define I2S_TX_WFULL_INT_RAW_M (BIT(4)) 280 #define I2S_TX_WFULL_INT_RAW_V 0x1 281 #define I2S_TX_WFULL_INT_RAW_S 4 282 /* I2S_RX_REMPTY_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 283 /*description: The raw interrupt status bit for the i2s_rx_rempty_int interrupt*/ 284 #define I2S_RX_REMPTY_INT_RAW (BIT(3)) 285 #define I2S_RX_REMPTY_INT_RAW_M (BIT(3)) 286 #define I2S_RX_REMPTY_INT_RAW_V 0x1 287 #define I2S_RX_REMPTY_INT_RAW_S 3 288 /* I2S_RX_WFULL_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 289 /*description: The raw interrupt status bit for the i2s_rx_wfull_int interrupt*/ 290 #define I2S_RX_WFULL_INT_RAW (BIT(2)) 291 #define I2S_RX_WFULL_INT_RAW_M (BIT(2)) 292 #define I2S_RX_WFULL_INT_RAW_V 0x1 293 #define I2S_RX_WFULL_INT_RAW_S 2 294 /* I2S_TX_PUT_DATA_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 295 /*description: The raw interrupt status bit for the i2s_tx_put_data_int interrupt*/ 296 #define I2S_TX_PUT_DATA_INT_RAW (BIT(1)) 297 #define I2S_TX_PUT_DATA_INT_RAW_M (BIT(1)) 298 #define I2S_TX_PUT_DATA_INT_RAW_V 0x1 299 #define I2S_TX_PUT_DATA_INT_RAW_S 1 300 /* I2S_RX_TAKE_DATA_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 301 /*description: The raw interrupt status bit for the i2s_rx_take_data_int interrupt*/ 302 #define I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) 303 #define I2S_RX_TAKE_DATA_INT_RAW_M (BIT(0)) 304 #define I2S_RX_TAKE_DATA_INT_RAW_V 0x1 305 #define I2S_RX_TAKE_DATA_INT_RAW_S 0 306 307 #define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) 308 /* I2S_V_SYNC_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ 309 /*description: The masked interrupt status bit for the i2s_v_sync_int interrupt*/ 310 #define I2S_V_SYNC_INT_ST (BIT(17)) 311 #define I2S_V_SYNC_INT_ST_M (BIT(17)) 312 #define I2S_V_SYNC_INT_ST_V 0x1 313 #define I2S_V_SYNC_INT_ST_S 17 314 /* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 315 /*description: The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/ 316 #define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16)) 317 #define I2S_OUT_TOTAL_EOF_INT_ST_M (BIT(16)) 318 #define I2S_OUT_TOTAL_EOF_INT_ST_V 0x1 319 #define I2S_OUT_TOTAL_EOF_INT_ST_S 16 320 /* I2S_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 321 /*description: The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt*/ 322 #define I2S_IN_DSCR_EMPTY_INT_ST (BIT(15)) 323 #define I2S_IN_DSCR_EMPTY_INT_ST_M (BIT(15)) 324 #define I2S_IN_DSCR_EMPTY_INT_ST_V 0x1 325 #define I2S_IN_DSCR_EMPTY_INT_ST_S 15 326 /* I2S_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ 327 /*description: The masked interrupt status bit for the i2s_out_dscr_err_int interrupt*/ 328 #define I2S_OUT_DSCR_ERR_INT_ST (BIT(14)) 329 #define I2S_OUT_DSCR_ERR_INT_ST_M (BIT(14)) 330 #define I2S_OUT_DSCR_ERR_INT_ST_V 0x1 331 #define I2S_OUT_DSCR_ERR_INT_ST_S 14 332 /* I2S_IN_DSCR_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 333 /*description: The masked interrupt status bit for the i2s_in_dscr_err_int interrupt*/ 334 #define I2S_IN_DSCR_ERR_INT_ST (BIT(13)) 335 #define I2S_IN_DSCR_ERR_INT_ST_M (BIT(13)) 336 #define I2S_IN_DSCR_ERR_INT_ST_V 0x1 337 #define I2S_IN_DSCR_ERR_INT_ST_S 13 338 /* I2S_OUT_EOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 339 /*description: The masked interrupt status bit for the i2s_out_eof_int interrupt*/ 340 #define I2S_OUT_EOF_INT_ST (BIT(12)) 341 #define I2S_OUT_EOF_INT_ST_M (BIT(12)) 342 #define I2S_OUT_EOF_INT_ST_V 0x1 343 #define I2S_OUT_EOF_INT_ST_S 12 344 /* I2S_OUT_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 345 /*description: The masked interrupt status bit for the i2s_out_done_int interrupt*/ 346 #define I2S_OUT_DONE_INT_ST (BIT(11)) 347 #define I2S_OUT_DONE_INT_ST_M (BIT(11)) 348 #define I2S_OUT_DONE_INT_ST_V 0x1 349 #define I2S_OUT_DONE_INT_ST_S 11 350 /* I2S_IN_ERR_EOF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 351 /*description: don't use*/ 352 #define I2S_IN_ERR_EOF_INT_ST (BIT(10)) 353 #define I2S_IN_ERR_EOF_INT_ST_M (BIT(10)) 354 #define I2S_IN_ERR_EOF_INT_ST_V 0x1 355 #define I2S_IN_ERR_EOF_INT_ST_S 10 356 /* I2S_IN_SUC_EOF_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 357 /*description: The masked interrupt status bit for the i2s_in_suc_eof_int interrupt*/ 358 #define I2S_IN_SUC_EOF_INT_ST (BIT(9)) 359 #define I2S_IN_SUC_EOF_INT_ST_M (BIT(9)) 360 #define I2S_IN_SUC_EOF_INT_ST_V 0x1 361 #define I2S_IN_SUC_EOF_INT_ST_S 9 362 /* I2S_IN_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 363 /*description: The masked interrupt status bit for the i2s_in_done_int interrupt*/ 364 #define I2S_IN_DONE_INT_ST (BIT(8)) 365 #define I2S_IN_DONE_INT_ST_M (BIT(8)) 366 #define I2S_IN_DONE_INT_ST_V 0x1 367 #define I2S_IN_DONE_INT_ST_S 8 368 /* I2S_TX_HUNG_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 369 /*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ 370 #define I2S_TX_HUNG_INT_ST (BIT(7)) 371 #define I2S_TX_HUNG_INT_ST_M (BIT(7)) 372 #define I2S_TX_HUNG_INT_ST_V 0x1 373 #define I2S_TX_HUNG_INT_ST_S 7 374 /* I2S_RX_HUNG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 375 /*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ 376 #define I2S_RX_HUNG_INT_ST (BIT(6)) 377 #define I2S_RX_HUNG_INT_ST_M (BIT(6)) 378 #define I2S_RX_HUNG_INT_ST_V 0x1 379 #define I2S_RX_HUNG_INT_ST_S 6 380 /* I2S_TX_REMPTY_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 381 /*description: The masked interrupt status bit for the i2s_tx_rempty_int interrupt*/ 382 #define I2S_TX_REMPTY_INT_ST (BIT(5)) 383 #define I2S_TX_REMPTY_INT_ST_M (BIT(5)) 384 #define I2S_TX_REMPTY_INT_ST_V 0x1 385 #define I2S_TX_REMPTY_INT_ST_S 5 386 /* I2S_TX_WFULL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 387 /*description: The masked interrupt status bit for the i2s_tx_wfull_int interrupt*/ 388 #define I2S_TX_WFULL_INT_ST (BIT(4)) 389 #define I2S_TX_WFULL_INT_ST_M (BIT(4)) 390 #define I2S_TX_WFULL_INT_ST_V 0x1 391 #define I2S_TX_WFULL_INT_ST_S 4 392 /* I2S_RX_REMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 393 /*description: The masked interrupt status bit for the i2s_rx_rempty_int interrupt*/ 394 #define I2S_RX_REMPTY_INT_ST (BIT(3)) 395 #define I2S_RX_REMPTY_INT_ST_M (BIT(3)) 396 #define I2S_RX_REMPTY_INT_ST_V 0x1 397 #define I2S_RX_REMPTY_INT_ST_S 3 398 /* I2S_RX_WFULL_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 399 /*description: The masked interrupt status bit for the i2s_rx_wfull_int interrupt*/ 400 #define I2S_RX_WFULL_INT_ST (BIT(2)) 401 #define I2S_RX_WFULL_INT_ST_M (BIT(2)) 402 #define I2S_RX_WFULL_INT_ST_V 0x1 403 #define I2S_RX_WFULL_INT_ST_S 2 404 /* I2S_TX_PUT_DATA_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 405 /*description: The masked interrupt status bit for the i2s_tx_put_data_int interrupt*/ 406 #define I2S_TX_PUT_DATA_INT_ST (BIT(1)) 407 #define I2S_TX_PUT_DATA_INT_ST_M (BIT(1)) 408 #define I2S_TX_PUT_DATA_INT_ST_V 0x1 409 #define I2S_TX_PUT_DATA_INT_ST_S 1 410 /* I2S_RX_TAKE_DATA_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 411 /*description: The masked interrupt status bit for the i2s_rx_take_data_int interrupt*/ 412 #define I2S_RX_TAKE_DATA_INT_ST (BIT(0)) 413 #define I2S_RX_TAKE_DATA_INT_ST_M (BIT(0)) 414 #define I2S_RX_TAKE_DATA_INT_ST_V 0x1 415 #define I2S_RX_TAKE_DATA_INT_ST_S 0 416 417 #define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) 418 /* I2S_V_SYNC_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ 419 /*description: The interrupt enable bit for the i2s_v_sync_int interrupt*/ 420 #define I2S_V_SYNC_INT_ENA (BIT(17)) 421 #define I2S_V_SYNC_INT_ENA_M (BIT(17)) 422 #define I2S_V_SYNC_INT_ENA_V 0x1 423 #define I2S_V_SYNC_INT_ENA_S 17 424 /* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 425 /*description: The interrupt enable bit for the i2s_out_total_eof_int interrupt*/ 426 #define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16)) 427 #define I2S_OUT_TOTAL_EOF_INT_ENA_M (BIT(16)) 428 #define I2S_OUT_TOTAL_EOF_INT_ENA_V 0x1 429 #define I2S_OUT_TOTAL_EOF_INT_ENA_S 16 430 /* I2S_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 431 /*description: The interrupt enable bit for the i2s_in_dscr_empty_int interrupt*/ 432 #define I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15)) 433 #define I2S_IN_DSCR_EMPTY_INT_ENA_M (BIT(15)) 434 #define I2S_IN_DSCR_EMPTY_INT_ENA_V 0x1 435 #define I2S_IN_DSCR_EMPTY_INT_ENA_S 15 436 /* I2S_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 437 /*description: The interrupt enable bit for the i2s_out_dscr_err_int interrupt*/ 438 #define I2S_OUT_DSCR_ERR_INT_ENA (BIT(14)) 439 #define I2S_OUT_DSCR_ERR_INT_ENA_M (BIT(14)) 440 #define I2S_OUT_DSCR_ERR_INT_ENA_V 0x1 441 #define I2S_OUT_DSCR_ERR_INT_ENA_S 14 442 /* I2S_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 443 /*description: The interrupt enable bit for the i2s_in_dscr_err_int interrupt*/ 444 #define I2S_IN_DSCR_ERR_INT_ENA (BIT(13)) 445 #define I2S_IN_DSCR_ERR_INT_ENA_M (BIT(13)) 446 #define I2S_IN_DSCR_ERR_INT_ENA_V 0x1 447 #define I2S_IN_DSCR_ERR_INT_ENA_S 13 448 /* I2S_OUT_EOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 449 /*description: The interrupt enable bit for the i2s_out_eof_int interrupt*/ 450 #define I2S_OUT_EOF_INT_ENA (BIT(12)) 451 #define I2S_OUT_EOF_INT_ENA_M (BIT(12)) 452 #define I2S_OUT_EOF_INT_ENA_V 0x1 453 #define I2S_OUT_EOF_INT_ENA_S 12 454 /* I2S_OUT_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 455 /*description: The interrupt enable bit for the i2s_out_done_int interrupt*/ 456 #define I2S_OUT_DONE_INT_ENA (BIT(11)) 457 #define I2S_OUT_DONE_INT_ENA_M (BIT(11)) 458 #define I2S_OUT_DONE_INT_ENA_V 0x1 459 #define I2S_OUT_DONE_INT_ENA_S 11 460 /* I2S_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 461 /*description: don't use*/ 462 #define I2S_IN_ERR_EOF_INT_ENA (BIT(10)) 463 #define I2S_IN_ERR_EOF_INT_ENA_M (BIT(10)) 464 #define I2S_IN_ERR_EOF_INT_ENA_V 0x1 465 #define I2S_IN_ERR_EOF_INT_ENA_S 10 466 /* I2S_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 467 /*description: The interrupt enable bit for the i2s_in_suc_eof_int interrupt*/ 468 #define I2S_IN_SUC_EOF_INT_ENA (BIT(9)) 469 #define I2S_IN_SUC_EOF_INT_ENA_M (BIT(9)) 470 #define I2S_IN_SUC_EOF_INT_ENA_V 0x1 471 #define I2S_IN_SUC_EOF_INT_ENA_S 9 472 /* I2S_IN_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 473 /*description: The interrupt enable bit for the i2s_in_done_int interrupt*/ 474 #define I2S_IN_DONE_INT_ENA (BIT(8)) 475 #define I2S_IN_DONE_INT_ENA_M (BIT(8)) 476 #define I2S_IN_DONE_INT_ENA_V 0x1 477 #define I2S_IN_DONE_INT_ENA_S 8 478 /* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 479 /*description: The interrupt enable bit for the i2s_tx_hung_int interrupt*/ 480 #define I2S_TX_HUNG_INT_ENA (BIT(7)) 481 #define I2S_TX_HUNG_INT_ENA_M (BIT(7)) 482 #define I2S_TX_HUNG_INT_ENA_V 0x1 483 #define I2S_TX_HUNG_INT_ENA_S 7 484 /* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 485 /*description: The interrupt enable bit for the i2s_rx_hung_int interrupt*/ 486 #define I2S_RX_HUNG_INT_ENA (BIT(6)) 487 #define I2S_RX_HUNG_INT_ENA_M (BIT(6)) 488 #define I2S_RX_HUNG_INT_ENA_V 0x1 489 #define I2S_RX_HUNG_INT_ENA_S 6 490 /* I2S_TX_REMPTY_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 491 /*description: The interrupt enable bit for the i2s_tx_rempty_int interrupt*/ 492 #define I2S_TX_REMPTY_INT_ENA (BIT(5)) 493 #define I2S_TX_REMPTY_INT_ENA_M (BIT(5)) 494 #define I2S_TX_REMPTY_INT_ENA_V 0x1 495 #define I2S_TX_REMPTY_INT_ENA_S 5 496 /* I2S_TX_WFULL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 497 /*description: The interrupt enable bit for the i2s_tx_wfull_int interrupt*/ 498 #define I2S_TX_WFULL_INT_ENA (BIT(4)) 499 #define I2S_TX_WFULL_INT_ENA_M (BIT(4)) 500 #define I2S_TX_WFULL_INT_ENA_V 0x1 501 #define I2S_TX_WFULL_INT_ENA_S 4 502 /* I2S_RX_REMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 503 /*description: The interrupt enable bit for the i2s_rx_rempty_int interrupt*/ 504 #define I2S_RX_REMPTY_INT_ENA (BIT(3)) 505 #define I2S_RX_REMPTY_INT_ENA_M (BIT(3)) 506 #define I2S_RX_REMPTY_INT_ENA_V 0x1 507 #define I2S_RX_REMPTY_INT_ENA_S 3 508 /* I2S_RX_WFULL_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 509 /*description: The interrupt enable bit for the i2s_rx_wfull_int interrupt*/ 510 #define I2S_RX_WFULL_INT_ENA (BIT(2)) 511 #define I2S_RX_WFULL_INT_ENA_M (BIT(2)) 512 #define I2S_RX_WFULL_INT_ENA_V 0x1 513 #define I2S_RX_WFULL_INT_ENA_S 2 514 /* I2S_TX_PUT_DATA_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 515 /*description: The interrupt enable bit for the i2s_tx_put_data_int interrupt*/ 516 #define I2S_TX_PUT_DATA_INT_ENA (BIT(1)) 517 #define I2S_TX_PUT_DATA_INT_ENA_M (BIT(1)) 518 #define I2S_TX_PUT_DATA_INT_ENA_V 0x1 519 #define I2S_TX_PUT_DATA_INT_ENA_S 1 520 /* I2S_RX_TAKE_DATA_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 521 /*description: The interrupt enable bit for the i2s_rx_take_data_int interrupt*/ 522 #define I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) 523 #define I2S_RX_TAKE_DATA_INT_ENA_M (BIT(0)) 524 #define I2S_RX_TAKE_DATA_INT_ENA_V 0x1 525 #define I2S_RX_TAKE_DATA_INT_ENA_S 0 526 527 #define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) 528 /* I2S_V_SYNC_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ 529 /*description: Set this bit to clear the i2s_v_sync_int interrupt*/ 530 #define I2S_V_SYNC_INT_CLR (BIT(17)) 531 #define I2S_V_SYNC_INT_CLR_M (BIT(17)) 532 #define I2S_V_SYNC_INT_CLR_V 0x1 533 #define I2S_V_SYNC_INT_CLR_S 17 534 /* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 535 /*description: Set this bit to clear the i2s_out_total_eof_int interrupt*/ 536 #define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16)) 537 #define I2S_OUT_TOTAL_EOF_INT_CLR_M (BIT(16)) 538 #define I2S_OUT_TOTAL_EOF_INT_CLR_V 0x1 539 #define I2S_OUT_TOTAL_EOF_INT_CLR_S 16 540 /* I2S_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 541 /*description: Set this bit to clear the i2s_in_dscr_empty_int interrupt*/ 542 #define I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15)) 543 #define I2S_IN_DSCR_EMPTY_INT_CLR_M (BIT(15)) 544 #define I2S_IN_DSCR_EMPTY_INT_CLR_V 0x1 545 #define I2S_IN_DSCR_EMPTY_INT_CLR_S 15 546 /* I2S_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ 547 /*description: Set this bit to clear the i2s_out_dscr_err_int interrupt*/ 548 #define I2S_OUT_DSCR_ERR_INT_CLR (BIT(14)) 549 #define I2S_OUT_DSCR_ERR_INT_CLR_M (BIT(14)) 550 #define I2S_OUT_DSCR_ERR_INT_CLR_V 0x1 551 #define I2S_OUT_DSCR_ERR_INT_CLR_S 14 552 /* I2S_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ 553 /*description: Set this bit to clear the i2s_in_dscr_err_int interrupt*/ 554 #define I2S_IN_DSCR_ERR_INT_CLR (BIT(13)) 555 #define I2S_IN_DSCR_ERR_INT_CLR_M (BIT(13)) 556 #define I2S_IN_DSCR_ERR_INT_CLR_V 0x1 557 #define I2S_IN_DSCR_ERR_INT_CLR_S 13 558 /* I2S_OUT_EOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 559 /*description: Set this bit to clear the i2s_out_eof_int interrupt*/ 560 #define I2S_OUT_EOF_INT_CLR (BIT(12)) 561 #define I2S_OUT_EOF_INT_CLR_M (BIT(12)) 562 #define I2S_OUT_EOF_INT_CLR_V 0x1 563 #define I2S_OUT_EOF_INT_CLR_S 12 564 /* I2S_OUT_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 565 /*description: Set this bit to clear the i2s_out_done_int interrupt*/ 566 #define I2S_OUT_DONE_INT_CLR (BIT(11)) 567 #define I2S_OUT_DONE_INT_CLR_M (BIT(11)) 568 #define I2S_OUT_DONE_INT_CLR_V 0x1 569 #define I2S_OUT_DONE_INT_CLR_S 11 570 /* I2S_IN_ERR_EOF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 571 /*description: don't use*/ 572 #define I2S_IN_ERR_EOF_INT_CLR (BIT(10)) 573 #define I2S_IN_ERR_EOF_INT_CLR_M (BIT(10)) 574 #define I2S_IN_ERR_EOF_INT_CLR_V 0x1 575 #define I2S_IN_ERR_EOF_INT_CLR_S 10 576 /* I2S_IN_SUC_EOF_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 577 /*description: Set this bit to clear the i2s_in_suc_eof_int interrupt*/ 578 #define I2S_IN_SUC_EOF_INT_CLR (BIT(9)) 579 #define I2S_IN_SUC_EOF_INT_CLR_M (BIT(9)) 580 #define I2S_IN_SUC_EOF_INT_CLR_V 0x1 581 #define I2S_IN_SUC_EOF_INT_CLR_S 9 582 /* I2S_IN_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 583 /*description: Set this bit to clear the i2s_in_done_int interrupt*/ 584 #define I2S_IN_DONE_INT_CLR (BIT(8)) 585 #define I2S_IN_DONE_INT_CLR_M (BIT(8)) 586 #define I2S_IN_DONE_INT_CLR_V 0x1 587 #define I2S_IN_DONE_INT_CLR_S 8 588 /* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 589 /*description: Set this bit to clear the i2s_tx_hung_int interrupt*/ 590 #define I2S_TX_HUNG_INT_CLR (BIT(7)) 591 #define I2S_TX_HUNG_INT_CLR_M (BIT(7)) 592 #define I2S_TX_HUNG_INT_CLR_V 0x1 593 #define I2S_TX_HUNG_INT_CLR_S 7 594 /* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 595 /*description: Set this bit to clear the i2s_rx_hung_int interrupt*/ 596 #define I2S_RX_HUNG_INT_CLR (BIT(6)) 597 #define I2S_RX_HUNG_INT_CLR_M (BIT(6)) 598 #define I2S_RX_HUNG_INT_CLR_V 0x1 599 #define I2S_RX_HUNG_INT_CLR_S 6 600 /* I2S_TX_REMPTY_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 601 /*description: Set this bit to clear the i2s_tx_rempty_int interrupt*/ 602 #define I2S_TX_REMPTY_INT_CLR (BIT(5)) 603 #define I2S_TX_REMPTY_INT_CLR_M (BIT(5)) 604 #define I2S_TX_REMPTY_INT_CLR_V 0x1 605 #define I2S_TX_REMPTY_INT_CLR_S 5 606 /* I2S_TX_WFULL_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 607 /*description: Set this bit to clear the i2s_tx_wfull_int interrupt*/ 608 #define I2S_TX_WFULL_INT_CLR (BIT(4)) 609 #define I2S_TX_WFULL_INT_CLR_M (BIT(4)) 610 #define I2S_TX_WFULL_INT_CLR_V 0x1 611 #define I2S_TX_WFULL_INT_CLR_S 4 612 /* I2S_RX_REMPTY_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 613 /*description: Set this bit to clear the i2s_rx_rempty_int interrupt*/ 614 #define I2S_RX_REMPTY_INT_CLR (BIT(3)) 615 #define I2S_RX_REMPTY_INT_CLR_M (BIT(3)) 616 #define I2S_RX_REMPTY_INT_CLR_V 0x1 617 #define I2S_RX_REMPTY_INT_CLR_S 3 618 /* I2S_RX_WFULL_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 619 /*description: Set this bit to clear the i2s_rx_wfull_int interrupt*/ 620 #define I2S_RX_WFULL_INT_CLR (BIT(2)) 621 #define I2S_RX_WFULL_INT_CLR_M (BIT(2)) 622 #define I2S_RX_WFULL_INT_CLR_V 0x1 623 #define I2S_RX_WFULL_INT_CLR_S 2 624 /* I2S_PUT_DATA_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 625 /*description: Set this bit to clear the i2s_tx_put_data_int interrupt*/ 626 #define I2S_PUT_DATA_INT_CLR (BIT(1)) 627 #define I2S_PUT_DATA_INT_CLR_M (BIT(1)) 628 #define I2S_PUT_DATA_INT_CLR_V 0x1 629 #define I2S_PUT_DATA_INT_CLR_S 1 630 /* I2S_TAKE_DATA_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 631 /*description: Set this bit to clear the i2s_rx_take_data_int interrupt*/ 632 #define I2S_TAKE_DATA_INT_CLR (BIT(0)) 633 #define I2S_TAKE_DATA_INT_CLR_M (BIT(0)) 634 #define I2S_TAKE_DATA_INT_CLR_V 0x1 635 #define I2S_TAKE_DATA_INT_CLR_S 0 636 637 #define I2S_TIMING_REG(i) (REG_I2S_BASE(i) + 0x001c) 638 /* I2S_TX_BCK_IN_INV : R/W ;bitpos:[24] ;default: 1'b0 ; */ 639 /*description: Set this bit to invert BCK signal input to the slave transmitter*/ 640 #define I2S_TX_BCK_IN_INV (BIT(24)) 641 #define I2S_TX_BCK_IN_INV_M (BIT(24)) 642 #define I2S_TX_BCK_IN_INV_V 0x1 643 #define I2S_TX_BCK_IN_INV_S 24 644 /* I2S_DATA_ENABLE_DELAY : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ 645 /*description: Number of delay cycles for data valid flag.*/ 646 #define I2S_DATA_ENABLE_DELAY 0x00000003 647 #define I2S_DATA_ENABLE_DELAY_M ((I2S_DATA_ENABLE_DELAY_V)<<(I2S_DATA_ENABLE_DELAY_S)) 648 #define I2S_DATA_ENABLE_DELAY_V 0x3 649 #define I2S_DATA_ENABLE_DELAY_S 22 650 /* I2S_RX_DSYNC_SW : R/W ;bitpos:[21] ;default: 1'b0 ; */ 651 /*description: Set this bit to synchronize signals with the double sync method 652 into the receiver*/ 653 #define I2S_RX_DSYNC_SW (BIT(21)) 654 #define I2S_RX_DSYNC_SW_M (BIT(21)) 655 #define I2S_RX_DSYNC_SW_V 0x1 656 #define I2S_RX_DSYNC_SW_S 21 657 /* I2S_TX_DSYNC_SW : R/W ;bitpos:[20] ;default: 1'b0 ; */ 658 /*description: Set this bit to synchronize signals with the double sync method 659 into the transmitter*/ 660 #define I2S_TX_DSYNC_SW (BIT(20)) 661 #define I2S_TX_DSYNC_SW_M (BIT(20)) 662 #define I2S_TX_DSYNC_SW_V 0x1 663 #define I2S_TX_DSYNC_SW_S 20 664 /* I2S_RX_BCK_OUT_DELAY : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ 665 /*description: Number of delay cycles for BCK out of the receiver*/ 666 #define I2S_RX_BCK_OUT_DELAY 0x00000003 667 #define I2S_RX_BCK_OUT_DELAY_M ((I2S_RX_BCK_OUT_DELAY_V)<<(I2S_RX_BCK_OUT_DELAY_S)) 668 #define I2S_RX_BCK_OUT_DELAY_V 0x3 669 #define I2S_RX_BCK_OUT_DELAY_S 18 670 /* I2S_RX_WS_OUT_DELAY : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ 671 /*description: Number of delay cycles for WS out of the receiver*/ 672 #define I2S_RX_WS_OUT_DELAY 0x00000003 673 #define I2S_RX_WS_OUT_DELAY_M ((I2S_RX_WS_OUT_DELAY_V)<<(I2S_RX_WS_OUT_DELAY_S)) 674 #define I2S_RX_WS_OUT_DELAY_V 0x3 675 #define I2S_RX_WS_OUT_DELAY_S 16 676 /* I2S_TX_SD_OUT_DELAY : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ 677 /*description: Number of delay cycles for SD out of the transmitter*/ 678 #define I2S_TX_SD_OUT_DELAY 0x00000003 679 #define I2S_TX_SD_OUT_DELAY_M ((I2S_TX_SD_OUT_DELAY_V)<<(I2S_TX_SD_OUT_DELAY_S)) 680 #define I2S_TX_SD_OUT_DELAY_V 0x3 681 #define I2S_TX_SD_OUT_DELAY_S 14 682 /* I2S_TX_WS_OUT_DELAY : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ 683 /*description: Number of delay cycles for WS out of the transmitter*/ 684 #define I2S_TX_WS_OUT_DELAY 0x00000003 685 #define I2S_TX_WS_OUT_DELAY_M ((I2S_TX_WS_OUT_DELAY_V)<<(I2S_TX_WS_OUT_DELAY_S)) 686 #define I2S_TX_WS_OUT_DELAY_V 0x3 687 #define I2S_TX_WS_OUT_DELAY_S 12 688 /* I2S_TX_BCK_OUT_DELAY : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ 689 /*description: Number of delay cycles for BCK out of the transmitter*/ 690 #define I2S_TX_BCK_OUT_DELAY 0x00000003 691 #define I2S_TX_BCK_OUT_DELAY_M ((I2S_TX_BCK_OUT_DELAY_V)<<(I2S_TX_BCK_OUT_DELAY_S)) 692 #define I2S_TX_BCK_OUT_DELAY_V 0x3 693 #define I2S_TX_BCK_OUT_DELAY_S 10 694 /* I2S_RX_SD_IN_DELAY : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ 695 /*description: Number of delay cycles for SD into the receiver*/ 696 #define I2S_RX_SD_IN_DELAY 0x00000003 697 #define I2S_RX_SD_IN_DELAY_M ((I2S_RX_SD_IN_DELAY_V)<<(I2S_RX_SD_IN_DELAY_S)) 698 #define I2S_RX_SD_IN_DELAY_V 0x3 699 #define I2S_RX_SD_IN_DELAY_S 8 700 /* I2S_RX_WS_IN_DELAY : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ 701 /*description: Number of delay cycles for WS into the receiver*/ 702 #define I2S_RX_WS_IN_DELAY 0x00000003 703 #define I2S_RX_WS_IN_DELAY_M ((I2S_RX_WS_IN_DELAY_V)<<(I2S_RX_WS_IN_DELAY_S)) 704 #define I2S_RX_WS_IN_DELAY_V 0x3 705 #define I2S_RX_WS_IN_DELAY_S 6 706 /* I2S_RX_BCK_IN_DELAY : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ 707 /*description: Number of delay cycles for BCK into the receiver*/ 708 #define I2S_RX_BCK_IN_DELAY 0x00000003 709 #define I2S_RX_BCK_IN_DELAY_M ((I2S_RX_BCK_IN_DELAY_V)<<(I2S_RX_BCK_IN_DELAY_S)) 710 #define I2S_RX_BCK_IN_DELAY_V 0x3 711 #define I2S_RX_BCK_IN_DELAY_S 4 712 /* I2S_TX_WS_IN_DELAY : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ 713 /*description: Number of delay cycles for WS into the transmitter*/ 714 #define I2S_TX_WS_IN_DELAY 0x00000003 715 #define I2S_TX_WS_IN_DELAY_M ((I2S_TX_WS_IN_DELAY_V)<<(I2S_TX_WS_IN_DELAY_S)) 716 #define I2S_TX_WS_IN_DELAY_V 0x3 717 #define I2S_TX_WS_IN_DELAY_S 2 718 /* I2S_TX_BCK_IN_DELAY : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 719 /*description: Number of delay cycles for BCK into the transmitter*/ 720 #define I2S_TX_BCK_IN_DELAY 0x00000003 721 #define I2S_TX_BCK_IN_DELAY_M ((I2S_TX_BCK_IN_DELAY_V)<<(I2S_TX_BCK_IN_DELAY_S)) 722 #define I2S_TX_BCK_IN_DELAY_V 0x3 723 #define I2S_TX_BCK_IN_DELAY_S 0 724 725 #define I2S_FIFO_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) 726 /* I2S_TX_24MSB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ 727 /*description: Only useful in tx 24bit mode. 1: the high 24 bits are effective 728 in i2s fifo 0: the low 24 bits are effective in i2s fifo*/ 729 #define I2S_TX_24MSB_EN (BIT(23)) 730 #define I2S_TX_24MSB_EN_M (BIT(23)) 731 #define I2S_TX_24MSB_EN_V 0x1 732 #define I2S_TX_24MSB_EN_S 23 733 /* I2S_RX_24MSB_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ 734 /*description: Only useful in rx 24bit mode. 1: the high 24 bits are effective 735 in i2s fifo 0: the low 24 bits are effective in i2s fifo*/ 736 #define I2S_RX_24MSB_EN (BIT(22)) 737 #define I2S_RX_24MSB_EN_M (BIT(22)) 738 #define I2S_RX_24MSB_EN_V 0x1 739 #define I2S_RX_24MSB_EN_S 22 740 /* I2S_RX_FIFO_SYNC : R/W ;bitpos:[21] ;default: 1'b0 ; */ 741 /*description: force write back rx data to memory*/ 742 #define I2S_RX_FIFO_SYNC (BIT(21)) 743 #define I2S_RX_FIFO_SYNC_M (BIT(21)) 744 #define I2S_RX_FIFO_SYNC_V 0x1 745 #define I2S_RX_FIFO_SYNC_S 21 746 /* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 747 /*description: The bit should always be set to 1*/ 748 #define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20)) 749 #define I2S_RX_FIFO_MOD_FORCE_EN_M (BIT(20)) 750 #define I2S_RX_FIFO_MOD_FORCE_EN_V 0x1 751 #define I2S_RX_FIFO_MOD_FORCE_EN_S 20 752 /* I2S_TX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 753 /*description: The bit should always be set to 1*/ 754 #define I2S_TX_FIFO_MOD_FORCE_EN (BIT(19)) 755 #define I2S_TX_FIFO_MOD_FORCE_EN_M (BIT(19)) 756 #define I2S_TX_FIFO_MOD_FORCE_EN_V 0x1 757 #define I2S_TX_FIFO_MOD_FORCE_EN_S 19 758 /* I2S_RX_FIFO_MOD : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ 759 /*description: Receiver FIFO mode configuration bits*/ 760 #define I2S_RX_FIFO_MOD 0x00000007 761 #define I2S_RX_FIFO_MOD_M ((I2S_RX_FIFO_MOD_V)<<(I2S_RX_FIFO_MOD_S)) 762 #define I2S_RX_FIFO_MOD_V 0x7 763 #define I2S_RX_FIFO_MOD_S 16 764 /* I2S_TX_FIFO_MOD : R/W ;bitpos:[15:13] ;default: 3'b0 ; */ 765 /*description: Transmitter FIFO mode configuration bits*/ 766 #define I2S_TX_FIFO_MOD 0x00000007 767 #define I2S_TX_FIFO_MOD_M ((I2S_TX_FIFO_MOD_V)<<(I2S_TX_FIFO_MOD_S)) 768 #define I2S_TX_FIFO_MOD_V 0x7 769 #define I2S_TX_FIFO_MOD_S 13 770 /* I2S_DSCR_EN : R/W ;bitpos:[12] ;default: 1'd1 ; */ 771 /*description: Set this bit to enable I2S DMA mode*/ 772 #define I2S_DSCR_EN (BIT(12)) 773 #define I2S_DSCR_EN_M (BIT(12)) 774 #define I2S_DSCR_EN_V 0x1 775 #define I2S_DSCR_EN_S 12 776 /* I2S_TX_DATA_NUM : R/W ;bitpos:[11:6] ;default: 6'd32 ; */ 777 /*description: Threshold of data length in transmitter FIFO*/ 778 #define I2S_TX_DATA_NUM 0x0000003F 779 #define I2S_TX_DATA_NUM_M ((I2S_TX_DATA_NUM_V)<<(I2S_TX_DATA_NUM_S)) 780 #define I2S_TX_DATA_NUM_V 0x3F 781 #define I2S_TX_DATA_NUM_S 6 782 /* I2S_RX_DATA_NUM : R/W ;bitpos:[5:0] ;default: 6'd32 ; */ 783 /*description: Threshold of data length in receiver FIFO*/ 784 #define I2S_RX_DATA_NUM 0x0000003F 785 #define I2S_RX_DATA_NUM_M ((I2S_RX_DATA_NUM_V)<<(I2S_RX_DATA_NUM_S)) 786 #define I2S_RX_DATA_NUM_V 0x3F 787 #define I2S_RX_DATA_NUM_S 0 788 789 #define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0024) 790 /* I2S_RX_EOF_NUM : R/W ;bitpos:[31:0] ;default: 32'd64 ; */ 791 /*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ 792 #define I2S_RX_EOF_NUM 0xFFFFFFFF 793 #define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) 794 #define I2S_RX_EOF_NUM_V 0xFFFFFFFF 795 #define I2S_RX_EOF_NUM_S 0 796 797 #define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0028) 798 /* I2S_SIGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 799 /*description: the right channel or left channel put out constant value stored 800 in this register according to tx_chan_mod and reg_tx_msb_right*/ 801 #define I2S_SIGLE_DATA 0xFFFFFFFF 802 #define I2S_SIGLE_DATA_M ((I2S_SIGLE_DATA_V)<<(I2S_SIGLE_DATA_S)) 803 #define I2S_SIGLE_DATA_V 0xFFFFFFFF 804 #define I2S_SIGLE_DATA_S 0 805 806 #define I2S_CONF_CHAN_REG(i) (REG_I2S_BASE(i) + 0x002c) 807 /* I2S_RX_CHAN_MOD : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ 808 /*description: I2S receiver channel mode configuration bits.*/ 809 #define I2S_RX_CHAN_MOD 0x00000003 810 #define I2S_RX_CHAN_MOD_M ((I2S_RX_CHAN_MOD_V)<<(I2S_RX_CHAN_MOD_S)) 811 #define I2S_RX_CHAN_MOD_V 0x3 812 #define I2S_RX_CHAN_MOD_S 3 813 /* I2S_TX_CHAN_MOD : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 814 /*description: I2S transmitter channel mode configuration bits.*/ 815 #define I2S_TX_CHAN_MOD 0x00000007 816 #define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) 817 #define I2S_TX_CHAN_MOD_V 0x7 818 #define I2S_TX_CHAN_MOD_S 0 819 820 #define I2S_OUT_LINK_REG(i) (REG_I2S_BASE(i) + 0x0030) 821 /* I2S_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ 822 /*description: */ 823 #define I2S_OUTLINK_PARK (BIT(31)) 824 #define I2S_OUTLINK_PARK_M (BIT(31)) 825 #define I2S_OUTLINK_PARK_V 0x1 826 #define I2S_OUTLINK_PARK_S 31 827 /* I2S_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ 828 /*description: Set this bit to restart outlink descriptor*/ 829 #define I2S_OUTLINK_RESTART (BIT(30)) 830 #define I2S_OUTLINK_RESTART_M (BIT(30)) 831 #define I2S_OUTLINK_RESTART_V 0x1 832 #define I2S_OUTLINK_RESTART_S 30 833 /* I2S_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ 834 /*description: Set this bit to start outlink descriptor*/ 835 #define I2S_OUTLINK_START (BIT(29)) 836 #define I2S_OUTLINK_START_M (BIT(29)) 837 #define I2S_OUTLINK_START_V 0x1 838 #define I2S_OUTLINK_START_S 29 839 /* I2S_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ 840 /*description: Set this bit to stop outlink descriptor*/ 841 #define I2S_OUTLINK_STOP (BIT(28)) 842 #define I2S_OUTLINK_STOP_M (BIT(28)) 843 #define I2S_OUTLINK_STOP_V 0x1 844 #define I2S_OUTLINK_STOP_S 28 845 /* I2S_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 846 /*description: The address of first outlink descriptor*/ 847 #define I2S_OUTLINK_ADDR 0x000FFFFF 848 #define I2S_OUTLINK_ADDR_M ((I2S_OUTLINK_ADDR_V)<<(I2S_OUTLINK_ADDR_S)) 849 #define I2S_OUTLINK_ADDR_V 0xFFFFF 850 #define I2S_OUTLINK_ADDR_S 0 851 852 #define I2S_IN_LINK_REG(i) (REG_I2S_BASE(i) + 0x0034) 853 /* I2S_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ 854 /*description: */ 855 #define I2S_INLINK_PARK (BIT(31)) 856 #define I2S_INLINK_PARK_M (BIT(31)) 857 #define I2S_INLINK_PARK_V 0x1 858 #define I2S_INLINK_PARK_S 31 859 /* I2S_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ 860 /*description: Set this bit to restart inlink descriptor*/ 861 #define I2S_INLINK_RESTART (BIT(30)) 862 #define I2S_INLINK_RESTART_M (BIT(30)) 863 #define I2S_INLINK_RESTART_V 0x1 864 #define I2S_INLINK_RESTART_S 30 865 /* I2S_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ 866 /*description: Set this bit to start inlink descriptor*/ 867 #define I2S_INLINK_START (BIT(29)) 868 #define I2S_INLINK_START_M (BIT(29)) 869 #define I2S_INLINK_START_V 0x1 870 #define I2S_INLINK_START_S 29 871 /* I2S_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ 872 /*description: Set this bit to stop inlink descriptor*/ 873 #define I2S_INLINK_STOP (BIT(28)) 874 #define I2S_INLINK_STOP_M (BIT(28)) 875 #define I2S_INLINK_STOP_V 0x1 876 #define I2S_INLINK_STOP_S 28 877 /* I2S_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 878 /*description: The address of first inlink descriptor*/ 879 #define I2S_INLINK_ADDR 0x000FFFFF 880 #define I2S_INLINK_ADDR_M ((I2S_INLINK_ADDR_V)<<(I2S_INLINK_ADDR_S)) 881 #define I2S_INLINK_ADDR_V 0xFFFFF 882 #define I2S_INLINK_ADDR_S 0 883 884 #define I2S_OUT_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0038) 885 /* I2S_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 886 /*description: The address of outlink descriptor that produces EOF*/ 887 #define I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF 888 #define I2S_OUT_EOF_DES_ADDR_M ((I2S_OUT_EOF_DES_ADDR_V)<<(I2S_OUT_EOF_DES_ADDR_S)) 889 #define I2S_OUT_EOF_DES_ADDR_V 0xFFFFFFFF 890 #define I2S_OUT_EOF_DES_ADDR_S 0 891 892 #define I2S_IN_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x003c) 893 /* I2S_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 894 /*description: The address of inlink descriptor that produces EOF*/ 895 #define I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF 896 #define I2S_IN_SUC_EOF_DES_ADDR_M ((I2S_IN_SUC_EOF_DES_ADDR_V)<<(I2S_IN_SUC_EOF_DES_ADDR_S)) 897 #define I2S_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF 898 #define I2S_IN_SUC_EOF_DES_ADDR_S 0 899 900 #define I2S_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0040) 901 /* I2S_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 902 /*description: The address of buffer relative to the outlink descriptor that produces EOF*/ 903 #define I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF 904 #define I2S_OUT_EOF_BFR_DES_ADDR_M ((I2S_OUT_EOF_BFR_DES_ADDR_V)<<(I2S_OUT_EOF_BFR_DES_ADDR_S)) 905 #define I2S_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF 906 #define I2S_OUT_EOF_BFR_DES_ADDR_S 0 907 908 #define I2S_AHB_TEST_REG(i) (REG_I2S_BASE(i) + 0x0044) 909 /* I2S_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ 910 /*description: */ 911 #define I2S_AHB_TESTADDR 0x00000003 912 #define I2S_AHB_TESTADDR_M ((I2S_AHB_TESTADDR_V)<<(I2S_AHB_TESTADDR_S)) 913 #define I2S_AHB_TESTADDR_V 0x3 914 #define I2S_AHB_TESTADDR_S 4 915 /* I2S_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 916 /*description: */ 917 #define I2S_AHB_TESTMODE 0x00000007 918 #define I2S_AHB_TESTMODE_M ((I2S_AHB_TESTMODE_V)<<(I2S_AHB_TESTMODE_S)) 919 #define I2S_AHB_TESTMODE_V 0x7 920 #define I2S_AHB_TESTMODE_S 0 921 922 #define I2S_INLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0048) 923 /* I2S_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 924 /*description: The address of current inlink descriptor*/ 925 #define I2S_INLINK_DSCR 0xFFFFFFFF 926 #define I2S_INLINK_DSCR_M ((I2S_INLINK_DSCR_V)<<(I2S_INLINK_DSCR_S)) 927 #define I2S_INLINK_DSCR_V 0xFFFFFFFF 928 #define I2S_INLINK_DSCR_S 0 929 930 #define I2S_INLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x004C) 931 /* I2S_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 932 /*description: The address of next inlink descriptor*/ 933 #define I2S_INLINK_DSCR_BF0 0xFFFFFFFF 934 #define I2S_INLINK_DSCR_BF0_M ((I2S_INLINK_DSCR_BF0_V)<<(I2S_INLINK_DSCR_BF0_S)) 935 #define I2S_INLINK_DSCR_BF0_V 0xFFFFFFFF 936 #define I2S_INLINK_DSCR_BF0_S 0 937 938 #define I2S_INLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x0050) 939 /* I2S_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 940 /*description: The address of next inlink data buffer*/ 941 #define I2S_INLINK_DSCR_BF1 0xFFFFFFFF 942 #define I2S_INLINK_DSCR_BF1_M ((I2S_INLINK_DSCR_BF1_V)<<(I2S_INLINK_DSCR_BF1_S)) 943 #define I2S_INLINK_DSCR_BF1_V 0xFFFFFFFF 944 #define I2S_INLINK_DSCR_BF1_S 0 945 946 #define I2S_OUTLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0054) 947 /* I2S_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 948 /*description: The address of current outlink descriptor*/ 949 #define I2S_OUTLINK_DSCR 0xFFFFFFFF 950 #define I2S_OUTLINK_DSCR_M ((I2S_OUTLINK_DSCR_V)<<(I2S_OUTLINK_DSCR_S)) 951 #define I2S_OUTLINK_DSCR_V 0xFFFFFFFF 952 #define I2S_OUTLINK_DSCR_S 0 953 954 #define I2S_OUTLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x0058) 955 /* I2S_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 956 /*description: The address of next outlink descriptor*/ 957 #define I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF 958 #define I2S_OUTLINK_DSCR_BF0_M ((I2S_OUTLINK_DSCR_BF0_V)<<(I2S_OUTLINK_DSCR_BF0_S)) 959 #define I2S_OUTLINK_DSCR_BF0_V 0xFFFFFFFF 960 #define I2S_OUTLINK_DSCR_BF0_S 0 961 962 #define I2S_OUTLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x005C) 963 /* I2S_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 964 /*description: The address of next outlink data buffer*/ 965 #define I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF 966 #define I2S_OUTLINK_DSCR_BF1_M ((I2S_OUTLINK_DSCR_BF1_V)<<(I2S_OUTLINK_DSCR_BF1_S)) 967 #define I2S_OUTLINK_DSCR_BF1_V 0xFFFFFFFF 968 #define I2S_OUTLINK_DSCR_BF1_S 0 969 970 #define I2S_LC_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) 971 /* I2S_EXT_MEM_BK_SIZE : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ 972 /*description: DMA access external memory block size. 0: 16 bytes 1: 32 973 bytes 2:64 bytes 3:reserved*/ 974 #define I2S_EXT_MEM_BK_SIZE 0x00000003 975 #define I2S_EXT_MEM_BK_SIZE_M ((I2S_EXT_MEM_BK_SIZE_V)<<(I2S_EXT_MEM_BK_SIZE_S)) 976 #define I2S_EXT_MEM_BK_SIZE_V 0x3 977 #define I2S_EXT_MEM_BK_SIZE_S 14 978 /* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ 979 /*description: don't use*/ 980 #define I2S_MEM_TRANS_EN (BIT(13)) 981 #define I2S_MEM_TRANS_EN_M (BIT(13)) 982 #define I2S_MEM_TRANS_EN_V 0x1 983 #define I2S_MEM_TRANS_EN_S 13 984 /* I2S_CHECK_OWNER : R/W ;bitpos:[12] ;default: 1'b0 ; */ 985 /*description: Set this bit to enable check owner bit by hardware*/ 986 #define I2S_CHECK_OWNER (BIT(12)) 987 #define I2S_CHECK_OWNER_M (BIT(12)) 988 #define I2S_CHECK_OWNER_V 0x1 989 #define I2S_CHECK_OWNER_S 12 990 /* I2S_OUT_DATA_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 991 /*description: Transmitter data transfer mode configuration bit. 1: to prepare 992 out data with burst mode 0: to prepare out data with byte mode*/ 993 #define I2S_OUT_DATA_BURST_EN (BIT(11)) 994 #define I2S_OUT_DATA_BURST_EN_M (BIT(11)) 995 #define I2S_OUT_DATA_BURST_EN_V 0x1 996 #define I2S_OUT_DATA_BURST_EN_S 11 997 /* I2S_INDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 998 /*description: DMA inlink descriptor transfer mode configuration bit. 1: to 999 prepare inlink descriptor with burst mode 0: to prepare inlink descriptor with byte mode*/ 1000 #define I2S_INDSCR_BURST_EN (BIT(10)) 1001 #define I2S_INDSCR_BURST_EN_M (BIT(10)) 1002 #define I2S_INDSCR_BURST_EN_V 0x1 1003 #define I2S_INDSCR_BURST_EN_S 10 1004 /* I2S_OUTDSCR_BURST_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1005 /*description: DMA outlink descriptor transfer mode configuration bit. 1: to 1006 prepare outlink descriptor with burst mode 0: to prepare outlink descriptor with byte mode*/ 1007 #define I2S_OUTDSCR_BURST_EN (BIT(9)) 1008 #define I2S_OUTDSCR_BURST_EN_M (BIT(9)) 1009 #define I2S_OUTDSCR_BURST_EN_V 0x1 1010 #define I2S_OUTDSCR_BURST_EN_S 9 1011 /* I2S_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */ 1012 /*description: DMA out EOF flag generation mode . 1: when dma has popped all 1013 data from the FIFO 0:when ahb has pushed all data to the FIFO*/ 1014 #define I2S_OUT_EOF_MODE (BIT(8)) 1015 #define I2S_OUT_EOF_MODE_M (BIT(8)) 1016 #define I2S_OUT_EOF_MODE_V 0x1 1017 #define I2S_OUT_EOF_MODE_S 8 1018 /* I2S_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1019 /*description: don't use*/ 1020 #define I2S_OUT_NO_RESTART_CLR (BIT(7)) 1021 #define I2S_OUT_NO_RESTART_CLR_M (BIT(7)) 1022 #define I2S_OUT_NO_RESTART_CLR_V 0x1 1023 #define I2S_OUT_NO_RESTART_CLR_S 7 1024 /* I2S_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1025 /*description: Set this bit to enable outlink-written-back automatically when 1026 out buffer is transmitted done.*/ 1027 #define I2S_OUT_AUTO_WRBACK (BIT(6)) 1028 #define I2S_OUT_AUTO_WRBACK_M (BIT(6)) 1029 #define I2S_OUT_AUTO_WRBACK_V 0x1 1030 #define I2S_OUT_AUTO_WRBACK_S 6 1031 /* I2S_IN_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1032 /*description: Set this bit to loop test outlink*/ 1033 #define I2S_IN_LOOP_TEST (BIT(5)) 1034 #define I2S_IN_LOOP_TEST_M (BIT(5)) 1035 #define I2S_IN_LOOP_TEST_V 0x1 1036 #define I2S_IN_LOOP_TEST_S 5 1037 /* I2S_OUT_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1038 /*description: Set this bit to loop test inlink*/ 1039 #define I2S_OUT_LOOP_TEST (BIT(4)) 1040 #define I2S_OUT_LOOP_TEST_M (BIT(4)) 1041 #define I2S_OUT_LOOP_TEST_V 0x1 1042 #define I2S_OUT_LOOP_TEST_S 4 1043 /* I2S_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1044 /*description: Set this bit to reset ahb interface of DMA*/ 1045 #define I2S_AHBM_RST (BIT(3)) 1046 #define I2S_AHBM_RST_M (BIT(3)) 1047 #define I2S_AHBM_RST_V 0x1 1048 #define I2S_AHBM_RST_S 3 1049 /* I2S_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1050 /*description: Set this bit to reset ahb interface cmdFIFO of DMA*/ 1051 #define I2S_AHBM_FIFO_RST (BIT(2)) 1052 #define I2S_AHBM_FIFO_RST_M (BIT(2)) 1053 #define I2S_AHBM_FIFO_RST_V 0x1 1054 #define I2S_AHBM_FIFO_RST_S 2 1055 /* I2S_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1056 /*description: Set this bit to reset out dma FSM*/ 1057 #define I2S_OUT_RST (BIT(1)) 1058 #define I2S_OUT_RST_M (BIT(1)) 1059 #define I2S_OUT_RST_V 0x1 1060 #define I2S_OUT_RST_S 1 1061 /* I2S_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ 1062 /*description: Set this bit to reset in dma FSM*/ 1063 #define I2S_IN_RST (BIT(0)) 1064 #define I2S_IN_RST_M (BIT(0)) 1065 #define I2S_IN_RST_V 0x1 1066 #define I2S_IN_RST_S 0 1067 1068 #define I2S_OUTFIFO_PUSH_REG(i) (REG_I2S_BASE(i) + 0x0064) 1069 /* I2S_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ 1070 /*description: */ 1071 #define I2S_OUTFIFO_PUSH (BIT(16)) 1072 #define I2S_OUTFIFO_PUSH_M (BIT(16)) 1073 #define I2S_OUTFIFO_PUSH_V 0x1 1074 #define I2S_OUTFIFO_PUSH_S 16 1075 /* I2S_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ 1076 /*description: */ 1077 #define I2S_OUTFIFO_WDATA 0x000001FF 1078 #define I2S_OUTFIFO_WDATA_M ((I2S_OUTFIFO_WDATA_V)<<(I2S_OUTFIFO_WDATA_S)) 1079 #define I2S_OUTFIFO_WDATA_V 0x1FF 1080 #define I2S_OUTFIFO_WDATA_S 0 1081 1082 #define I2S_INFIFO_POP_REG(i) (REG_I2S_BASE(i) + 0x0068) 1083 /* I2S_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ 1084 /*description: */ 1085 #define I2S_INFIFO_POP (BIT(16)) 1086 #define I2S_INFIFO_POP_M (BIT(16)) 1087 #define I2S_INFIFO_POP_V 0x1 1088 #define I2S_INFIFO_POP_S 16 1089 /* I2S_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */ 1090 /*description: */ 1091 #define I2S_INFIFO_RDATA 0x00000FFF 1092 #define I2S_INFIFO_RDATA_M ((I2S_INFIFO_RDATA_V)<<(I2S_INFIFO_RDATA_S)) 1093 #define I2S_INFIFO_RDATA_V 0xFFF 1094 #define I2S_INFIFO_RDATA_S 0 1095 1096 #define I2S_LC_STATE0_REG(i) (REG_I2S_BASE(i) + 0x006C) 1097 /* I2S_OUT_EMPTY : RO ;bitpos:[31] ;default: 1'h0 ; */ 1098 /*description: DMA transmitter status register*/ 1099 #define I2S_OUT_EMPTY (BIT(31)) 1100 #define I2S_OUT_EMPTY_M (BIT(31)) 1101 #define I2S_OUT_EMPTY_V 0x1 1102 #define I2S_OUT_EMPTY_S 31 1103 /* I2S_OUT_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */ 1104 /*description: */ 1105 #define I2S_OUT_FULL (BIT(30)) 1106 #define I2S_OUT_FULL_M (BIT(30)) 1107 #define I2S_OUT_FULL_V 0x1 1108 #define I2S_OUT_FULL_S 30 1109 /* I2S_OUTFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */ 1110 /*description: */ 1111 #define I2S_OUTFIFO_CNT 0x0000007F 1112 #define I2S_OUTFIFO_CNT_M ((I2S_OUTFIFO_CNT_V)<<(I2S_OUTFIFO_CNT_S)) 1113 #define I2S_OUTFIFO_CNT_V 0x7F 1114 #define I2S_OUTFIFO_CNT_S 23 1115 /* I2S_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ 1116 /*description: */ 1117 #define I2S_OUT_STATE 0x00000007 1118 #define I2S_OUT_STATE_M ((I2S_OUT_STATE_V)<<(I2S_OUT_STATE_S)) 1119 #define I2S_OUT_STATE_V 0x7 1120 #define I2S_OUT_STATE_S 20 1121 /* I2S_OUT_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ 1122 /*description: */ 1123 #define I2S_OUT_DSCR_STATE 0x00000003 1124 #define I2S_OUT_DSCR_STATE_M ((I2S_OUT_DSCR_STATE_V)<<(I2S_OUT_DSCR_STATE_S)) 1125 #define I2S_OUT_DSCR_STATE_V 0x3 1126 #define I2S_OUT_DSCR_STATE_S 18 1127 /* I2S_OUTLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'h0 ; */ 1128 /*description: */ 1129 #define I2S_OUTLINK_DSCR_ADDR 0x0003FFFF 1130 #define I2S_OUTLINK_DSCR_ADDR_M ((I2S_OUTLINK_DSCR_ADDR_V)<<(I2S_OUTLINK_DSCR_ADDR_S)) 1131 #define I2S_OUTLINK_DSCR_ADDR_V 0x3FFFF 1132 #define I2S_OUTLINK_DSCR_ADDR_S 0 1133 1134 #define I2S_LC_STATE1_REG(i) (REG_I2S_BASE(i) + 0x0070) 1135 /* I2S_IN_EMPTY : RO ;bitpos:[31] ;default: 1'h0 ; */ 1136 /*description: DMA receiver status register*/ 1137 #define I2S_IN_EMPTY (BIT(31)) 1138 #define I2S_IN_EMPTY_M (BIT(31)) 1139 #define I2S_IN_EMPTY_V 0x1 1140 #define I2S_IN_EMPTY_S 31 1141 /* I2S_IN_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */ 1142 /*description: */ 1143 #define I2S_IN_FULL (BIT(30)) 1144 #define I2S_IN_FULL_M (BIT(30)) 1145 #define I2S_IN_FULL_V 0x1 1146 #define I2S_IN_FULL_S 30 1147 /* I2S_INFIFO_CNT_DEBUG : RO ;bitpos:[29:23] ;default: 7'b0 ; */ 1148 /*description: */ 1149 #define I2S_INFIFO_CNT_DEBUG 0x0000007F 1150 #define I2S_INFIFO_CNT_DEBUG_M ((I2S_INFIFO_CNT_DEBUG_V)<<(I2S_INFIFO_CNT_DEBUG_S)) 1151 #define I2S_INFIFO_CNT_DEBUG_V 0x7F 1152 #define I2S_INFIFO_CNT_DEBUG_S 23 1153 /* I2S_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ 1154 /*description: */ 1155 #define I2S_IN_STATE 0x00000007 1156 #define I2S_IN_STATE_M ((I2S_IN_STATE_V)<<(I2S_IN_STATE_S)) 1157 #define I2S_IN_STATE_V 0x7 1158 #define I2S_IN_STATE_S 20 1159 /* I2S_IN_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ 1160 /*description: */ 1161 #define I2S_IN_DSCR_STATE 0x00000003 1162 #define I2S_IN_DSCR_STATE_M ((I2S_IN_DSCR_STATE_V)<<(I2S_IN_DSCR_STATE_S)) 1163 #define I2S_IN_DSCR_STATE_V 0x3 1164 #define I2S_IN_DSCR_STATE_S 18 1165 /* I2S_INLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'h0 ; */ 1166 /*description: */ 1167 #define I2S_INLINK_DSCR_ADDR 0x0003FFFF 1168 #define I2S_INLINK_DSCR_ADDR_M ((I2S_INLINK_DSCR_ADDR_V)<<(I2S_INLINK_DSCR_ADDR_S)) 1169 #define I2S_INLINK_DSCR_ADDR_V 0x3FFFF 1170 #define I2S_INLINK_DSCR_ADDR_S 0 1171 1172 #define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0074) 1173 /* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1174 /*description: The enable bit for FIFO timeout*/ 1175 #define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) 1176 #define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) 1177 #define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 1178 #define I2S_LC_FIFO_TIMEOUT_ENA_S 11 1179 /* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ 1180 /*description: The bits are used to scale tick counter threshold. The tick counter 1181 is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ 1182 #define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 1183 #define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) 1184 #define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 1185 #define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 1186 /* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ 1187 /*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt 1188 will be triggered when fifo hung counter is equal to this value*/ 1189 #define I2S_LC_FIFO_TIMEOUT 0x000000FF 1190 #define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) 1191 #define I2S_LC_FIFO_TIMEOUT_V 0xFF 1192 #define I2S_LC_FIFO_TIMEOUT_S 0 1193 1194 #define I2S_CONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0) 1195 /* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ 1196 /*description: don't use*/ 1197 #define I2S_TX_ZEROS_RM_EN (BIT(9)) 1198 #define I2S_TX_ZEROS_RM_EN_M (BIT(9)) 1199 #define I2S_TX_ZEROS_RM_EN_V 0x1 1200 #define I2S_TX_ZEROS_RM_EN_S 9 1201 /* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1202 /*description: Set this bit to stop disable output BCK signal and WS signal 1203 when tx FIFO is emtpy*/ 1204 #define I2S_TX_STOP_EN (BIT(8)) 1205 #define I2S_TX_STOP_EN_M (BIT(8)) 1206 #define I2S_TX_STOP_EN_V 0x1 1207 #define I2S_TX_STOP_EN_S 8 1208 /* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */ 1209 /*description: Set this bit to bypass Compress/Decompress module for received data.*/ 1210 #define I2S_RX_PCM_BYPASS (BIT(7)) 1211 #define I2S_RX_PCM_BYPASS_M (BIT(7)) 1212 #define I2S_RX_PCM_BYPASS_V 0x1 1213 #define I2S_RX_PCM_BYPASS_S 7 1214 /* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ 1215 /*description: Compress/Decompress module configuration bits. 0: decompress 1216 received data 1:compress received data*/ 1217 #define I2S_RX_PCM_CONF 0x00000007 1218 #define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) 1219 #define I2S_RX_PCM_CONF_V 0x7 1220 #define I2S_RX_PCM_CONF_S 4 1221 /* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */ 1222 /*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/ 1223 #define I2S_TX_PCM_BYPASS (BIT(3)) 1224 #define I2S_TX_PCM_BYPASS_M (BIT(3)) 1225 #define I2S_TX_PCM_BYPASS_V 0x1 1226 #define I2S_TX_PCM_BYPASS_S 3 1227 /* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */ 1228 /*description: Compress/Decompress module configuration bits. 0: decompress 1229 transmitted data 1:compress transmitted data*/ 1230 #define I2S_TX_PCM_CONF 0x00000007 1231 #define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) 1232 #define I2S_TX_PCM_CONF_V 0x7 1233 #define I2S_TX_PCM_CONF_S 0 1234 1235 #define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4) 1236 /* I2S_DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'h0 ; */ 1237 /*description: */ 1238 #define I2S_DMA_RAM_CLK_FO (BIT(6)) 1239 #define I2S_DMA_RAM_CLK_FO_M (BIT(6)) 1240 #define I2S_DMA_RAM_CLK_FO_V 0x1 1241 #define I2S_DMA_RAM_CLK_FO_S 6 1242 /* I2S_DMA_RAM_FORCE_PU : R/W ;bitpos:[5] ;default: 1'h1 ; */ 1243 /*description: */ 1244 #define I2S_DMA_RAM_FORCE_PU (BIT(5)) 1245 #define I2S_DMA_RAM_FORCE_PU_M (BIT(5)) 1246 #define I2S_DMA_RAM_FORCE_PU_V 0x1 1247 #define I2S_DMA_RAM_FORCE_PU_S 5 1248 /* I2S_DMA_RAM_FORCE_PD : R/W ;bitpos:[4] ;default: 1'h0 ; */ 1249 /*description: */ 1250 #define I2S_DMA_RAM_FORCE_PD (BIT(4)) 1251 #define I2S_DMA_RAM_FORCE_PD_M (BIT(4)) 1252 #define I2S_DMA_RAM_FORCE_PD_V 0x1 1253 #define I2S_DMA_RAM_FORCE_PD_S 4 1254 /* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */ 1255 /*description: */ 1256 #define I2S_PLC_MEM_FORCE_PU (BIT(3)) 1257 #define I2S_PLC_MEM_FORCE_PU_M (BIT(3)) 1258 #define I2S_PLC_MEM_FORCE_PU_V 0x1 1259 #define I2S_PLC_MEM_FORCE_PU_S 3 1260 /* I2S_PLC_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */ 1261 /*description: */ 1262 #define I2S_PLC_MEM_FORCE_PD (BIT(2)) 1263 #define I2S_PLC_MEM_FORCE_PD_M (BIT(2)) 1264 #define I2S_PLC_MEM_FORCE_PD_V 0x1 1265 #define I2S_PLC_MEM_FORCE_PD_S 2 1266 /* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */ 1267 /*description: Force FIFO power-up*/ 1268 #define I2S_FIFO_FORCE_PU (BIT(1)) 1269 #define I2S_FIFO_FORCE_PU_M (BIT(1)) 1270 #define I2S_FIFO_FORCE_PU_V 0x1 1271 #define I2S_FIFO_FORCE_PU_S 1 1272 /* I2S_FIFO_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ 1273 /*description: Force FIFO power-down*/ 1274 #define I2S_FIFO_FORCE_PD (BIT(0)) 1275 #define I2S_FIFO_FORCE_PD_M (BIT(0)) 1276 #define I2S_FIFO_FORCE_PD_V 0x1 1277 #define I2S_FIFO_FORCE_PD_S 0 1278 1279 #define I2S_CONF2_REG(i) (REG_I2S_BASE(i) + 0x00a8) 1280 /* I2S_I2SI_V_SYNC_FILTER_THRES : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ 1281 /*description: */ 1282 #define I2S_I2SI_V_SYNC_FILTER_THRES 0x00000007 1283 #define I2S_I2SI_V_SYNC_FILTER_THRES_M ((I2S_I2SI_V_SYNC_FILTER_THRES_V)<<(I2S_I2SI_V_SYNC_FILTER_THRES_S)) 1284 #define I2S_I2SI_V_SYNC_FILTER_THRES_V 0x7 1285 #define I2S_I2SI_V_SYNC_FILTER_THRES_S 11 1286 /* I2S_I2SI_V_SYNC_FILTER_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1287 /*description: */ 1288 #define I2S_I2SI_V_SYNC_FILTER_EN (BIT(10)) 1289 #define I2S_I2SI_V_SYNC_FILTER_EN_M (BIT(10)) 1290 #define I2S_I2SI_V_SYNC_FILTER_EN_V 0x1 1291 #define I2S_I2SI_V_SYNC_FILTER_EN_S 10 1292 /* I2S_CAM_CLK_LOOPBACK : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1293 /*description: Set this bit to loopback cam_clk from i2s_rx*/ 1294 #define I2S_CAM_CLK_LOOPBACK (BIT(9)) 1295 #define I2S_CAM_CLK_LOOPBACK_M (BIT(9)) 1296 #define I2S_CAM_CLK_LOOPBACK_V 0x1 1297 #define I2S_CAM_CLK_LOOPBACK_S 9 1298 /* I2S_CAM_SYNC_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1299 /*description: Set this bit to reset cam_sync_fifo*/ 1300 #define I2S_CAM_SYNC_FIFO_RESET (BIT(8)) 1301 #define I2S_CAM_SYNC_FIFO_RESET_M (BIT(8)) 1302 #define I2S_CAM_SYNC_FIFO_RESET_V 0x1 1303 #define I2S_CAM_SYNC_FIFO_RESET_S 8 1304 /* I2S_INTER_VALID_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1305 /*description: Set this bit to enable camera internal valid*/ 1306 #define I2S_INTER_VALID_EN (BIT(7)) 1307 #define I2S_INTER_VALID_EN_M (BIT(7)) 1308 #define I2S_INTER_VALID_EN_V 0x1 1309 #define I2S_INTER_VALID_EN_S 7 1310 /* I2S_EXT_ADC_START_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1311 /*description: Set this bit to enable the function that ADC mode is triggered 1312 by external signal.*/ 1313 #define I2S_EXT_ADC_START_EN (BIT(6)) 1314 #define I2S_EXT_ADC_START_EN_M (BIT(6)) 1315 #define I2S_EXT_ADC_START_EN_V 0x1 1316 #define I2S_EXT_ADC_START_EN_S 6 1317 /* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1318 /*description: Set this bit to enable LCD mode*/ 1319 #define I2S_LCD_EN (BIT(5)) 1320 #define I2S_LCD_EN_M (BIT(5)) 1321 #define I2S_LCD_EN_V 0x1 1322 #define I2S_LCD_EN_S 5 1323 /* I2S_DATA_ENABLE : R/W ;bitpos:[4] ;default: 1'h0 ; */ 1324 /*description: for debug camera mode enable*/ 1325 #define I2S_DATA_ENABLE (BIT(4)) 1326 #define I2S_DATA_ENABLE_M (BIT(4)) 1327 #define I2S_DATA_ENABLE_V 0x1 1328 #define I2S_DATA_ENABLE_S 4 1329 /* I2S_DATA_ENABLE_TEST_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ 1330 /*description: for debug camera mode enable*/ 1331 #define I2S_DATA_ENABLE_TEST_EN (BIT(3)) 1332 #define I2S_DATA_ENABLE_TEST_EN_M (BIT(3)) 1333 #define I2S_DATA_ENABLE_TEST_EN_V 0x1 1334 #define I2S_DATA_ENABLE_TEST_EN_S 3 1335 /* I2S_LCD_TX_SDX2_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ 1336 /*description: Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/ 1337 #define I2S_LCD_TX_SDX2_EN (BIT(2)) 1338 #define I2S_LCD_TX_SDX2_EN_M (BIT(2)) 1339 #define I2S_LCD_TX_SDX2_EN_V 0x1 1340 #define I2S_LCD_TX_SDX2_EN_S 2 1341 /* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 1342 /*description: LCD WR double for one datum.*/ 1343 #define I2S_LCD_TX_WRX2_EN (BIT(1)) 1344 #define I2S_LCD_TX_WRX2_EN_M (BIT(1)) 1345 #define I2S_LCD_TX_WRX2_EN_V 0x1 1346 #define I2S_LCD_TX_WRX2_EN_S 1 1347 /* I2S_CAMERA_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 1348 /*description: Set this bit to enable camera mode*/ 1349 #define I2S_CAMERA_EN (BIT(0)) 1350 #define I2S_CAMERA_EN_M (BIT(0)) 1351 #define I2S_CAMERA_EN_V 0x1 1352 #define I2S_CAMERA_EN_S 0 1353 1354 #define I2S_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00ac) 1355 /* I2S_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ 1356 /*description: Set this bit to enable clk_apll*/ 1357 #define I2S_CLK_SEL 0x00000003 1358 #define I2S_CLK_SEL_M ((I2S_CLK_SEL_V)<<(I2S_CLK_SEL_S)) 1359 #define I2S_CLK_SEL_V 0x3 1360 #define I2S_CLK_SEL_S 21 1361 #define I2S_CLK_AUDIO_PLL 1 1362 #define I2S_CLK_160M_PLL 2 1363 /* I2S_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 1364 /*description: Set this bit to enable clk gate*/ 1365 #define I2S_CLK_EN (BIT(20)) 1366 #define I2S_CLK_EN_M (BIT(20)) 1367 #define I2S_CLK_EN_V 0x1 1368 #define I2S_CLK_EN_S 20 1369 /* I2S_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ 1370 /*description: Fractional clock divider denominator value*/ 1371 #define I2S_CLKM_DIV_A 0x0000003F 1372 #define I2S_CLKM_DIV_A_M ((I2S_CLKM_DIV_A_V)<<(I2S_CLKM_DIV_A_S)) 1373 #define I2S_CLKM_DIV_A_V 0x3F 1374 #define I2S_CLKM_DIV_A_S 14 1375 /* I2S_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ 1376 /*description: Fractional clock divider numerator value*/ 1377 #define I2S_CLKM_DIV_B 0x0000003F 1378 #define I2S_CLKM_DIV_B_M ((I2S_CLKM_DIV_B_V)<<(I2S_CLKM_DIV_B_S)) 1379 #define I2S_CLKM_DIV_B_V 0x3F 1380 #define I2S_CLKM_DIV_B_S 8 1381 /* I2S_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ 1382 /*description: Integral I2S clock divider value*/ 1383 #define I2S_CLKM_DIV_NUM 0x000000FF 1384 #define I2S_CLKM_DIV_NUM_M ((I2S_CLKM_DIV_NUM_V)<<(I2S_CLKM_DIV_NUM_S)) 1385 #define I2S_CLKM_DIV_NUM_V 0xFF 1386 #define I2S_CLKM_DIV_NUM_S 0 1387 1388 #define I2S_SAMPLE_RATE_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b0) 1389 /* I2S_RX_BITS_MOD : R/W ;bitpos:[23:18] ;default: 6'd16 ; */ 1390 /*description: Set the bits to configure bit length of I2S receiver channel.*/ 1391 #define I2S_RX_BITS_MOD 0x0000003F 1392 #define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) 1393 #define I2S_RX_BITS_MOD_V 0x3F 1394 #define I2S_RX_BITS_MOD_S 18 1395 /* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */ 1396 /*description: Set the bits to configure bit length of I2S transmitter channel.*/ 1397 #define I2S_TX_BITS_MOD 0x0000003F 1398 #define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) 1399 #define I2S_TX_BITS_MOD_V 0x3F 1400 #define I2S_TX_BITS_MOD_S 12 1401 /* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[11:6] ;default: 6'd6 ; */ 1402 /*description: Bit clock configuration bits in receiver mode.*/ 1403 #define I2S_RX_BCK_DIV_NUM 0x0000003F 1404 #define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) 1405 #define I2S_RX_BCK_DIV_NUM_V 0x3F 1406 #define I2S_RX_BCK_DIV_NUM_S 6 1407 /* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[5:0] ;default: 6'd6 ; */ 1408 /*description: Bit clock configuration bits in transmitter mode.*/ 1409 #define I2S_TX_BCK_DIV_NUM 0x0000003F 1410 #define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) 1411 #define I2S_TX_BCK_DIV_NUM_V 0x3F 1412 #define I2S_TX_BCK_DIV_NUM_S 0 1413 1414 #define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x00bc) 1415 /* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ 1416 /*description: */ 1417 #define I2S_TX_IDLE (BIT(0)) 1418 #define I2S_TX_IDLE_M (BIT(0)) 1419 #define I2S_TX_IDLE_V 0x1 1420 #define I2S_TX_IDLE_S 0 1421 1422 #define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x00fc) 1423 /* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h19052500 ; */ 1424 /*description: */ 1425 #define I2S_I2SDATE 0xFFFFFFFF 1426 #define I2S_I2SDATE_M ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S)) 1427 #define I2S_I2SDATE_V 0xFFFFFFFF 1428 #define I2S_I2SDATE_S 0 1429 1430 #ifdef __cplusplus 1431 } 1432 #endif 1433 1434 1435 1436 #endif /*_SOC_I2S_REG_H_ */ 1437
