1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_I2S_REG_H_ 7 #define _SOC_I2S_REG_H_ 8 9 #include "soc.h" 10 11 #define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000)) 12 13 14 #define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) 15 /* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */ 16 /*description: */ 17 #define I2S_SIG_LOOPBACK (BIT(18)) 18 #define I2S_SIG_LOOPBACK_M (BIT(18)) 19 #define I2S_SIG_LOOPBACK_V 0x1 20 #define I2S_SIG_LOOPBACK_S 18 21 /* I2S_RX_MSB_RIGHT : R/W ;bitpos:[17] ;default: 1'b1 ; */ 22 /*description: */ 23 #define I2S_RX_MSB_RIGHT (BIT(17)) 24 #define I2S_RX_MSB_RIGHT_M (BIT(17)) 25 #define I2S_RX_MSB_RIGHT_V 0x1 26 #define I2S_RX_MSB_RIGHT_S 17 27 /* I2S_TX_MSB_RIGHT : R/W ;bitpos:[16] ;default: 1'b1 ; */ 28 /*description: */ 29 #define I2S_TX_MSB_RIGHT (BIT(16)) 30 #define I2S_TX_MSB_RIGHT_M (BIT(16)) 31 #define I2S_TX_MSB_RIGHT_V 0x1 32 #define I2S_TX_MSB_RIGHT_S 16 33 /* I2S_RX_MONO : R/W ;bitpos:[15] ;default: 1'b0 ; */ 34 /*description: */ 35 #define I2S_RX_MONO (BIT(15)) 36 #define I2S_RX_MONO_M (BIT(15)) 37 #define I2S_RX_MONO_V 0x1 38 #define I2S_RX_MONO_S 15 39 /* I2S_TX_MONO : R/W ;bitpos:[14] ;default: 1'b0 ; */ 40 /*description: */ 41 #define I2S_TX_MONO (BIT(14)) 42 #define I2S_TX_MONO_M (BIT(14)) 43 #define I2S_TX_MONO_V 0x1 44 #define I2S_TX_MONO_S 14 45 /* I2S_RX_SHORT_SYNC : R/W ;bitpos:[13] ;default: 1'b0 ; */ 46 /*description: */ 47 #define I2S_RX_SHORT_SYNC (BIT(13)) 48 #define I2S_RX_SHORT_SYNC_M (BIT(13)) 49 #define I2S_RX_SHORT_SYNC_V 0x1 50 #define I2S_RX_SHORT_SYNC_S 13 51 /* I2S_TX_SHORT_SYNC : R/W ;bitpos:[12] ;default: 1'b0 ; */ 52 /*description: */ 53 #define I2S_TX_SHORT_SYNC (BIT(12)) 54 #define I2S_TX_SHORT_SYNC_M (BIT(12)) 55 #define I2S_TX_SHORT_SYNC_V 0x1 56 #define I2S_TX_SHORT_SYNC_S 12 57 /* I2S_RX_MSB_SHIFT : R/W ;bitpos:[11] ;default: 1'b0 ; */ 58 /*description: */ 59 #define I2S_RX_MSB_SHIFT (BIT(11)) 60 #define I2S_RX_MSB_SHIFT_M (BIT(11)) 61 #define I2S_RX_MSB_SHIFT_V 0x1 62 #define I2S_RX_MSB_SHIFT_S 11 63 /* I2S_TX_MSB_SHIFT : R/W ;bitpos:[10] ;default: 1'b0 ; */ 64 /*description: */ 65 #define I2S_TX_MSB_SHIFT (BIT(10)) 66 #define I2S_TX_MSB_SHIFT_M (BIT(10)) 67 #define I2S_TX_MSB_SHIFT_V 0x1 68 #define I2S_TX_MSB_SHIFT_S 10 69 /* I2S_RX_RIGHT_FIRST : R/W ;bitpos:[9] ;default: 1'b1 ; */ 70 /*description: */ 71 #define I2S_RX_RIGHT_FIRST (BIT(9)) 72 #define I2S_RX_RIGHT_FIRST_M (BIT(9)) 73 #define I2S_RX_RIGHT_FIRST_V 0x1 74 #define I2S_RX_RIGHT_FIRST_S 9 75 /* I2S_TX_RIGHT_FIRST : R/W ;bitpos:[8] ;default: 1'b1 ; */ 76 /*description: */ 77 #define I2S_TX_RIGHT_FIRST (BIT(8)) 78 #define I2S_TX_RIGHT_FIRST_M (BIT(8)) 79 #define I2S_TX_RIGHT_FIRST_V 0x1 80 #define I2S_TX_RIGHT_FIRST_S 8 81 /* I2S_RX_SLAVE_MOD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 82 /*description: */ 83 #define I2S_RX_SLAVE_MOD (BIT(7)) 84 #define I2S_RX_SLAVE_MOD_M (BIT(7)) 85 #define I2S_RX_SLAVE_MOD_V 0x1 86 #define I2S_RX_SLAVE_MOD_S 7 87 /* I2S_TX_SLAVE_MOD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 88 /*description: */ 89 #define I2S_TX_SLAVE_MOD (BIT(6)) 90 #define I2S_TX_SLAVE_MOD_M (BIT(6)) 91 #define I2S_TX_SLAVE_MOD_V 0x1 92 #define I2S_TX_SLAVE_MOD_S 6 93 /* I2S_RX_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ 94 /*description: */ 95 #define I2S_RX_START (BIT(5)) 96 #define I2S_RX_START_M (BIT(5)) 97 #define I2S_RX_START_V 0x1 98 #define I2S_RX_START_S 5 99 /* I2S_TX_START : R/W ;bitpos:[4] ;default: 1'b0 ; */ 100 /*description: */ 101 #define I2S_TX_START (BIT(4)) 102 #define I2S_TX_START_M (BIT(4)) 103 #define I2S_TX_START_V 0x1 104 #define I2S_TX_START_S 4 105 /* I2S_RX_FIFO_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ 106 /*description: */ 107 #define I2S_RX_FIFO_RESET (BIT(3)) 108 #define I2S_RX_FIFO_RESET_M (BIT(3)) 109 #define I2S_RX_FIFO_RESET_V 0x1 110 #define I2S_RX_FIFO_RESET_S 3 111 /* I2S_TX_FIFO_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ 112 /*description: */ 113 #define I2S_TX_FIFO_RESET (BIT(2)) 114 #define I2S_TX_FIFO_RESET_M (BIT(2)) 115 #define I2S_TX_FIFO_RESET_V 0x1 116 #define I2S_TX_FIFO_RESET_S 2 117 /* I2S_RX_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ 118 /*description: */ 119 #define I2S_RX_RESET (BIT(1)) 120 #define I2S_RX_RESET_M (BIT(1)) 121 #define I2S_RX_RESET_V 0x1 122 #define I2S_RX_RESET_S 1 123 /* I2S_TX_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */ 124 /*description: */ 125 #define I2S_TX_RESET (BIT(0)) 126 #define I2S_TX_RESET_M (BIT(0)) 127 #define I2S_TX_RESET_V 0x1 128 #define I2S_TX_RESET_S 0 129 130 #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) 131 /* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 132 /*description: */ 133 #define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16)) 134 #define I2S_OUT_TOTAL_EOF_INT_RAW_M (BIT(16)) 135 #define I2S_OUT_TOTAL_EOF_INT_RAW_V 0x1 136 #define I2S_OUT_TOTAL_EOF_INT_RAW_S 16 137 /* I2S_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 138 /*description: */ 139 #define I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15)) 140 #define I2S_IN_DSCR_EMPTY_INT_RAW_M (BIT(15)) 141 #define I2S_IN_DSCR_EMPTY_INT_RAW_V 0x1 142 #define I2S_IN_DSCR_EMPTY_INT_RAW_S 15 143 /* I2S_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ 144 /*description: */ 145 #define I2S_OUT_DSCR_ERR_INT_RAW (BIT(14)) 146 #define I2S_OUT_DSCR_ERR_INT_RAW_M (BIT(14)) 147 #define I2S_OUT_DSCR_ERR_INT_RAW_V 0x1 148 #define I2S_OUT_DSCR_ERR_INT_RAW_S 14 149 /* I2S_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ 150 /*description: */ 151 #define I2S_IN_DSCR_ERR_INT_RAW (BIT(13)) 152 #define I2S_IN_DSCR_ERR_INT_RAW_M (BIT(13)) 153 #define I2S_IN_DSCR_ERR_INT_RAW_V 0x1 154 #define I2S_IN_DSCR_ERR_INT_RAW_S 13 155 /* I2S_OUT_EOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 156 /*description: */ 157 #define I2S_OUT_EOF_INT_RAW (BIT(12)) 158 #define I2S_OUT_EOF_INT_RAW_M (BIT(12)) 159 #define I2S_OUT_EOF_INT_RAW_V 0x1 160 #define I2S_OUT_EOF_INT_RAW_S 12 161 /* I2S_OUT_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 162 /*description: */ 163 #define I2S_OUT_DONE_INT_RAW (BIT(11)) 164 #define I2S_OUT_DONE_INT_RAW_M (BIT(11)) 165 #define I2S_OUT_DONE_INT_RAW_V 0x1 166 #define I2S_OUT_DONE_INT_RAW_S 11 167 /* I2S_IN_ERR_EOF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 168 /*description: */ 169 #define I2S_IN_ERR_EOF_INT_RAW (BIT(10)) 170 #define I2S_IN_ERR_EOF_INT_RAW_M (BIT(10)) 171 #define I2S_IN_ERR_EOF_INT_RAW_V 0x1 172 #define I2S_IN_ERR_EOF_INT_RAW_S 10 173 /* I2S_IN_SUC_EOF_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 174 /*description: */ 175 #define I2S_IN_SUC_EOF_INT_RAW (BIT(9)) 176 #define I2S_IN_SUC_EOF_INT_RAW_M (BIT(9)) 177 #define I2S_IN_SUC_EOF_INT_RAW_V 0x1 178 #define I2S_IN_SUC_EOF_INT_RAW_S 9 179 /* I2S_IN_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 180 /*description: */ 181 #define I2S_IN_DONE_INT_RAW (BIT(8)) 182 #define I2S_IN_DONE_INT_RAW_M (BIT(8)) 183 #define I2S_IN_DONE_INT_RAW_V 0x1 184 #define I2S_IN_DONE_INT_RAW_S 8 185 /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 186 /*description: */ 187 #define I2S_TX_HUNG_INT_RAW (BIT(7)) 188 #define I2S_TX_HUNG_INT_RAW_M (BIT(7)) 189 #define I2S_TX_HUNG_INT_RAW_V 0x1 190 #define I2S_TX_HUNG_INT_RAW_S 7 191 /* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 192 /*description: */ 193 #define I2S_RX_HUNG_INT_RAW (BIT(6)) 194 #define I2S_RX_HUNG_INT_RAW_M (BIT(6)) 195 #define I2S_RX_HUNG_INT_RAW_V 0x1 196 #define I2S_RX_HUNG_INT_RAW_S 6 197 /* I2S_TX_REMPTY_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 198 /*description: */ 199 #define I2S_TX_REMPTY_INT_RAW (BIT(5)) 200 #define I2S_TX_REMPTY_INT_RAW_M (BIT(5)) 201 #define I2S_TX_REMPTY_INT_RAW_V 0x1 202 #define I2S_TX_REMPTY_INT_RAW_S 5 203 /* I2S_TX_WFULL_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 204 /*description: */ 205 #define I2S_TX_WFULL_INT_RAW (BIT(4)) 206 #define I2S_TX_WFULL_INT_RAW_M (BIT(4)) 207 #define I2S_TX_WFULL_INT_RAW_V 0x1 208 #define I2S_TX_WFULL_INT_RAW_S 4 209 /* I2S_RX_REMPTY_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 210 /*description: */ 211 #define I2S_RX_REMPTY_INT_RAW (BIT(3)) 212 #define I2S_RX_REMPTY_INT_RAW_M (BIT(3)) 213 #define I2S_RX_REMPTY_INT_RAW_V 0x1 214 #define I2S_RX_REMPTY_INT_RAW_S 3 215 /* I2S_RX_WFULL_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 216 /*description: */ 217 #define I2S_RX_WFULL_INT_RAW (BIT(2)) 218 #define I2S_RX_WFULL_INT_RAW_M (BIT(2)) 219 #define I2S_RX_WFULL_INT_RAW_V 0x1 220 #define I2S_RX_WFULL_INT_RAW_S 2 221 /* I2S_TX_PUT_DATA_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 222 /*description: */ 223 #define I2S_TX_PUT_DATA_INT_RAW (BIT(1)) 224 #define I2S_TX_PUT_DATA_INT_RAW_M (BIT(1)) 225 #define I2S_TX_PUT_DATA_INT_RAW_V 0x1 226 #define I2S_TX_PUT_DATA_INT_RAW_S 1 227 /* I2S_RX_TAKE_DATA_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 228 /*description: */ 229 #define I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) 230 #define I2S_RX_TAKE_DATA_INT_RAW_M (BIT(0)) 231 #define I2S_RX_TAKE_DATA_INT_RAW_V 0x1 232 #define I2S_RX_TAKE_DATA_INT_RAW_S 0 233 234 #define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) 235 /* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 236 /*description: */ 237 #define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16)) 238 #define I2S_OUT_TOTAL_EOF_INT_ST_M (BIT(16)) 239 #define I2S_OUT_TOTAL_EOF_INT_ST_V 0x1 240 #define I2S_OUT_TOTAL_EOF_INT_ST_S 16 241 /* I2S_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 242 /*description: */ 243 #define I2S_IN_DSCR_EMPTY_INT_ST (BIT(15)) 244 #define I2S_IN_DSCR_EMPTY_INT_ST_M (BIT(15)) 245 #define I2S_IN_DSCR_EMPTY_INT_ST_V 0x1 246 #define I2S_IN_DSCR_EMPTY_INT_ST_S 15 247 /* I2S_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ 248 /*description: */ 249 #define I2S_OUT_DSCR_ERR_INT_ST (BIT(14)) 250 #define I2S_OUT_DSCR_ERR_INT_ST_M (BIT(14)) 251 #define I2S_OUT_DSCR_ERR_INT_ST_V 0x1 252 #define I2S_OUT_DSCR_ERR_INT_ST_S 14 253 /* I2S_IN_DSCR_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 254 /*description: */ 255 #define I2S_IN_DSCR_ERR_INT_ST (BIT(13)) 256 #define I2S_IN_DSCR_ERR_INT_ST_M (BIT(13)) 257 #define I2S_IN_DSCR_ERR_INT_ST_V 0x1 258 #define I2S_IN_DSCR_ERR_INT_ST_S 13 259 /* I2S_OUT_EOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 260 /*description: */ 261 #define I2S_OUT_EOF_INT_ST (BIT(12)) 262 #define I2S_OUT_EOF_INT_ST_M (BIT(12)) 263 #define I2S_OUT_EOF_INT_ST_V 0x1 264 #define I2S_OUT_EOF_INT_ST_S 12 265 /* I2S_OUT_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 266 /*description: */ 267 #define I2S_OUT_DONE_INT_ST (BIT(11)) 268 #define I2S_OUT_DONE_INT_ST_M (BIT(11)) 269 #define I2S_OUT_DONE_INT_ST_V 0x1 270 #define I2S_OUT_DONE_INT_ST_S 11 271 /* I2S_IN_ERR_EOF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 272 /*description: */ 273 #define I2S_IN_ERR_EOF_INT_ST (BIT(10)) 274 #define I2S_IN_ERR_EOF_INT_ST_M (BIT(10)) 275 #define I2S_IN_ERR_EOF_INT_ST_V 0x1 276 #define I2S_IN_ERR_EOF_INT_ST_S 10 277 /* I2S_IN_SUC_EOF_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 278 /*description: */ 279 #define I2S_IN_SUC_EOF_INT_ST (BIT(9)) 280 #define I2S_IN_SUC_EOF_INT_ST_M (BIT(9)) 281 #define I2S_IN_SUC_EOF_INT_ST_V 0x1 282 #define I2S_IN_SUC_EOF_INT_ST_S 9 283 /* I2S_IN_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 284 /*description: */ 285 #define I2S_IN_DONE_INT_ST (BIT(8)) 286 #define I2S_IN_DONE_INT_ST_M (BIT(8)) 287 #define I2S_IN_DONE_INT_ST_V 0x1 288 #define I2S_IN_DONE_INT_ST_S 8 289 /* I2S_TX_HUNG_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 290 /*description: */ 291 #define I2S_TX_HUNG_INT_ST (BIT(7)) 292 #define I2S_TX_HUNG_INT_ST_M (BIT(7)) 293 #define I2S_TX_HUNG_INT_ST_V 0x1 294 #define I2S_TX_HUNG_INT_ST_S 7 295 /* I2S_RX_HUNG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 296 /*description: */ 297 #define I2S_RX_HUNG_INT_ST (BIT(6)) 298 #define I2S_RX_HUNG_INT_ST_M (BIT(6)) 299 #define I2S_RX_HUNG_INT_ST_V 0x1 300 #define I2S_RX_HUNG_INT_ST_S 6 301 /* I2S_TX_REMPTY_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 302 /*description: */ 303 #define I2S_TX_REMPTY_INT_ST (BIT(5)) 304 #define I2S_TX_REMPTY_INT_ST_M (BIT(5)) 305 #define I2S_TX_REMPTY_INT_ST_V 0x1 306 #define I2S_TX_REMPTY_INT_ST_S 5 307 /* I2S_TX_WFULL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 308 /*description: */ 309 #define I2S_TX_WFULL_INT_ST (BIT(4)) 310 #define I2S_TX_WFULL_INT_ST_M (BIT(4)) 311 #define I2S_TX_WFULL_INT_ST_V 0x1 312 #define I2S_TX_WFULL_INT_ST_S 4 313 /* I2S_RX_REMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 314 /*description: */ 315 #define I2S_RX_REMPTY_INT_ST (BIT(3)) 316 #define I2S_RX_REMPTY_INT_ST_M (BIT(3)) 317 #define I2S_RX_REMPTY_INT_ST_V 0x1 318 #define I2S_RX_REMPTY_INT_ST_S 3 319 /* I2S_RX_WFULL_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 320 /*description: */ 321 #define I2S_RX_WFULL_INT_ST (BIT(2)) 322 #define I2S_RX_WFULL_INT_ST_M (BIT(2)) 323 #define I2S_RX_WFULL_INT_ST_V 0x1 324 #define I2S_RX_WFULL_INT_ST_S 2 325 /* I2S_TX_PUT_DATA_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 326 /*description: */ 327 #define I2S_TX_PUT_DATA_INT_ST (BIT(1)) 328 #define I2S_TX_PUT_DATA_INT_ST_M (BIT(1)) 329 #define I2S_TX_PUT_DATA_INT_ST_V 0x1 330 #define I2S_TX_PUT_DATA_INT_ST_S 1 331 /* I2S_RX_TAKE_DATA_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 332 /*description: */ 333 #define I2S_RX_TAKE_DATA_INT_ST (BIT(0)) 334 #define I2S_RX_TAKE_DATA_INT_ST_M (BIT(0)) 335 #define I2S_RX_TAKE_DATA_INT_ST_V 0x1 336 #define I2S_RX_TAKE_DATA_INT_ST_S 0 337 338 #define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) 339 /* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 340 /*description: */ 341 #define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16)) 342 #define I2S_OUT_TOTAL_EOF_INT_ENA_M (BIT(16)) 343 #define I2S_OUT_TOTAL_EOF_INT_ENA_V 0x1 344 #define I2S_OUT_TOTAL_EOF_INT_ENA_S 16 345 /* I2S_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 346 /*description: */ 347 #define I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15)) 348 #define I2S_IN_DSCR_EMPTY_INT_ENA_M (BIT(15)) 349 #define I2S_IN_DSCR_EMPTY_INT_ENA_V 0x1 350 #define I2S_IN_DSCR_EMPTY_INT_ENA_S 15 351 /* I2S_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 352 /*description: */ 353 #define I2S_OUT_DSCR_ERR_INT_ENA (BIT(14)) 354 #define I2S_OUT_DSCR_ERR_INT_ENA_M (BIT(14)) 355 #define I2S_OUT_DSCR_ERR_INT_ENA_V 0x1 356 #define I2S_OUT_DSCR_ERR_INT_ENA_S 14 357 /* I2S_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 358 /*description: */ 359 #define I2S_IN_DSCR_ERR_INT_ENA (BIT(13)) 360 #define I2S_IN_DSCR_ERR_INT_ENA_M (BIT(13)) 361 #define I2S_IN_DSCR_ERR_INT_ENA_V 0x1 362 #define I2S_IN_DSCR_ERR_INT_ENA_S 13 363 /* I2S_OUT_EOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 364 /*description: */ 365 #define I2S_OUT_EOF_INT_ENA (BIT(12)) 366 #define I2S_OUT_EOF_INT_ENA_M (BIT(12)) 367 #define I2S_OUT_EOF_INT_ENA_V 0x1 368 #define I2S_OUT_EOF_INT_ENA_S 12 369 /* I2S_OUT_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 370 /*description: */ 371 #define I2S_OUT_DONE_INT_ENA (BIT(11)) 372 #define I2S_OUT_DONE_INT_ENA_M (BIT(11)) 373 #define I2S_OUT_DONE_INT_ENA_V 0x1 374 #define I2S_OUT_DONE_INT_ENA_S 11 375 /* I2S_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 376 /*description: */ 377 #define I2S_IN_ERR_EOF_INT_ENA (BIT(10)) 378 #define I2S_IN_ERR_EOF_INT_ENA_M (BIT(10)) 379 #define I2S_IN_ERR_EOF_INT_ENA_V 0x1 380 #define I2S_IN_ERR_EOF_INT_ENA_S 10 381 /* I2S_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 382 /*description: */ 383 #define I2S_IN_SUC_EOF_INT_ENA (BIT(9)) 384 #define I2S_IN_SUC_EOF_INT_ENA_M (BIT(9)) 385 #define I2S_IN_SUC_EOF_INT_ENA_V 0x1 386 #define I2S_IN_SUC_EOF_INT_ENA_S 9 387 /* I2S_IN_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 388 /*description: */ 389 #define I2S_IN_DONE_INT_ENA (BIT(8)) 390 #define I2S_IN_DONE_INT_ENA_M (BIT(8)) 391 #define I2S_IN_DONE_INT_ENA_V 0x1 392 #define I2S_IN_DONE_INT_ENA_S 8 393 /* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 394 /*description: */ 395 #define I2S_TX_HUNG_INT_ENA (BIT(7)) 396 #define I2S_TX_HUNG_INT_ENA_M (BIT(7)) 397 #define I2S_TX_HUNG_INT_ENA_V 0x1 398 #define I2S_TX_HUNG_INT_ENA_S 7 399 /* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 400 /*description: */ 401 #define I2S_RX_HUNG_INT_ENA (BIT(6)) 402 #define I2S_RX_HUNG_INT_ENA_M (BIT(6)) 403 #define I2S_RX_HUNG_INT_ENA_V 0x1 404 #define I2S_RX_HUNG_INT_ENA_S 6 405 /* I2S_TX_REMPTY_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 406 /*description: */ 407 #define I2S_TX_REMPTY_INT_ENA (BIT(5)) 408 #define I2S_TX_REMPTY_INT_ENA_M (BIT(5)) 409 #define I2S_TX_REMPTY_INT_ENA_V 0x1 410 #define I2S_TX_REMPTY_INT_ENA_S 5 411 /* I2S_TX_WFULL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 412 /*description: */ 413 #define I2S_TX_WFULL_INT_ENA (BIT(4)) 414 #define I2S_TX_WFULL_INT_ENA_M (BIT(4)) 415 #define I2S_TX_WFULL_INT_ENA_V 0x1 416 #define I2S_TX_WFULL_INT_ENA_S 4 417 /* I2S_RX_REMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 418 /*description: */ 419 #define I2S_RX_REMPTY_INT_ENA (BIT(3)) 420 #define I2S_RX_REMPTY_INT_ENA_M (BIT(3)) 421 #define I2S_RX_REMPTY_INT_ENA_V 0x1 422 #define I2S_RX_REMPTY_INT_ENA_S 3 423 /* I2S_RX_WFULL_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 424 /*description: */ 425 #define I2S_RX_WFULL_INT_ENA (BIT(2)) 426 #define I2S_RX_WFULL_INT_ENA_M (BIT(2)) 427 #define I2S_RX_WFULL_INT_ENA_V 0x1 428 #define I2S_RX_WFULL_INT_ENA_S 2 429 /* I2S_TX_PUT_DATA_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 430 /*description: */ 431 #define I2S_TX_PUT_DATA_INT_ENA (BIT(1)) 432 #define I2S_TX_PUT_DATA_INT_ENA_M (BIT(1)) 433 #define I2S_TX_PUT_DATA_INT_ENA_V 0x1 434 #define I2S_TX_PUT_DATA_INT_ENA_S 1 435 /* I2S_RX_TAKE_DATA_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 436 /*description: */ 437 #define I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) 438 #define I2S_RX_TAKE_DATA_INT_ENA_M (BIT(0)) 439 #define I2S_RX_TAKE_DATA_INT_ENA_V 0x1 440 #define I2S_RX_TAKE_DATA_INT_ENA_S 0 441 442 #define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) 443 /* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 444 /*description: */ 445 #define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16)) 446 #define I2S_OUT_TOTAL_EOF_INT_CLR_M (BIT(16)) 447 #define I2S_OUT_TOTAL_EOF_INT_CLR_V 0x1 448 #define I2S_OUT_TOTAL_EOF_INT_CLR_S 16 449 /* I2S_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 450 /*description: */ 451 #define I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15)) 452 #define I2S_IN_DSCR_EMPTY_INT_CLR_M (BIT(15)) 453 #define I2S_IN_DSCR_EMPTY_INT_CLR_V 0x1 454 #define I2S_IN_DSCR_EMPTY_INT_CLR_S 15 455 /* I2S_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ 456 /*description: */ 457 #define I2S_OUT_DSCR_ERR_INT_CLR (BIT(14)) 458 #define I2S_OUT_DSCR_ERR_INT_CLR_M (BIT(14)) 459 #define I2S_OUT_DSCR_ERR_INT_CLR_V 0x1 460 #define I2S_OUT_DSCR_ERR_INT_CLR_S 14 461 /* I2S_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ 462 /*description: */ 463 #define I2S_IN_DSCR_ERR_INT_CLR (BIT(13)) 464 #define I2S_IN_DSCR_ERR_INT_CLR_M (BIT(13)) 465 #define I2S_IN_DSCR_ERR_INT_CLR_V 0x1 466 #define I2S_IN_DSCR_ERR_INT_CLR_S 13 467 /* I2S_OUT_EOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 468 /*description: */ 469 #define I2S_OUT_EOF_INT_CLR (BIT(12)) 470 #define I2S_OUT_EOF_INT_CLR_M (BIT(12)) 471 #define I2S_OUT_EOF_INT_CLR_V 0x1 472 #define I2S_OUT_EOF_INT_CLR_S 12 473 /* I2S_OUT_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 474 /*description: */ 475 #define I2S_OUT_DONE_INT_CLR (BIT(11)) 476 #define I2S_OUT_DONE_INT_CLR_M (BIT(11)) 477 #define I2S_OUT_DONE_INT_CLR_V 0x1 478 #define I2S_OUT_DONE_INT_CLR_S 11 479 /* I2S_IN_ERR_EOF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 480 /*description: */ 481 #define I2S_IN_ERR_EOF_INT_CLR (BIT(10)) 482 #define I2S_IN_ERR_EOF_INT_CLR_M (BIT(10)) 483 #define I2S_IN_ERR_EOF_INT_CLR_V 0x1 484 #define I2S_IN_ERR_EOF_INT_CLR_S 10 485 /* I2S_IN_SUC_EOF_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 486 /*description: */ 487 #define I2S_IN_SUC_EOF_INT_CLR (BIT(9)) 488 #define I2S_IN_SUC_EOF_INT_CLR_M (BIT(9)) 489 #define I2S_IN_SUC_EOF_INT_CLR_V 0x1 490 #define I2S_IN_SUC_EOF_INT_CLR_S 9 491 /* I2S_IN_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 492 /*description: */ 493 #define I2S_IN_DONE_INT_CLR (BIT(8)) 494 #define I2S_IN_DONE_INT_CLR_M (BIT(8)) 495 #define I2S_IN_DONE_INT_CLR_V 0x1 496 #define I2S_IN_DONE_INT_CLR_S 8 497 /* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 498 /*description: */ 499 #define I2S_TX_HUNG_INT_CLR (BIT(7)) 500 #define I2S_TX_HUNG_INT_CLR_M (BIT(7)) 501 #define I2S_TX_HUNG_INT_CLR_V 0x1 502 #define I2S_TX_HUNG_INT_CLR_S 7 503 /* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 504 /*description: */ 505 #define I2S_RX_HUNG_INT_CLR (BIT(6)) 506 #define I2S_RX_HUNG_INT_CLR_M (BIT(6)) 507 #define I2S_RX_HUNG_INT_CLR_V 0x1 508 #define I2S_RX_HUNG_INT_CLR_S 6 509 /* I2S_TX_REMPTY_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 510 /*description: */ 511 #define I2S_TX_REMPTY_INT_CLR (BIT(5)) 512 #define I2S_TX_REMPTY_INT_CLR_M (BIT(5)) 513 #define I2S_TX_REMPTY_INT_CLR_V 0x1 514 #define I2S_TX_REMPTY_INT_CLR_S 5 515 /* I2S_TX_WFULL_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 516 /*description: */ 517 #define I2S_TX_WFULL_INT_CLR (BIT(4)) 518 #define I2S_TX_WFULL_INT_CLR_M (BIT(4)) 519 #define I2S_TX_WFULL_INT_CLR_V 0x1 520 #define I2S_TX_WFULL_INT_CLR_S 4 521 /* I2S_RX_REMPTY_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 522 /*description: */ 523 #define I2S_RX_REMPTY_INT_CLR (BIT(3)) 524 #define I2S_RX_REMPTY_INT_CLR_M (BIT(3)) 525 #define I2S_RX_REMPTY_INT_CLR_V 0x1 526 #define I2S_RX_REMPTY_INT_CLR_S 3 527 /* I2S_RX_WFULL_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 528 /*description: */ 529 #define I2S_RX_WFULL_INT_CLR (BIT(2)) 530 #define I2S_RX_WFULL_INT_CLR_M (BIT(2)) 531 #define I2S_RX_WFULL_INT_CLR_V 0x1 532 #define I2S_RX_WFULL_INT_CLR_S 2 533 /* I2S_PUT_DATA_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 534 /*description: */ 535 #define I2S_PUT_DATA_INT_CLR (BIT(1)) 536 #define I2S_PUT_DATA_INT_CLR_M (BIT(1)) 537 #define I2S_PUT_DATA_INT_CLR_V 0x1 538 #define I2S_PUT_DATA_INT_CLR_S 1 539 /* I2S_TAKE_DATA_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 540 /*description: */ 541 #define I2S_TAKE_DATA_INT_CLR (BIT(0)) 542 #define I2S_TAKE_DATA_INT_CLR_M (BIT(0)) 543 #define I2S_TAKE_DATA_INT_CLR_V 0x1 544 #define I2S_TAKE_DATA_INT_CLR_S 0 545 546 #define I2S_TIMING_REG(i) (REG_I2S_BASE(i) + 0x001c) 547 /* I2S_TX_BCK_IN_INV : R/W ;bitpos:[24] ;default: 1'b0 ; */ 548 /*description: */ 549 #define I2S_TX_BCK_IN_INV (BIT(24)) 550 #define I2S_TX_BCK_IN_INV_M (BIT(24)) 551 #define I2S_TX_BCK_IN_INV_V 0x1 552 #define I2S_TX_BCK_IN_INV_S 24 553 /* I2S_DATA_ENABLE_DELAY : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ 554 /*description: */ 555 #define I2S_DATA_ENABLE_DELAY 0x00000003 556 #define I2S_DATA_ENABLE_DELAY_M ((I2S_DATA_ENABLE_DELAY_V)<<(I2S_DATA_ENABLE_DELAY_S)) 557 #define I2S_DATA_ENABLE_DELAY_V 0x3 558 #define I2S_DATA_ENABLE_DELAY_S 22 559 /* I2S_RX_DSYNC_SW : R/W ;bitpos:[21] ;default: 1'b0 ; */ 560 /*description: */ 561 #define I2S_RX_DSYNC_SW (BIT(21)) 562 #define I2S_RX_DSYNC_SW_M (BIT(21)) 563 #define I2S_RX_DSYNC_SW_V 0x1 564 #define I2S_RX_DSYNC_SW_S 21 565 /* I2S_TX_DSYNC_SW : R/W ;bitpos:[20] ;default: 1'b0 ; */ 566 /*description: */ 567 #define I2S_TX_DSYNC_SW (BIT(20)) 568 #define I2S_TX_DSYNC_SW_M (BIT(20)) 569 #define I2S_TX_DSYNC_SW_V 0x1 570 #define I2S_TX_DSYNC_SW_S 20 571 /* I2S_RX_BCK_OUT_DELAY : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ 572 /*description: */ 573 #define I2S_RX_BCK_OUT_DELAY 0x00000003 574 #define I2S_RX_BCK_OUT_DELAY_M ((I2S_RX_BCK_OUT_DELAY_V)<<(I2S_RX_BCK_OUT_DELAY_S)) 575 #define I2S_RX_BCK_OUT_DELAY_V 0x3 576 #define I2S_RX_BCK_OUT_DELAY_S 18 577 /* I2S_RX_WS_OUT_DELAY : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ 578 /*description: */ 579 #define I2S_RX_WS_OUT_DELAY 0x00000003 580 #define I2S_RX_WS_OUT_DELAY_M ((I2S_RX_WS_OUT_DELAY_V)<<(I2S_RX_WS_OUT_DELAY_S)) 581 #define I2S_RX_WS_OUT_DELAY_V 0x3 582 #define I2S_RX_WS_OUT_DELAY_S 16 583 /* I2S_TX_SD_OUT_DELAY : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ 584 /*description: */ 585 #define I2S_TX_SD_OUT_DELAY 0x00000003 586 #define I2S_TX_SD_OUT_DELAY_M ((I2S_TX_SD_OUT_DELAY_V)<<(I2S_TX_SD_OUT_DELAY_S)) 587 #define I2S_TX_SD_OUT_DELAY_V 0x3 588 #define I2S_TX_SD_OUT_DELAY_S 14 589 /* I2S_TX_WS_OUT_DELAY : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ 590 /*description: */ 591 #define I2S_TX_WS_OUT_DELAY 0x00000003 592 #define I2S_TX_WS_OUT_DELAY_M ((I2S_TX_WS_OUT_DELAY_V)<<(I2S_TX_WS_OUT_DELAY_S)) 593 #define I2S_TX_WS_OUT_DELAY_V 0x3 594 #define I2S_TX_WS_OUT_DELAY_S 12 595 /* I2S_TX_BCK_OUT_DELAY : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ 596 /*description: */ 597 #define I2S_TX_BCK_OUT_DELAY 0x00000003 598 #define I2S_TX_BCK_OUT_DELAY_M ((I2S_TX_BCK_OUT_DELAY_V)<<(I2S_TX_BCK_OUT_DELAY_S)) 599 #define I2S_TX_BCK_OUT_DELAY_V 0x3 600 #define I2S_TX_BCK_OUT_DELAY_S 10 601 /* I2S_RX_SD_IN_DELAY : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ 602 /*description: */ 603 #define I2S_RX_SD_IN_DELAY 0x00000003 604 #define I2S_RX_SD_IN_DELAY_M ((I2S_RX_SD_IN_DELAY_V)<<(I2S_RX_SD_IN_DELAY_S)) 605 #define I2S_RX_SD_IN_DELAY_V 0x3 606 #define I2S_RX_SD_IN_DELAY_S 8 607 /* I2S_RX_WS_IN_DELAY : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ 608 /*description: */ 609 #define I2S_RX_WS_IN_DELAY 0x00000003 610 #define I2S_RX_WS_IN_DELAY_M ((I2S_RX_WS_IN_DELAY_V)<<(I2S_RX_WS_IN_DELAY_S)) 611 #define I2S_RX_WS_IN_DELAY_V 0x3 612 #define I2S_RX_WS_IN_DELAY_S 6 613 /* I2S_RX_BCK_IN_DELAY : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ 614 /*description: */ 615 #define I2S_RX_BCK_IN_DELAY 0x00000003 616 #define I2S_RX_BCK_IN_DELAY_M ((I2S_RX_BCK_IN_DELAY_V)<<(I2S_RX_BCK_IN_DELAY_S)) 617 #define I2S_RX_BCK_IN_DELAY_V 0x3 618 #define I2S_RX_BCK_IN_DELAY_S 4 619 /* I2S_TX_WS_IN_DELAY : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ 620 /*description: */ 621 #define I2S_TX_WS_IN_DELAY 0x00000003 622 #define I2S_TX_WS_IN_DELAY_M ((I2S_TX_WS_IN_DELAY_V)<<(I2S_TX_WS_IN_DELAY_S)) 623 #define I2S_TX_WS_IN_DELAY_V 0x3 624 #define I2S_TX_WS_IN_DELAY_S 2 625 /* I2S_TX_BCK_IN_DELAY : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 626 /*description: */ 627 #define I2S_TX_BCK_IN_DELAY 0x00000003 628 #define I2S_TX_BCK_IN_DELAY_M ((I2S_TX_BCK_IN_DELAY_V)<<(I2S_TX_BCK_IN_DELAY_S)) 629 #define I2S_TX_BCK_IN_DELAY_V 0x3 630 #define I2S_TX_BCK_IN_DELAY_S 0 631 632 #define I2S_FIFO_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) 633 /* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 634 /*description: */ 635 #define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20)) 636 #define I2S_RX_FIFO_MOD_FORCE_EN_M (BIT(20)) 637 #define I2S_RX_FIFO_MOD_FORCE_EN_V 0x1 638 #define I2S_RX_FIFO_MOD_FORCE_EN_S 20 639 /* I2S_TX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 640 /*description: */ 641 #define I2S_TX_FIFO_MOD_FORCE_EN (BIT(19)) 642 #define I2S_TX_FIFO_MOD_FORCE_EN_M (BIT(19)) 643 #define I2S_TX_FIFO_MOD_FORCE_EN_V 0x1 644 #define I2S_TX_FIFO_MOD_FORCE_EN_S 19 645 /* I2S_RX_FIFO_MOD : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ 646 /*description: */ 647 #define I2S_RX_FIFO_MOD 0x00000007 648 #define I2S_RX_FIFO_MOD_M ((I2S_RX_FIFO_MOD_V)<<(I2S_RX_FIFO_MOD_S)) 649 #define I2S_RX_FIFO_MOD_V 0x7 650 #define I2S_RX_FIFO_MOD_S 16 651 /* I2S_TX_FIFO_MOD : R/W ;bitpos:[15:13] ;default: 3'b0 ; */ 652 /*description: */ 653 #define I2S_TX_FIFO_MOD 0x00000007 654 #define I2S_TX_FIFO_MOD_M ((I2S_TX_FIFO_MOD_V)<<(I2S_TX_FIFO_MOD_S)) 655 #define I2S_TX_FIFO_MOD_V 0x7 656 #define I2S_TX_FIFO_MOD_S 13 657 /* I2S_DSCR_EN : R/W ;bitpos:[12] ;default: 1'd1 ; */ 658 /*description: */ 659 #define I2S_DSCR_EN (BIT(12)) 660 #define I2S_DSCR_EN_M (BIT(12)) 661 #define I2S_DSCR_EN_V 0x1 662 #define I2S_DSCR_EN_S 12 663 /* I2S_TX_DATA_NUM : R/W ;bitpos:[11:6] ;default: 6'd32 ; */ 664 /*description: */ 665 #define I2S_TX_DATA_NUM 0x0000003F 666 #define I2S_TX_DATA_NUM_M ((I2S_TX_DATA_NUM_V)<<(I2S_TX_DATA_NUM_S)) 667 #define I2S_TX_DATA_NUM_V 0x3F 668 #define I2S_TX_DATA_NUM_S 6 669 /* I2S_RX_DATA_NUM : R/W ;bitpos:[5:0] ;default: 6'd32 ; */ 670 /*description: */ 671 #define I2S_RX_DATA_NUM 0x0000003F 672 #define I2S_RX_DATA_NUM_M ((I2S_RX_DATA_NUM_V)<<(I2S_RX_DATA_NUM_S)) 673 #define I2S_RX_DATA_NUM_V 0x3F 674 #define I2S_RX_DATA_NUM_S 0 675 676 #define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0024) 677 /* I2S_RX_EOF_NUM : R/W ;bitpos:[31:0] ;default: 32'd64 ; */ 678 /*description: */ 679 #define I2S_RX_EOF_NUM 0xFFFFFFFF 680 #define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) 681 #define I2S_RX_EOF_NUM_V 0xFFFFFFFF 682 #define I2S_RX_EOF_NUM_S 0 683 684 #define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0028) 685 /* I2S_SIGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 686 /*description: */ 687 #define I2S_SIGLE_DATA 0xFFFFFFFF 688 #define I2S_SIGLE_DATA_M ((I2S_SIGLE_DATA_V)<<(I2S_SIGLE_DATA_S)) 689 #define I2S_SIGLE_DATA_V 0xFFFFFFFF 690 #define I2S_SIGLE_DATA_S 0 691 692 #define I2S_CONF_CHAN_REG(i) (REG_I2S_BASE(i) + 0x002c) 693 /* I2S_RX_CHAN_MOD : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ 694 /*description: */ 695 #define I2S_RX_CHAN_MOD 0x00000003 696 #define I2S_RX_CHAN_MOD_M ((I2S_RX_CHAN_MOD_V)<<(I2S_RX_CHAN_MOD_S)) 697 #define I2S_RX_CHAN_MOD_V 0x3 698 #define I2S_RX_CHAN_MOD_S 3 699 /* I2S_TX_CHAN_MOD : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 700 /*description: */ 701 #define I2S_TX_CHAN_MOD 0x00000007 702 #define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) 703 #define I2S_TX_CHAN_MOD_V 0x7 704 #define I2S_TX_CHAN_MOD_S 0 705 706 #define I2S_OUT_LINK_REG(i) (REG_I2S_BASE(i) + 0x0030) 707 /* I2S_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ 708 /*description: */ 709 #define I2S_OUTLINK_PARK (BIT(31)) 710 #define I2S_OUTLINK_PARK_M (BIT(31)) 711 #define I2S_OUTLINK_PARK_V 0x1 712 #define I2S_OUTLINK_PARK_S 31 713 /* I2S_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ 714 /*description: */ 715 #define I2S_OUTLINK_RESTART (BIT(30)) 716 #define I2S_OUTLINK_RESTART_M (BIT(30)) 717 #define I2S_OUTLINK_RESTART_V 0x1 718 #define I2S_OUTLINK_RESTART_S 30 719 /* I2S_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ 720 /*description: */ 721 #define I2S_OUTLINK_START (BIT(29)) 722 #define I2S_OUTLINK_START_M (BIT(29)) 723 #define I2S_OUTLINK_START_V 0x1 724 #define I2S_OUTLINK_START_S 29 725 /* I2S_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ 726 /*description: */ 727 #define I2S_OUTLINK_STOP (BIT(28)) 728 #define I2S_OUTLINK_STOP_M (BIT(28)) 729 #define I2S_OUTLINK_STOP_V 0x1 730 #define I2S_OUTLINK_STOP_S 28 731 /* I2S_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 732 /*description: */ 733 #define I2S_OUTLINK_ADDR 0x000FFFFF 734 #define I2S_OUTLINK_ADDR_M ((I2S_OUTLINK_ADDR_V)<<(I2S_OUTLINK_ADDR_S)) 735 #define I2S_OUTLINK_ADDR_V 0xFFFFF 736 #define I2S_OUTLINK_ADDR_S 0 737 738 #define I2S_IN_LINK_REG(i) (REG_I2S_BASE(i) + 0x0034) 739 /* I2S_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ 740 /*description: */ 741 #define I2S_INLINK_PARK (BIT(31)) 742 #define I2S_INLINK_PARK_M (BIT(31)) 743 #define I2S_INLINK_PARK_V 0x1 744 #define I2S_INLINK_PARK_S 31 745 /* I2S_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ 746 /*description: */ 747 #define I2S_INLINK_RESTART (BIT(30)) 748 #define I2S_INLINK_RESTART_M (BIT(30)) 749 #define I2S_INLINK_RESTART_V 0x1 750 #define I2S_INLINK_RESTART_S 30 751 /* I2S_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ 752 /*description: */ 753 #define I2S_INLINK_START (BIT(29)) 754 #define I2S_INLINK_START_M (BIT(29)) 755 #define I2S_INLINK_START_V 0x1 756 #define I2S_INLINK_START_S 29 757 /* I2S_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ 758 /*description: */ 759 #define I2S_INLINK_STOP (BIT(28)) 760 #define I2S_INLINK_STOP_M (BIT(28)) 761 #define I2S_INLINK_STOP_V 0x1 762 #define I2S_INLINK_STOP_S 28 763 /* I2S_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 764 /*description: */ 765 #define I2S_INLINK_ADDR 0x000FFFFF 766 #define I2S_INLINK_ADDR_M ((I2S_INLINK_ADDR_V)<<(I2S_INLINK_ADDR_S)) 767 #define I2S_INLINK_ADDR_V 0xFFFFF 768 #define I2S_INLINK_ADDR_S 0 769 770 #define I2S_OUT_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0038) 771 /* I2S_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 772 /*description: */ 773 #define I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF 774 #define I2S_OUT_EOF_DES_ADDR_M ((I2S_OUT_EOF_DES_ADDR_V)<<(I2S_OUT_EOF_DES_ADDR_S)) 775 #define I2S_OUT_EOF_DES_ADDR_V 0xFFFFFFFF 776 #define I2S_OUT_EOF_DES_ADDR_S 0 777 778 #define I2S_IN_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x003c) 779 /* I2S_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 780 /*description: */ 781 #define I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF 782 #define I2S_IN_SUC_EOF_DES_ADDR_M ((I2S_IN_SUC_EOF_DES_ADDR_V)<<(I2S_IN_SUC_EOF_DES_ADDR_S)) 783 #define I2S_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF 784 #define I2S_IN_SUC_EOF_DES_ADDR_S 0 785 786 #define I2S_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0040) 787 /* I2S_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 788 /*description: */ 789 #define I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF 790 #define I2S_OUT_EOF_BFR_DES_ADDR_M ((I2S_OUT_EOF_BFR_DES_ADDR_V)<<(I2S_OUT_EOF_BFR_DES_ADDR_S)) 791 #define I2S_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF 792 #define I2S_OUT_EOF_BFR_DES_ADDR_S 0 793 794 #define I2S_AHB_TEST_REG(i) (REG_I2S_BASE(i) + 0x0044) 795 /* I2S_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ 796 /*description: */ 797 #define I2S_AHB_TESTADDR 0x00000003 798 #define I2S_AHB_TESTADDR_M ((I2S_AHB_TESTADDR_V)<<(I2S_AHB_TESTADDR_S)) 799 #define I2S_AHB_TESTADDR_V 0x3 800 #define I2S_AHB_TESTADDR_S 4 801 /* I2S_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 802 /*description: */ 803 #define I2S_AHB_TESTMODE 0x00000007 804 #define I2S_AHB_TESTMODE_M ((I2S_AHB_TESTMODE_V)<<(I2S_AHB_TESTMODE_S)) 805 #define I2S_AHB_TESTMODE_V 0x7 806 #define I2S_AHB_TESTMODE_S 0 807 808 #define I2S_INLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0048) 809 /* I2S_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 810 /*description: */ 811 #define I2S_INLINK_DSCR 0xFFFFFFFF 812 #define I2S_INLINK_DSCR_M ((I2S_INLINK_DSCR_V)<<(I2S_INLINK_DSCR_S)) 813 #define I2S_INLINK_DSCR_V 0xFFFFFFFF 814 #define I2S_INLINK_DSCR_S 0 815 816 #define I2S_INLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x004C) 817 /* I2S_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 818 /*description: */ 819 #define I2S_INLINK_DSCR_BF0 0xFFFFFFFF 820 #define I2S_INLINK_DSCR_BF0_M ((I2S_INLINK_DSCR_BF0_V)<<(I2S_INLINK_DSCR_BF0_S)) 821 #define I2S_INLINK_DSCR_BF0_V 0xFFFFFFFF 822 #define I2S_INLINK_DSCR_BF0_S 0 823 824 #define I2S_INLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x0050) 825 /* I2S_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 826 /*description: */ 827 #define I2S_INLINK_DSCR_BF1 0xFFFFFFFF 828 #define I2S_INLINK_DSCR_BF1_M ((I2S_INLINK_DSCR_BF1_V)<<(I2S_INLINK_DSCR_BF1_S)) 829 #define I2S_INLINK_DSCR_BF1_V 0xFFFFFFFF 830 #define I2S_INLINK_DSCR_BF1_S 0 831 832 #define I2S_OUTLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0054) 833 /* I2S_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 834 /*description: */ 835 #define I2S_OUTLINK_DSCR 0xFFFFFFFF 836 #define I2S_OUTLINK_DSCR_M ((I2S_OUTLINK_DSCR_V)<<(I2S_OUTLINK_DSCR_S)) 837 #define I2S_OUTLINK_DSCR_V 0xFFFFFFFF 838 #define I2S_OUTLINK_DSCR_S 0 839 840 #define I2S_OUTLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x0058) 841 /* I2S_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 842 /*description: */ 843 #define I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF 844 #define I2S_OUTLINK_DSCR_BF0_M ((I2S_OUTLINK_DSCR_BF0_V)<<(I2S_OUTLINK_DSCR_BF0_S)) 845 #define I2S_OUTLINK_DSCR_BF0_V 0xFFFFFFFF 846 #define I2S_OUTLINK_DSCR_BF0_S 0 847 848 #define I2S_OUTLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x005C) 849 /* I2S_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 850 /*description: */ 851 #define I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF 852 #define I2S_OUTLINK_DSCR_BF1_M ((I2S_OUTLINK_DSCR_BF1_V)<<(I2S_OUTLINK_DSCR_BF1_S)) 853 #define I2S_OUTLINK_DSCR_BF1_V 0xFFFFFFFF 854 #define I2S_OUTLINK_DSCR_BF1_S 0 855 856 #define I2S_LC_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) 857 /* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ 858 /*description: */ 859 #define I2S_MEM_TRANS_EN (BIT(13)) 860 #define I2S_MEM_TRANS_EN_M (BIT(13)) 861 #define I2S_MEM_TRANS_EN_V 0x1 862 #define I2S_MEM_TRANS_EN_S 13 863 /* I2S_CHECK_OWNER : R/W ;bitpos:[12] ;default: 1'b0 ; */ 864 /*description: */ 865 #define I2S_CHECK_OWNER (BIT(12)) 866 #define I2S_CHECK_OWNER_M (BIT(12)) 867 #define I2S_CHECK_OWNER_V 0x1 868 #define I2S_CHECK_OWNER_S 12 869 /* I2S_OUT_DATA_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 870 /*description: */ 871 #define I2S_OUT_DATA_BURST_EN (BIT(11)) 872 #define I2S_OUT_DATA_BURST_EN_M (BIT(11)) 873 #define I2S_OUT_DATA_BURST_EN_V 0x1 874 #define I2S_OUT_DATA_BURST_EN_S 11 875 /* I2S_INDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 876 /*description: */ 877 #define I2S_INDSCR_BURST_EN (BIT(10)) 878 #define I2S_INDSCR_BURST_EN_M (BIT(10)) 879 #define I2S_INDSCR_BURST_EN_V 0x1 880 #define I2S_INDSCR_BURST_EN_S 10 881 /* I2S_OUTDSCR_BURST_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 882 /*description: */ 883 #define I2S_OUTDSCR_BURST_EN (BIT(9)) 884 #define I2S_OUTDSCR_BURST_EN_M (BIT(9)) 885 #define I2S_OUTDSCR_BURST_EN_V 0x1 886 #define I2S_OUTDSCR_BURST_EN_S 9 887 /* I2S_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */ 888 /*description: */ 889 #define I2S_OUT_EOF_MODE (BIT(8)) 890 #define I2S_OUT_EOF_MODE_M (BIT(8)) 891 #define I2S_OUT_EOF_MODE_V 0x1 892 #define I2S_OUT_EOF_MODE_S 8 893 /* I2S_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ 894 /*description: */ 895 #define I2S_OUT_NO_RESTART_CLR (BIT(7)) 896 #define I2S_OUT_NO_RESTART_CLR_M (BIT(7)) 897 #define I2S_OUT_NO_RESTART_CLR_V 0x1 898 #define I2S_OUT_NO_RESTART_CLR_S 7 899 /* I2S_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ 900 /*description: */ 901 #define I2S_OUT_AUTO_WRBACK (BIT(6)) 902 #define I2S_OUT_AUTO_WRBACK_M (BIT(6)) 903 #define I2S_OUT_AUTO_WRBACK_V 0x1 904 #define I2S_OUT_AUTO_WRBACK_S 6 905 /* I2S_IN_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 906 /*description: */ 907 #define I2S_IN_LOOP_TEST (BIT(5)) 908 #define I2S_IN_LOOP_TEST_M (BIT(5)) 909 #define I2S_IN_LOOP_TEST_V 0x1 910 #define I2S_IN_LOOP_TEST_S 5 911 /* I2S_OUT_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 912 /*description: */ 913 #define I2S_OUT_LOOP_TEST (BIT(4)) 914 #define I2S_OUT_LOOP_TEST_M (BIT(4)) 915 #define I2S_OUT_LOOP_TEST_V 0x1 916 #define I2S_OUT_LOOP_TEST_S 4 917 /* I2S_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 918 /*description: */ 919 #define I2S_AHBM_RST (BIT(3)) 920 #define I2S_AHBM_RST_M (BIT(3)) 921 #define I2S_AHBM_RST_V 0x1 922 #define I2S_AHBM_RST_S 3 923 /* I2S_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 924 /*description: */ 925 #define I2S_AHBM_FIFO_RST (BIT(2)) 926 #define I2S_AHBM_FIFO_RST_M (BIT(2)) 927 #define I2S_AHBM_FIFO_RST_V 0x1 928 #define I2S_AHBM_FIFO_RST_S 2 929 /* I2S_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 930 /*description: */ 931 #define I2S_OUT_RST (BIT(1)) 932 #define I2S_OUT_RST_M (BIT(1)) 933 #define I2S_OUT_RST_V 0x1 934 #define I2S_OUT_RST_S 1 935 /* I2S_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ 936 /*description: */ 937 #define I2S_IN_RST (BIT(0)) 938 #define I2S_IN_RST_M (BIT(0)) 939 #define I2S_IN_RST_V 0x1 940 #define I2S_IN_RST_S 0 941 942 #define I2S_OUTFIFO_PUSH_REG(i) (REG_I2S_BASE(i) + 0x0064) 943 /* I2S_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ 944 /*description: */ 945 #define I2S_OUTFIFO_PUSH (BIT(16)) 946 #define I2S_OUTFIFO_PUSH_M (BIT(16)) 947 #define I2S_OUTFIFO_PUSH_V 0x1 948 #define I2S_OUTFIFO_PUSH_S 16 949 /* I2S_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ 950 /*description: */ 951 #define I2S_OUTFIFO_WDATA 0x000001FF 952 #define I2S_OUTFIFO_WDATA_M ((I2S_OUTFIFO_WDATA_V)<<(I2S_OUTFIFO_WDATA_S)) 953 #define I2S_OUTFIFO_WDATA_V 0x1FF 954 #define I2S_OUTFIFO_WDATA_S 0 955 956 #define I2S_INFIFO_POP_REG(i) (REG_I2S_BASE(i) + 0x0068) 957 /* I2S_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ 958 /*description: */ 959 #define I2S_INFIFO_POP (BIT(16)) 960 #define I2S_INFIFO_POP_M (BIT(16)) 961 #define I2S_INFIFO_POP_V 0x1 962 #define I2S_INFIFO_POP_S 16 963 /* I2S_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */ 964 /*description: */ 965 #define I2S_INFIFO_RDATA 0x00000FFF 966 #define I2S_INFIFO_RDATA_M ((I2S_INFIFO_RDATA_V)<<(I2S_INFIFO_RDATA_S)) 967 #define I2S_INFIFO_RDATA_V 0xFFF 968 #define I2S_INFIFO_RDATA_S 0 969 970 #define I2S_LC_STATE0_REG(i) (REG_I2S_BASE(i) + 0x006C) 971 /* I2S_LC_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 972 /*description: */ 973 #define I2S_LC_STATE0 0xFFFFFFFF 974 #define I2S_LC_STATE0_M ((I2S_LC_STATE0_V)<<(I2S_LC_STATE0_S)) 975 #define I2S_LC_STATE0_V 0xFFFFFFFF 976 #define I2S_LC_STATE0_S 0 977 978 #define I2S_LC_STATE1_REG(i) (REG_I2S_BASE(i) + 0x0070) 979 /* I2S_LC_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 980 /*description: */ 981 #define I2S_LC_STATE1 0xFFFFFFFF 982 #define I2S_LC_STATE1_M ((I2S_LC_STATE1_V)<<(I2S_LC_STATE1_S)) 983 #define I2S_LC_STATE1_V 0xFFFFFFFF 984 #define I2S_LC_STATE1_S 0 985 986 #define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0074) 987 /* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ 988 /*description: */ 989 #define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) 990 #define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) 991 #define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 992 #define I2S_LC_FIFO_TIMEOUT_ENA_S 11 993 /* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ 994 /*description: */ 995 #define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 996 #define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) 997 #define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 998 #define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 999 /* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ 1000 /*description: */ 1001 #define I2S_LC_FIFO_TIMEOUT 0x000000FF 1002 #define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) 1003 #define I2S_LC_FIFO_TIMEOUT_V 0xFF 1004 #define I2S_LC_FIFO_TIMEOUT_S 0 1005 1006 #define I2S_CVSD_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0080) 1007 /* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */ 1008 /*description: */ 1009 #define I2S_CVSD_Y_MIN 0x0000FFFF 1010 #define I2S_CVSD_Y_MIN_M ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S)) 1011 #define I2S_CVSD_Y_MIN_V 0xFFFF 1012 #define I2S_CVSD_Y_MIN_S 16 1013 /* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */ 1014 /*description: */ 1015 #define I2S_CVSD_Y_MAX 0x0000FFFF 1016 #define I2S_CVSD_Y_MAX_M ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S)) 1017 #define I2S_CVSD_Y_MAX_V 0xFFFF 1018 #define I2S_CVSD_Y_MAX_S 0 1019 1020 #define I2S_CVSD_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0084) 1021 /* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ 1022 /*description: */ 1023 #define I2S_CVSD_SIGMA_MIN 0x0000FFFF 1024 #define I2S_CVSD_SIGMA_MIN_M ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S)) 1025 #define I2S_CVSD_SIGMA_MIN_V 0xFFFF 1026 #define I2S_CVSD_SIGMA_MIN_S 16 1027 /* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */ 1028 /*description: */ 1029 #define I2S_CVSD_SIGMA_MAX 0x0000FFFF 1030 #define I2S_CVSD_SIGMA_MAX_M ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S)) 1031 #define I2S_CVSD_SIGMA_MAX_V 0xFFFF 1032 #define I2S_CVSD_SIGMA_MAX_S 0 1033 1034 #define I2S_CVSD_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0088) 1035 /* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */ 1036 /*description: */ 1037 #define I2S_CVSD_H 0x00000007 1038 #define I2S_CVSD_H_M ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S)) 1039 #define I2S_CVSD_H_V 0x7 1040 #define I2S_CVSD_H_S 16 1041 /* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */ 1042 /*description: */ 1043 #define I2S_CVSD_BETA 0x000003FF 1044 #define I2S_CVSD_BETA_M ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S)) 1045 #define I2S_CVSD_BETA_V 0x3FF 1046 #define I2S_CVSD_BETA_S 6 1047 /* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */ 1048 /*description: */ 1049 #define I2S_CVSD_J 0x00000007 1050 #define I2S_CVSD_J_M ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S)) 1051 #define I2S_CVSD_J_V 0x7 1052 #define I2S_CVSD_J_S 3 1053 /* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */ 1054 /*description: */ 1055 #define I2S_CVSD_K 0x00000007 1056 #define I2S_CVSD_K_M ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S)) 1057 #define I2S_CVSD_K_V 0x7 1058 #define I2S_CVSD_K_S 0 1059 1060 #define I2S_PLC_CONF0_REG(i) (REG_I2S_BASE(i) + 0x008C) 1061 /* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ 1062 /*description: */ 1063 #define I2S_N_MIN_ERR 0x00000007 1064 #define I2S_N_MIN_ERR_M ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S)) 1065 #define I2S_N_MIN_ERR_V 0x7 1066 #define I2S_N_MIN_ERR_S 25 1067 /* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */ 1068 /*description: */ 1069 #define I2S_PACK_LEN_8K 0x0000001F 1070 #define I2S_PACK_LEN_8K_M ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S)) 1071 #define I2S_PACK_LEN_8K_V 0x1F 1072 #define I2S_PACK_LEN_8K_S 20 1073 /* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */ 1074 /*description: */ 1075 #define I2S_MAX_SLIDE_SAMPLE 0x000000FF 1076 #define I2S_MAX_SLIDE_SAMPLE_M ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S)) 1077 #define I2S_MAX_SLIDE_SAMPLE_V 0xFF 1078 #define I2S_MAX_SLIDE_SAMPLE_S 12 1079 /* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */ 1080 /*description: */ 1081 #define I2S_SHIFT_RATE 0x00000007 1082 #define I2S_SHIFT_RATE_M ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S)) 1083 #define I2S_SHIFT_RATE_V 0x7 1084 #define I2S_SHIFT_RATE_S 9 1085 /* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */ 1086 /*description: */ 1087 #define I2S_N_ERR_SEG 0x00000007 1088 #define I2S_N_ERR_SEG_M ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S)) 1089 #define I2S_N_ERR_SEG_V 0x7 1090 #define I2S_N_ERR_SEG_S 6 1091 /* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */ 1092 /*description: */ 1093 #define I2S_GOOD_PACK_MAX 0x0000003F 1094 #define I2S_GOOD_PACK_MAX_M ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S)) 1095 #define I2S_GOOD_PACK_MAX_V 0x3F 1096 #define I2S_GOOD_PACK_MAX_S 0 1097 1098 #define I2S_PLC_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0090) 1099 /* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */ 1100 /*description: */ 1101 #define I2S_SLIDE_WIN_LEN 0x000000FF 1102 #define I2S_SLIDE_WIN_LEN_M ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S)) 1103 #define I2S_SLIDE_WIN_LEN_V 0xFF 1104 #define I2S_SLIDE_WIN_LEN_S 24 1105 /* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */ 1106 /*description: */ 1107 #define I2S_BAD_OLA_WIN2_PARA 0x000000FF 1108 #define I2S_BAD_OLA_WIN2_PARA_M ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S)) 1109 #define I2S_BAD_OLA_WIN2_PARA_V 0xFF 1110 #define I2S_BAD_OLA_WIN2_PARA_S 16 1111 /* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */ 1112 /*description: */ 1113 #define I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F 1114 #define I2S_BAD_OLA_WIN2_PARA_SHIFT_M ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S)) 1115 #define I2S_BAD_OLA_WIN2_PARA_SHIFT_V 0xF 1116 #define I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12 1117 /* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */ 1118 /*description: */ 1119 #define I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F 1120 #define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S)) 1121 #define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V 0xF 1122 #define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8 1123 /* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */ 1124 /*description: */ 1125 #define I2S_BAD_CEF_ATTEN_PARA 0x000000FF 1126 #define I2S_BAD_CEF_ATTEN_PARA_M ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S)) 1127 #define I2S_BAD_CEF_ATTEN_PARA_V 0xFF 1128 #define I2S_BAD_CEF_ATTEN_PARA_S 0 1129 1130 #define I2S_PLC_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0094) 1131 /* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */ 1132 /*description: */ 1133 #define I2S_MIN_PERIOD 0x0000001F 1134 #define I2S_MIN_PERIOD_M ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S)) 1135 #define I2S_MIN_PERIOD_V 0x1F 1136 #define I2S_MIN_PERIOD_S 2 1137 /* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 1138 /*description: */ 1139 #define I2S_CVSD_SEG_MOD 0x00000003 1140 #define I2S_CVSD_SEG_MOD_M ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S)) 1141 #define I2S_CVSD_SEG_MOD_V 0x3 1142 #define I2S_CVSD_SEG_MOD_S 0 1143 1144 #define I2S_ESCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0098) 1145 /* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1146 /*description: */ 1147 #define I2S_PLC2DMA_EN (BIT(12)) 1148 #define I2S_PLC2DMA_EN_M (BIT(12)) 1149 #define I2S_PLC2DMA_EN_V 0x1 1150 #define I2S_PLC2DMA_EN_S 12 1151 /* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1152 /*description: */ 1153 #define I2S_PLC_EN (BIT(11)) 1154 #define I2S_PLC_EN_M (BIT(11)) 1155 #define I2S_PLC_EN_V 0x1 1156 #define I2S_PLC_EN_S 11 1157 /* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1158 /*description: */ 1159 #define I2S_CVSD_DEC_RESET (BIT(10)) 1160 #define I2S_CVSD_DEC_RESET_M (BIT(10)) 1161 #define I2S_CVSD_DEC_RESET_V 0x1 1162 #define I2S_CVSD_DEC_RESET_S 10 1163 /* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1164 /*description: */ 1165 #define I2S_CVSD_DEC_START (BIT(9)) 1166 #define I2S_CVSD_DEC_START_M (BIT(9)) 1167 #define I2S_CVSD_DEC_START_V 0x1 1168 #define I2S_CVSD_DEC_START_S 9 1169 /* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1170 /*description: */ 1171 #define I2S_ESCO_CVSD_INF_EN (BIT(8)) 1172 #define I2S_ESCO_CVSD_INF_EN_M (BIT(8)) 1173 #define I2S_ESCO_CVSD_INF_EN_V 0x1 1174 #define I2S_ESCO_CVSD_INF_EN_S 8 1175 /* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */ 1176 /*description: */ 1177 #define I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F 1178 #define I2S_ESCO_CVSD_PACK_LEN_8K_M ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S)) 1179 #define I2S_ESCO_CVSD_PACK_LEN_8K_V 0x1F 1180 #define I2S_ESCO_CVSD_PACK_LEN_8K_S 3 1181 /* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1182 /*description: */ 1183 #define I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2)) 1184 #define I2S_ESCO_CVSD_DEC_PACK_ERR_M (BIT(2)) 1185 #define I2S_ESCO_CVSD_DEC_PACK_ERR_V 0x1 1186 #define I2S_ESCO_CVSD_DEC_PACK_ERR_S 2 1187 /* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */ 1188 /*description: */ 1189 #define I2S_ESCO_CHAN_MOD (BIT(1)) 1190 #define I2S_ESCO_CHAN_MOD_M (BIT(1)) 1191 #define I2S_ESCO_CHAN_MOD_V 0x1 1192 #define I2S_ESCO_CHAN_MOD_S 1 1193 /* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ 1194 /*description: */ 1195 #define I2S_ESCO_EN (BIT(0)) 1196 #define I2S_ESCO_EN_M (BIT(0)) 1197 #define I2S_ESCO_EN_V 0x1 1198 #define I2S_ESCO_EN_S 0 1199 1200 #define I2S_SCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x009c) 1201 /* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */ 1202 /*description: */ 1203 #define I2S_CVSD_ENC_RESET (BIT(3)) 1204 #define I2S_CVSD_ENC_RESET_M (BIT(3)) 1205 #define I2S_CVSD_ENC_RESET_V 0x1 1206 #define I2S_CVSD_ENC_RESET_S 3 1207 /* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */ 1208 /*description: */ 1209 #define I2S_CVSD_ENC_START (BIT(2)) 1210 #define I2S_CVSD_ENC_START_M (BIT(2)) 1211 #define I2S_CVSD_ENC_START_V 0x1 1212 #define I2S_CVSD_ENC_START_S 2 1213 /* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ 1214 /*description: */ 1215 #define I2S_SCO_NO_I2S_EN (BIT(1)) 1216 #define I2S_SCO_NO_I2S_EN_M (BIT(1)) 1217 #define I2S_SCO_NO_I2S_EN_V 0x1 1218 #define I2S_SCO_NO_I2S_EN_S 1 1219 /* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ 1220 /*description: */ 1221 #define I2S_SCO_WITH_I2S_EN (BIT(0)) 1222 #define I2S_SCO_WITH_I2S_EN_M (BIT(0)) 1223 #define I2S_SCO_WITH_I2S_EN_V 0x1 1224 #define I2S_SCO_WITH_I2S_EN_S 0 1225 1226 #define I2S_CONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0) 1227 /* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ 1228 /*description: */ 1229 #define I2S_TX_ZEROS_RM_EN (BIT(9)) 1230 #define I2S_TX_ZEROS_RM_EN_M (BIT(9)) 1231 #define I2S_TX_ZEROS_RM_EN_V 0x1 1232 #define I2S_TX_ZEROS_RM_EN_S 9 1233 /* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1234 /*description: */ 1235 #define I2S_TX_STOP_EN (BIT(8)) 1236 #define I2S_TX_STOP_EN_M (BIT(8)) 1237 #define I2S_TX_STOP_EN_V 0x1 1238 #define I2S_TX_STOP_EN_S 8 1239 /* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */ 1240 /*description: */ 1241 #define I2S_RX_PCM_BYPASS (BIT(7)) 1242 #define I2S_RX_PCM_BYPASS_M (BIT(7)) 1243 #define I2S_RX_PCM_BYPASS_V 0x1 1244 #define I2S_RX_PCM_BYPASS_S 7 1245 /* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ 1246 /*description: */ 1247 #define I2S_RX_PCM_CONF 0x00000007 1248 #define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) 1249 #define I2S_RX_PCM_CONF_V 0x7 1250 #define I2S_RX_PCM_CONF_S 4 1251 /* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */ 1252 /*description: */ 1253 #define I2S_TX_PCM_BYPASS (BIT(3)) 1254 #define I2S_TX_PCM_BYPASS_M (BIT(3)) 1255 #define I2S_TX_PCM_BYPASS_V 0x1 1256 #define I2S_TX_PCM_BYPASS_S 3 1257 /* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */ 1258 /*description: */ 1259 #define I2S_TX_PCM_CONF 0x00000007 1260 #define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) 1261 #define I2S_TX_PCM_CONF_V 0x7 1262 #define I2S_TX_PCM_CONF_S 0 1263 1264 #define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4) 1265 /* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */ 1266 /*description: */ 1267 #define I2S_PLC_MEM_FORCE_PU (BIT(3)) 1268 #define I2S_PLC_MEM_FORCE_PU_M (BIT(3)) 1269 #define I2S_PLC_MEM_FORCE_PU_V 0x1 1270 #define I2S_PLC_MEM_FORCE_PU_S 3 1271 /* I2S_PLC_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */ 1272 /*description: */ 1273 #define I2S_PLC_MEM_FORCE_PD (BIT(2)) 1274 #define I2S_PLC_MEM_FORCE_PD_M (BIT(2)) 1275 #define I2S_PLC_MEM_FORCE_PD_V 0x1 1276 #define I2S_PLC_MEM_FORCE_PD_S 2 1277 /* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */ 1278 /*description: */ 1279 #define I2S_FIFO_FORCE_PU (BIT(1)) 1280 #define I2S_FIFO_FORCE_PU_M (BIT(1)) 1281 #define I2S_FIFO_FORCE_PU_V 0x1 1282 #define I2S_FIFO_FORCE_PU_S 1 1283 /* I2S_FIFO_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ 1284 /*description: */ 1285 #define I2S_FIFO_FORCE_PD (BIT(0)) 1286 #define I2S_FIFO_FORCE_PD_M (BIT(0)) 1287 #define I2S_FIFO_FORCE_PD_V 0x1 1288 #define I2S_FIFO_FORCE_PD_S 0 1289 1290 #define I2S_CONF2_REG(i) (REG_I2S_BASE(i) + 0x00a8) 1291 /* I2S_INTER_VALID_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1292 /*description: */ 1293 #define I2S_INTER_VALID_EN (BIT(7)) 1294 #define I2S_INTER_VALID_EN_M (BIT(7)) 1295 #define I2S_INTER_VALID_EN_V 0x1 1296 #define I2S_INTER_VALID_EN_S 7 1297 /* I2S_EXT_ADC_START_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1298 /*description: */ 1299 #define I2S_EXT_ADC_START_EN (BIT(6)) 1300 #define I2S_EXT_ADC_START_EN_M (BIT(6)) 1301 #define I2S_EXT_ADC_START_EN_V 0x1 1302 #define I2S_EXT_ADC_START_EN_S 6 1303 /* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1304 /*description: */ 1305 #define I2S_LCD_EN (BIT(5)) 1306 #define I2S_LCD_EN_M (BIT(5)) 1307 #define I2S_LCD_EN_V 0x1 1308 #define I2S_LCD_EN_S 5 1309 /* I2S_DATA_ENABLE : R/W ;bitpos:[4] ;default: 1'h0 ; */ 1310 /*description: */ 1311 #define I2S_DATA_ENABLE (BIT(4)) 1312 #define I2S_DATA_ENABLE_M (BIT(4)) 1313 #define I2S_DATA_ENABLE_V 0x1 1314 #define I2S_DATA_ENABLE_S 4 1315 /* I2S_DATA_ENABLE_TEST_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ 1316 /*description: */ 1317 #define I2S_DATA_ENABLE_TEST_EN (BIT(3)) 1318 #define I2S_DATA_ENABLE_TEST_EN_M (BIT(3)) 1319 #define I2S_DATA_ENABLE_TEST_EN_V 0x1 1320 #define I2S_DATA_ENABLE_TEST_EN_S 3 1321 /* I2S_LCD_TX_SDX2_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ 1322 /*description: */ 1323 #define I2S_LCD_TX_SDX2_EN (BIT(2)) 1324 #define I2S_LCD_TX_SDX2_EN_M (BIT(2)) 1325 #define I2S_LCD_TX_SDX2_EN_V 0x1 1326 #define I2S_LCD_TX_SDX2_EN_S 2 1327 /* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 1328 /*description: */ 1329 #define I2S_LCD_TX_WRX2_EN (BIT(1)) 1330 #define I2S_LCD_TX_WRX2_EN_M (BIT(1)) 1331 #define I2S_LCD_TX_WRX2_EN_V 0x1 1332 #define I2S_LCD_TX_WRX2_EN_S 1 1333 /* I2S_CAMERA_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 1334 /*description: */ 1335 #define I2S_CAMERA_EN (BIT(0)) 1336 #define I2S_CAMERA_EN_M (BIT(0)) 1337 #define I2S_CAMERA_EN_V 0x1 1338 #define I2S_CAMERA_EN_S 0 1339 1340 #define I2S_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00ac) 1341 /* I2S_CLKA_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ 1342 /*description: */ 1343 #define I2S_CLKA_ENA (BIT(21)) 1344 #define I2S_CLKA_ENA_M (BIT(21)) 1345 #define I2S_CLKA_ENA_V 0x1 1346 #define I2S_CLKA_ENA_S 21 1347 /* I2S_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 1348 /*description: */ 1349 #define I2S_CLK_EN (BIT(20)) 1350 #define I2S_CLK_EN_M (BIT(20)) 1351 #define I2S_CLK_EN_V 0x1 1352 #define I2S_CLK_EN_S 20 1353 /* I2S_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ 1354 /*description: */ 1355 #define I2S_CLKM_DIV_A 0x0000003F 1356 #define I2S_CLKM_DIV_A_M ((I2S_CLKM_DIV_A_V)<<(I2S_CLKM_DIV_A_S)) 1357 #define I2S_CLKM_DIV_A_V 0x3F 1358 #define I2S_CLKM_DIV_A_S 14 1359 /* I2S_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ 1360 /*description: */ 1361 #define I2S_CLKM_DIV_B 0x0000003F 1362 #define I2S_CLKM_DIV_B_M ((I2S_CLKM_DIV_B_V)<<(I2S_CLKM_DIV_B_S)) 1363 #define I2S_CLKM_DIV_B_V 0x3F 1364 #define I2S_CLKM_DIV_B_S 8 1365 /* I2S_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ 1366 /*description: */ 1367 #define I2S_CLKM_DIV_NUM 0x000000FF 1368 #define I2S_CLKM_DIV_NUM_M ((I2S_CLKM_DIV_NUM_V)<<(I2S_CLKM_DIV_NUM_S)) 1369 #define I2S_CLKM_DIV_NUM_V 0xFF 1370 #define I2S_CLKM_DIV_NUM_S 0 1371 1372 #define I2S_SAMPLE_RATE_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b0) 1373 /* I2S_RX_BITS_MOD : R/W ;bitpos:[23:18] ;default: 6'd16 ; */ 1374 /*description: */ 1375 #define I2S_RX_BITS_MOD 0x0000003F 1376 #define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) 1377 #define I2S_RX_BITS_MOD_V 0x3F 1378 #define I2S_RX_BITS_MOD_S 18 1379 /* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */ 1380 /*description: */ 1381 #define I2S_TX_BITS_MOD 0x0000003F 1382 #define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) 1383 #define I2S_TX_BITS_MOD_V 0x3F 1384 #define I2S_TX_BITS_MOD_S 12 1385 /* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[11:6] ;default: 6'd6 ; */ 1386 /*description: */ 1387 #define I2S_RX_BCK_DIV_NUM 0x0000003F 1388 #define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) 1389 #define I2S_RX_BCK_DIV_NUM_V 0x3F 1390 #define I2S_RX_BCK_DIV_NUM_S 6 1391 /* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[5:0] ;default: 6'd6 ; */ 1392 /*description: */ 1393 #define I2S_TX_BCK_DIV_NUM 0x0000003F 1394 #define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) 1395 #define I2S_TX_BCK_DIV_NUM_V 0x3F 1396 #define I2S_TX_BCK_DIV_NUM_S 0 1397 1398 #define I2S_PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b4) 1399 /* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */ 1400 /*description: */ 1401 #define I2S_TX_PDM_HP_BYPASS (BIT(25)) 1402 #define I2S_TX_PDM_HP_BYPASS_M (BIT(25)) 1403 #define I2S_TX_PDM_HP_BYPASS_V 0x1 1404 #define I2S_TX_PDM_HP_BYPASS_S 25 1405 /* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */ 1406 /*description: */ 1407 #define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24)) 1408 #define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(24)) 1409 #define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 1410 #define I2S_RX_PDM_SINC_DSR_16_EN_S 24 1411 /* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */ 1412 /*description: */ 1413 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 1414 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) 1415 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 1416 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22 1417 /* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */ 1418 /*description: */ 1419 #define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 1420 #define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) 1421 #define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 1422 #define I2S_TX_PDM_SINC_IN_SHIFT_S 20 1423 /* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */ 1424 /*description: */ 1425 #define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 1426 #define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) 1427 #define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 1428 #define I2S_TX_PDM_LP_IN_SHIFT_S 18 1429 /* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */ 1430 /*description: */ 1431 #define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 1432 #define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) 1433 #define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 1434 #define I2S_TX_PDM_HP_IN_SHIFT_S 16 1435 /* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ 1436 /*description: */ 1437 #define I2S_TX_PDM_PRESCALE 0x000000FF 1438 #define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) 1439 #define I2S_TX_PDM_PRESCALE_V 0xFF 1440 #define I2S_TX_PDM_PRESCALE_S 8 1441 /* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */ 1442 /*description: */ 1443 #define I2S_TX_PDM_SINC_OSR2 0x0000000F 1444 #define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) 1445 #define I2S_TX_PDM_SINC_OSR2_V 0xF 1446 #define I2S_TX_PDM_SINC_OSR2_S 4 1447 /* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ 1448 /*description: */ 1449 #define I2S_PDM2PCM_CONV_EN (BIT(3)) 1450 #define I2S_PDM2PCM_CONV_EN_M (BIT(3)) 1451 #define I2S_PDM2PCM_CONV_EN_V 0x1 1452 #define I2S_PDM2PCM_CONV_EN_S 3 1453 /* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ 1454 /*description: */ 1455 #define I2S_PCM2PDM_CONV_EN (BIT(2)) 1456 #define I2S_PCM2PDM_CONV_EN_M (BIT(2)) 1457 #define I2S_PCM2PDM_CONV_EN_V 0x1 1458 #define I2S_PCM2PDM_CONV_EN_S 2 1459 /* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 1460 /*description: */ 1461 #define I2S_RX_PDM_EN (BIT(1)) 1462 #define I2S_RX_PDM_EN_M (BIT(1)) 1463 #define I2S_RX_PDM_EN_V 0x1 1464 #define I2S_RX_PDM_EN_S 1 1465 /* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 1466 /*description: */ 1467 #define I2S_TX_PDM_EN (BIT(0)) 1468 #define I2S_TX_PDM_EN_M (BIT(0)) 1469 #define I2S_TX_PDM_EN_V 0x1 1470 #define I2S_TX_PDM_EN_S 0 1471 1472 #define I2S_PDM_FREQ_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b8) 1473 /* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */ 1474 /*description: */ 1475 #define I2S_TX_PDM_FP 0x000003FF 1476 #define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) 1477 #define I2S_TX_PDM_FP_V 0x3FF 1478 #define I2S_TX_PDM_FP_S 10 1479 /* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */ 1480 /*description: */ 1481 #define I2S_TX_PDM_FS 0x000003FF 1482 #define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) 1483 #define I2S_TX_PDM_FS_V 0x3FF 1484 #define I2S_TX_PDM_FS_S 0 1485 1486 #define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x00bc) 1487 /* I2S_RX_FIFO_RESET_BACK : RO ;bitpos:[2] ;default: 1'b1 ; */ 1488 /*description: */ 1489 #define I2S_RX_FIFO_RESET_BACK (BIT(2)) 1490 #define I2S_RX_FIFO_RESET_BACK_M (BIT(2)) 1491 #define I2S_RX_FIFO_RESET_BACK_V 0x1 1492 #define I2S_RX_FIFO_RESET_BACK_S 2 1493 /* I2S_TX_FIFO_RESET_BACK : RO ;bitpos:[1] ;default: 1'b1 ; */ 1494 /*description: */ 1495 #define I2S_TX_FIFO_RESET_BACK (BIT(1)) 1496 #define I2S_TX_FIFO_RESET_BACK_M (BIT(1)) 1497 #define I2S_TX_FIFO_RESET_BACK_V 0x1 1498 #define I2S_TX_FIFO_RESET_BACK_S 1 1499 /* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ 1500 /*description: */ 1501 #define I2S_TX_IDLE (BIT(0)) 1502 #define I2S_TX_IDLE_M (BIT(0)) 1503 #define I2S_TX_IDLE_V 0x1 1504 #define I2S_TX_IDLE_S 0 1505 1506 #define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x00fc) 1507 /* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h1604201 ; */ 1508 /*description: */ 1509 #define I2S_I2SDATE 0xFFFFFFFF 1510 #define I2S_I2SDATE_M ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S)) 1511 #define I2S_I2SDATE_V 0xFFFFFFFF 1512 #define I2S_I2SDATE_S 0 1513 1514 1515 1516 1517 #endif /*_SOC_I2S_REG_H_ */ 1518
