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Searched refs:HAL_FORCE_MODIFY_U32_REG_FIELD (Results 1 – 25 of 114) sorted by relevance

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/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dlp_aon_ll.h37 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1); in lp_aon_ll_ext1_clear_wakeup_status()
50 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask); in lp_aon_ll_ext1_set_wakeup_pins()
51 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask); in lp_aon_ll_ext1_set_wakeup_pins()
59 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0); in lp_aon_ll_ext1_clear_wakeup_pins()
Dtemperature_sensor_ll.h143 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_clk_div, clk_div); in temperature_sensor_ll_set_clk_div()
186 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_low, th_low); in temperature_sensor_ll_set_th_low_val()
196 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_high, th_high); in temperature_sensor_ll_set_th_high_val()
243 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_sample, saradc_tsens_sample_rate, rate); in temperature_sensor_ll_set_sample_rate()
Duart_ll.h40 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \
42 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \
477 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd); in uart_ll_set_rxfifo_full_thr()
491 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd); in uart_ll_set_txfifo_empty_thr()
534 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); in uart_ll_tx_break()
555 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs); in uart_ll_set_hw_flow_ctrl()
601 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, flow_ctrl->xon_thrd); in uart_ll_set_sw_flow_ctrl()
602 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, flow_ctrl->xoff_thrd); in uart_ll_set_sw_flow_ctrl()
603 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); in uart_ll_set_sw_flow_ctrl()
604 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); in uart_ll_set_sw_flow_ctrl()
[all …]
Dsdm_ll.h40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
Dtwai_ll.h469 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->err_warning_limit, err_warning_limit, ewl); in twai_ll_set_err_warn_lim()
512 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_err_cnt, rx_err_cnt, rec); in twai_ll_set_rec()
542 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_err_cnt, tx_err_cnt, tec); in twai_ll_set_tec()
562 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
563 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
734 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, (divider / 2) - 1); in twai_ll_set_clkout()
738 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 255); in twai_ll_set_clkout()
741 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 0); in twai_ll_set_clkout()
Dadc_ll.h112 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_rstb_wait, rst_wait); in adc_ll_digi_set_fsm_time()
114 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_xpd_wait, start_wait); in adc_ll_digi_set_fsm_time()
116 …HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_standby_wait, standby_wai… in adc_ll_digi_set_fsm_time()
141 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div); in adc_ll_digi_set_clk_div()
152 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl2, saradc_saradc_max_meas_num, meas_num); in adc_ll_digi_set_convert_limit_num()
296 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num); in adc_ll_digi_controller_clk_div()
453 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_dma_conf, saradc_apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dlp_aon_ll.h37 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1); in lp_aon_ll_ext1_clear_wakeup_status()
50 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask); in lp_aon_ll_ext1_set_wakeup_pins()
51 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask); in lp_aon_ll_ext1_set_wakeup_pins()
59 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0); in lp_aon_ll_ext1_clear_wakeup_pins()
Drtc_io_ll.h65 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); in rtcio_ll_function_select()
72 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); in rtcio_ll_function_select()
83 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1ts, enable_w1ts, BIT(rtcio_num)); in rtcio_ll_output_enable()
93 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1tc, enable_w1tc, BIT(rtcio_num)); in rtcio_ll_output_disable()
105 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_data_w1ts, BIT(rtcio_num)); in rtcio_ll_set_level()
107 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_data_w1tc, BIT(rtcio_num)); in rtcio_ll_set_level()
380 HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_w1tc, 0xff); in rtcio_ll_clear_interrupt_status()
Dtemperature_sensor_ll.h143 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_apb_tsens_ctrl, saradc_tsens_clk_div, clk_div); in temperature_sensor_ll_set_clk_div()
186 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_low, th_low); in temperature_sensor_ll_set_th_low_val()
196 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_wake, saradc_wakeup_th_high, th_high); in temperature_sensor_ll_set_th_high_val()
243 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.tsens_sample, saradc_tsens_sample_rate, rate); in temperature_sensor_ll_set_sample_rate()
Duart_ll.h38 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart0_##reg_suffix, uart0_##field_suffix, (val)) \
40 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.uart1_##reg_suffix, uart1_##field_suffix, (val)) \
456 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd); in uart_ll_set_rxfifo_full_thr()
470 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd); in uart_ll_set_txfifo_empty_thr()
513 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); in uart_ll_tx_break()
534 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs); in uart_ll_set_hw_flow_ctrl()
580 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, flow_ctrl->xon_thrd); in uart_ll_set_sw_flow_ctrl()
581 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, flow_ctrl->xoff_thrd); in uart_ll_set_sw_flow_ctrl()
582 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); in uart_ll_set_sw_flow_ctrl()
583 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); in uart_ll_set_sw_flow_ctrl()
[all …]
Dsdm_ll.h40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
Dparlio_ll.h90 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_rx_conf, parl_clk_rx_div_num, div - 1); in parlio_ll_rx_set_clock_div()
151 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_cfg0, rx_data_bytelen, bitlen / 8); in parlio_ll_rx_set_recv_bit_len()
318 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_cfg1, rx_timeout_threshold, thres); in parlio_ll_rx_set_timeout_thres()
372 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_tx_conf, parl_clk_tx_div_num, div - 1); in parlio_ll_tx_set_clock_div()
410 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cfg0, tx_bytelen, bitlen / 8); in parlio_ll_tx_set_trans_bit_len()
530 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cfg1, tx_idle_value, value); in parlio_ll_tx_set_idle_data_value()
Dtwai_ll.h483 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->err_warning_limit, err_warning_limit, ewl); in twai_ll_set_err_warn_lim()
526 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_err_cnt, rx_err_cnt, rec); in twai_ll_set_rec()
556 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_err_cnt, tx_err_cnt, tec); in twai_ll_set_tec()
576 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
577 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
748 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, (divider / 2) - 1); in twai_ll_set_clkout()
752 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 255); in twai_ll_set_clkout()
755 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider, cd, 0); in twai_ll_set_clkout()
/hal_espressif-latest/components/hal/esp32/include/hal/
Ddac_ll.h64 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
67 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
127 …HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq… in dac_ll_cw_set_freq()
178 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset); in dac_ll_cw_set_dc_offset()
183 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset); in dac_ll_cw_set_dc_offset()
Dadc_ll.h108 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, rstb_wait, rst_wait); in adc_ll_digi_set_fsm_time()
110 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, start_wait, start_wait); in adc_ll_digi_set_fsm_time()
112 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, standby_wait, standby_wait); in adc_ll_digi_set_fsm_time()
123 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, sample_cycle, sample_cycle); in adc_ll_set_sample_cycle()
134 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
145 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl2, max_meas_num, meas_num); in adc_ll_digi_set_convert_limit_num()
343 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div); in adc_ll_set_sar_clk_div()
345 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div); in adc_ll_set_sar_clk_div()
653 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait1, 1); in adc_ll_amp_disable()
654 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1); in adc_ll_amp_disable()
[all …]
Dsdm_ll.h40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
Dtouch_sensor_ll.h59 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay, meas_time); in touch_ll_set_meas_time()
61 …HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT_MA… in touch_ll_set_meas_time()
85 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl2, touch_sleep_cycles, sleep_time); in touch_ll_set_sleep_time()
290 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], l_thresh, threshold); in touch_ll_set_threshold()
292 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], h_thresh, threshold); in touch_ll_set_threshold()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Ddac_ll.h76 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
79 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
148 …HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq… in dac_ll_cw_set_freq()
199 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset); in dac_ll_cw_set_dc_offset()
204 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset); in dac_ll_cw_set_dc_offset()
Dsdm_ll.h40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
Dtwai_ll.h462 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
505 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
535 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
555 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
556 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
727 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
731 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); in twai_ll_set_clkout()
734 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); in twai_ll_set_clkout()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dsdm_ll.h40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
Dtwai_ll.h462 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
505 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
535 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
555 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
556 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
727 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
731 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); in twai_ll_set_clkout()
734 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); in twai_ll_set_clkout()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dsdm_ll.h40 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); in sdm_ll_set_pulse_density()
53 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); in sdm_ll_set_prescale()
Dtwai_ll.h462 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
505 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
535 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
555 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
556 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
727 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
731 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); in twai_ll_set_clkout()
734 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); in twai_ll_set_clkout()
/hal_espressif-latest/components/hal/esp32h2/
Dpau_hal.c41 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.regdma_conf, regdma_rst_en, !enable); in pau_hal_regdma_clock_configure()
42 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.regdma_conf, regdma_clk_en, enable); in pau_hal_regdma_clock_configure()

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