1 /* 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 #include "soc.h" 9 10 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ 11 /* Output enable in sleep mode */ 12 #define SLP_OE (BIT(0)) 13 #define SLP_OE_M (BIT(0)) 14 #define SLP_OE_V 1 15 #define SLP_OE_S 0 16 /* Pin used for wakeup from sleep */ 17 #define SLP_SEL (BIT(1)) 18 #define SLP_SEL_M (BIT(1)) 19 #define SLP_SEL_V 1 20 #define SLP_SEL_S 1 21 /* Pulldown enable in sleep mode */ 22 #define SLP_PD (BIT(2)) 23 #define SLP_PD_M (BIT(2)) 24 #define SLP_PD_V 1 25 #define SLP_PD_S 2 26 /* Pullup enable in sleep mode */ 27 #define SLP_PU (BIT(3)) 28 #define SLP_PU_M (BIT(3)) 29 #define SLP_PU_V 1 30 #define SLP_PU_S 3 31 /* Input enable in sleep mode */ 32 #define SLP_IE (BIT(4)) 33 #define SLP_IE_M (BIT(4)) 34 #define SLP_IE_V 1 35 #define SLP_IE_S 4 36 /* Drive strength in sleep mode */ 37 #define SLP_DRV 0x3 38 #define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) 39 #define SLP_DRV_V 0x3 40 #define SLP_DRV_S 5 41 /* Pulldown enable */ 42 #define FUN_PD (BIT(7)) 43 #define FUN_PD_M (BIT(7)) 44 #define FUN_PD_V 1 45 #define FUN_PD_S 7 46 /* Pullup enable */ 47 #define FUN_PU (BIT(8)) 48 #define FUN_PU_M (BIT(8)) 49 #define FUN_PU_V 1 50 #define FUN_PU_S 8 51 /* Input enable */ 52 #define FUN_IE (BIT(9)) 53 #define FUN_IE_M (FUN_IE_V << FUN_IE_S) 54 #define FUN_IE_V 1 55 #define FUN_IE_S 9 56 /* Drive strength */ 57 #define FUN_DRV 0x3 58 #define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) 59 #define FUN_DRV_V 0x3 60 #define FUN_DRV_S 10 61 /* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ 62 #define MCU_SEL 0x7 63 #define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) 64 #define MCU_SEL_V 0x7 65 #define MCU_SEL_S 12 66 /* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ 67 #define FILTER_EN (BIT(15)) 68 #define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) 69 #define FILTER_EN_V 1 70 #define FILTER_EN_S 15 71 72 /* HYS_EN : R/W; bitpos: [16]; default: 0; 73 * Software enables hysteresis function for the pad. 74 * 1: Hysteresis enabled. 0: Hysteresis disabled. 75 */ 76 #define HYS_EN (BIT(16)) 77 #define HYS_EN_M (HYS_EN_V << HYS_EN_S) 78 #define HYS_EN_V 0x00000001 79 #define HYS_EN_S 16 80 /* HYS_SEL : R/W; bitpos: [17]; default: 0; 81 * Select enabling signals of the pad from software and efuse hardware. 82 * 1: Select enabling siganl from software. 83 * 0: Select enabling signal from efuse hardware. 84 */ 85 #define HYS_SEL (BIT(17)) 86 #define HYS_SEL_M (HYS_SEL_V << HYS_SEL_S) 87 #define HYS_SEL_V 0x00000001 88 #define HYS_SEL_S 17 89 90 #define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) 91 #define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) 92 #define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) 93 #define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) 94 #define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) 95 #define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) 96 #define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) 97 #define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) 98 #define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) 99 #define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) 100 101 #define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) 102 #define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) 103 #define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); 104 #define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) 105 #define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) 106 #define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) 107 #define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) 108 #define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) 109 #define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) 110 #define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) 111 #define PIN_HYS_EN_SEL_EFUSE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_SEL) 112 #define PIN_HYS_EN_SEL_SOFT(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_SEL) 113 #define PIN_HYS_SOFT_ENABLE(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_EN) 114 #define PIN_HYS_SOFT_DISABLE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_EN) 115 116 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U 117 #define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U 118 #define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_MTMS_U 119 #define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTDO_U 120 #define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTCK_U 121 #define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U 122 #define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U 123 #define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U 124 #define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U 125 #define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U 126 #define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U 127 #define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U 128 #define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U 129 #define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_XTAL_32K_P_U 130 #define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_XTAL_32K_N_U 131 #define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICS0_U 132 #define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIQ_U 133 #define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIWP_U 134 #define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SPIHD_U 135 #define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SPICLK_U 136 #define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SPID_U 137 #define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_VDD_SPI_U 138 #define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U 139 #define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U0RXD_U 140 #define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U0TXD_U 141 #define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U 142 #define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U 143 #define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U 144 145 #define PIN_FUNC_GPIO 1 146 147 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) 148 #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) 149 #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) 150 151 #define SPI_HD_GPIO_NUM 18 152 #define SPI_WP_GPIO_NUM 17 153 #define SPI_CS0_GPIO_NUM 15 154 #define SPI_CLK_GPIO_NUM 19 155 #define SPI_D_GPIO_NUM 20 156 #define SPI_Q_GPIO_NUM 16 157 158 #define USB_DM_GPIO_NUM 26 159 #define USB_DP_GPIO_NUM 27 160 161 #define EXT_OSC_SLOW_GPIO_NUM 13 162 163 #define MAX_RTC_GPIO_NUM 14 // GPIO7~14 are the pads with LP function 164 #define MAX_PAD_GPIO_NUM 27 165 #define MAX_GPIO_NUM 31 166 #define HIGH_IO_HOLD_BIT_SHIFT 32 167 168 169 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE 170 #define PIN_CTRL (REG_IO_MUX_BASE +0x00) 171 172 #define CLK_OUT3 IO_MUX_CLK_OUT3 173 #define CLK_OUT3_V IO_MUX_CLK_OUT3_V 174 #define CLK_OUT3_S IO_MUX_CLK_OUT3_S 175 #define CLK_OUT3_M IO_MUX_CLK_OUT3_M 176 #define CLK_OUT2 IO_MUX_CLK_OUT2 177 #define CLK_OUT2_V IO_MUX_CLK_OUT2_V 178 #define CLK_OUT2_S IO_MUX_CLK_OUT2_S 179 #define CLK_OUT2_M IO_MUX_CLK_OUT2_M 180 #define CLK_OUT1 IO_MUX_CLK_OUT1 181 #define CLK_OUT1_V IO_MUX_CLK_OUT1_V 182 #define CLK_OUT1_S IO_MUX_CLK_OUT1_S 183 #define CLK_OUT1_M IO_MUX_CLK_OUT1_M 184 // definitions above are inherited from previous version of code, should double check 185 186 // definitions below are generated from pin_txt.csv 187 #define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x4) 188 #define FUNC_GPIO0_FSPIQ 2 189 #define FUNC_GPIO0_GPIO0 1 190 #define FUNC_GPIO0_GPIO0_0 0 191 192 #define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE + 0x8) 193 #define FUNC_GPIO1_FSPICS0 2 194 #define FUNC_GPIO1_GPIO1 1 195 #define FUNC_GPIO1_GPIO1_0 0 196 197 #define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xC) 198 #define FUNC_MTMS_FSPIWP 2 199 #define FUNC_MTMS_GPIO2 1 200 #define FUNC_MTMS_MTMS 0 201 202 #define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x10) 203 #define FUNC_MTDO_FSPIHD 2 204 #define FUNC_MTDO_GPIO3 1 205 #define FUNC_MTDO_MTDO 0 206 207 #define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x14) 208 #define FUNC_MTCK_FSPICLK 2 209 #define FUNC_MTCK_GPIO4 1 210 #define FUNC_MTCK_MTCK 0 211 212 #define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18) 213 #define FUNC_MTDI_FSPID 2 214 #define FUNC_MTDI_GPIO5 1 215 #define FUNC_MTDI_MTDI 0 216 217 #define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE + 0x1C) 218 #define FUNC_GPIO6_GPIO6 1 219 #define FUNC_GPIO6_GPIO6_0 0 220 221 #define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x20) 222 #define FUNC_GPIO7_GPIO7 1 223 #define FUNC_GPIO7_GPIO7_0 0 224 225 #define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24) 226 #define FUNC_GPIO8_GPIO8 1 227 #define FUNC_GPIO8_GPIO8_0 0 228 229 #define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28) 230 #define FUNC_GPIO9_GPIO9 1 231 #define FUNC_GPIO9_GPIO9_0 0 232 233 #define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2C) 234 #define FUNC_GPIO10_GPIO10 1 235 #define FUNC_GPIO10_GPIO10_0 0 236 237 #define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE + 0x30) 238 #define FUNC_GPIO11_GPIO11 1 239 #define FUNC_GPIO11_GPIO11_0 0 240 241 #define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34) 242 #define FUNC_GPIO12_GPIO12 1 243 #define FUNC_GPIO12_GPIO12_0 0 244 245 #define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x38) 246 #define FUNC_XTAL_32K_P_GPIO13 1 247 #define FUNC_XTAL_32K_P_GPIO13_0 0 248 249 #define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x3C) 250 #define FUNC_XTAL_32K_N_GPIO14 1 251 #define FUNC_XTAL_32K_N_GPIO14_0 0 252 253 #define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x40) 254 #define FUNC_SPICS0_GPIO15 1 255 #define FUNC_SPICS0_SPICS0 0 256 257 #define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x44) 258 #define FUNC_SPIQ_GPIO16 1 259 #define FUNC_SPIQ_SPIQ 0 260 261 #define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x48) 262 #define FUNC_SPIWP_GPIO17 1 263 #define FUNC_SPIWP_SPIWP 0 264 265 #define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x4C) 266 #define FUNC_SPIHD_GPIO18 1 267 #define FUNC_SPIHD_SPIHD 0 268 269 #define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x50) 270 #define FUNC_SPICLK_GPIO19 1 271 #define FUNC_SPICLK_SPICLK 0 272 273 #define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x54) 274 #define FUNC_SPID_GPIO20 1 275 #define FUNC_SPID_SPID 0 276 277 #define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x58) 278 #define FUNC_VDD_SPI_GPIO21 1 279 #define FUNC_VDD_SPI_GPIO21_0 0 280 281 #define PERIPHS_IO_MUX_GPIO22_U (REG_IO_MUX_BASE + 0x5C) 282 #define FUNC_GPIO22_GPIO22 1 283 #define FUNC_GPIO22_GPIO22_0 0 284 285 #define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x60) 286 #define FUNC_U0RXD_FSPICS1 2 287 #define FUNC_U0RXD_GPIO23 1 288 #define FUNC_U0RXD_U0RXD 0 289 290 #define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x64) 291 #define FUNC_U0TXD_FSPICS2 2 292 #define FUNC_U0TXD_GPIO24 1 293 #define FUNC_U0TXD_U0TXD 0 294 295 #define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE + 0x68) 296 #define FUNC_GPIO25_FSPICS3 2 297 #define FUNC_GPIO25_GPIO25 1 298 #define FUNC_GPIO25_GPIO25_0 0 299 300 #define PERIPHS_IO_MUX_GPIO26_U (REG_IO_MUX_BASE + 0x6C) 301 #define FUNC_GPIO26_FSPICS4 2 302 #define FUNC_GPIO26_GPIO26 1 303 #define FUNC_GPIO26_GPIO26_0 0 304 305 #define PERIPHS_IO_MUX_GPIO27_U (REG_IO_MUX_BASE + 0x70) 306 #define FUNC_GPIO27_FSPICS5 2 307 #define FUNC_GPIO27_GPIO27 1 308 #define FUNC_GPIO27_GPIO27_0 0 309 310 /** IO_MUX_PIN_CTRL_REG register 311 * Clock Output Configuration 312 * Register 313 */ 314 #define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0) 315 /* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15; 316 * If you want to output clock for I2S to CLK_OUT_out1, set this register 317 * to 0x0. CLK_OUT_out1 can be found in peripheral output 318 * signals. 319 */ 320 #define IO_MUX_CLK_OUT1 0x0000001F 321 #define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S) 322 #define IO_MUX_CLK_OUT1_V 0x0000001F 323 #define IO_MUX_CLK_OUT1_S 0 324 /* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15; 325 * If you want to output clock for I2S to CLK_OUT_out2, set this register 326 * to 0x0. CLK_OUT_out2 can be found in peripheral output 327 * signals. 328 */ 329 #define IO_MUX_CLK_OUT2 0x0000001F 330 #define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S) 331 #define IO_MUX_CLK_OUT2_V 0x0000001F 332 #define IO_MUX_CLK_OUT2_S 5 333 /* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7; 334 * If you want to output clock for I2S to CLK_OUT_out3, set this register 335 * to 0x0. CLK_OUT_out3 can be found in peripheral output 336 * signals. 337 */ 338 #define IO_MUX_CLK_OUT3 0x0000001F 339 #define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S) 340 #define IO_MUX_CLK_OUT3_V 0x0000001F 341 #define IO_MUX_CLK_OUT3_S 10 342 343 /** IO_MUX_MODEM_DIAG_EN_REG register 344 * GPIO MATRIX Configure Register for modem 345 * diag 346 */ 347 #define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc) 348 /* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0; 349 * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] 350 * into gpio matrix. 0:enable other signals into gpio 351 * matrix 352 */ 353 #define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFF 354 #define IO_MUX_MODEM_DIAG_EN_M (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S) 355 #define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFF 356 #define IO_MUX_MODEM_DIAG_EN_S 0 357 358 /** IO_MUX_DATE_REG register 359 * IO MUX Version Control 360 * Register 361 */ 362 #define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) 363 /* IO_MUX_REG_DATE : R/W; bitpos: [28:0]; default: 35680880; 364 * Version control 365 * register 366 */ 367 #define IO_MUX_REG_DATE 0x0FFFFFFF 368 #define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S) 369 #define IO_MUX_REG_DATE_V 0x0FFFFFFF 370 #define IO_MUX_REG_DATE_S 0 371
