1 /** 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** EXTMEM_ICACHE_CTRL_REG register 15 * This description will be updated in the near future. 16 */ 17 #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) 18 /** EXTMEM_ICACHE_ENABLE : R/W; bitpos: [0]; default: 0; 19 * The bit is used to activate the data cache. 0: disable, 1: enable 20 */ 21 #define EXTMEM_ICACHE_ENABLE (BIT(0)) 22 #define EXTMEM_ICACHE_ENABLE_M (EXTMEM_ICACHE_ENABLE_V << EXTMEM_ICACHE_ENABLE_S) 23 #define EXTMEM_ICACHE_ENABLE_V 0x00000001U 24 #define EXTMEM_ICACHE_ENABLE_S 0 25 26 /** EXTMEM_ICACHE_CTRL1_REG register 27 * This description will be updated in the near future. 28 */ 29 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) 30 /** EXTMEM_ICACHE_SHUT_IBUS : R/W; bitpos: [0]; default: 1; 31 * The bit is used to disable core0 ibus, 0: enable, 1: disable 32 */ 33 #define EXTMEM_ICACHE_SHUT_IBUS (BIT(0)) 34 #define EXTMEM_ICACHE_SHUT_IBUS_M (EXTMEM_ICACHE_SHUT_IBUS_V << EXTMEM_ICACHE_SHUT_IBUS_S) 35 #define EXTMEM_ICACHE_SHUT_IBUS_V 0x00000001U 36 #define EXTMEM_ICACHE_SHUT_IBUS_S 0 37 /** EXTMEM_ICACHE_SHUT_DBUS : R/W; bitpos: [1]; default: 1; 38 * The bit is used to disable core1 ibus, 0: enable, 1: disable 39 */ 40 #define EXTMEM_ICACHE_SHUT_DBUS (BIT(1)) 41 #define EXTMEM_ICACHE_SHUT_DBUS_M (EXTMEM_ICACHE_SHUT_DBUS_V << EXTMEM_ICACHE_SHUT_DBUS_S) 42 #define EXTMEM_ICACHE_SHUT_DBUS_V 0x00000001U 43 #define EXTMEM_ICACHE_SHUT_DBUS_S 1 44 45 /** EXTMEM_ICACHE_TAG_POWER_CTRL_REG register 46 * This description will be updated in the near future. 47 */ 48 #define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) 49 /** EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; 50 * The bit is used to close clock gating of icache tag memory. 1: close gating, 0: 51 * open clock gating. 52 */ 53 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) 54 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V << EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S) 55 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x00000001U 56 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 57 /** EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; 58 * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down 59 */ 60 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) 61 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S) 62 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x00000001U 63 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 64 /** EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; 65 * The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up 66 */ 67 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) 68 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S) 69 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x00000001U 70 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 71 72 /** EXTMEM_ICACHE_SYNC_CTRL_REG register 73 * This description will be updated in the near future. 74 */ 75 #define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) 76 /** EXTMEM_ICACHE_INVALIDATE_ENA : R/W/SS; bitpos: [0]; default: 1; 77 * The bit is used to enable invalidate operation. It will be cleared by hardware 78 * after invalidate operation done. 79 */ 80 #define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) 81 #define EXTMEM_ICACHE_INVALIDATE_ENA_M (EXTMEM_ICACHE_INVALIDATE_ENA_V << EXTMEM_ICACHE_INVALIDATE_ENA_S) 82 #define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x00000001U 83 #define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 84 /** EXTMEM_ICACHE_SYNC_DONE : RO; bitpos: [1]; default: 0; 85 * The bit is used to indicate invalidate operation is finished. 86 */ 87 #define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) 88 #define EXTMEM_ICACHE_SYNC_DONE_M (EXTMEM_ICACHE_SYNC_DONE_V << EXTMEM_ICACHE_SYNC_DONE_S) 89 #define EXTMEM_ICACHE_SYNC_DONE_V 0x00000001U 90 #define EXTMEM_ICACHE_SYNC_DONE_S 1 91 92 /** EXTMEM_ICACHE_SYNC_ADDR_REG register 93 * This description will be updated in the near future. 94 */ 95 #define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2c) 96 /** EXTMEM_ICACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; 97 * The bits are used to configure the start virtual address for clean operations. It 98 * should be combined with ICACHE_SYNC_SIZE_REG. 99 */ 100 #define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFFU 101 #define EXTMEM_ICACHE_SYNC_ADDR_M (EXTMEM_ICACHE_SYNC_ADDR_V << EXTMEM_ICACHE_SYNC_ADDR_S) 102 #define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFFU 103 #define EXTMEM_ICACHE_SYNC_ADDR_S 0 104 105 /** EXTMEM_ICACHE_SYNC_SIZE_REG register 106 * This description will be updated in the near future. 107 */ 108 #define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30) 109 /** EXTMEM_ICACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0; 110 * The bits are used to configure the length for sync operations. The bits are the 111 * counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. 112 */ 113 #define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFFU 114 #define EXTMEM_ICACHE_SYNC_SIZE_M (EXTMEM_ICACHE_SYNC_SIZE_V << EXTMEM_ICACHE_SYNC_SIZE_S) 115 #define EXTMEM_ICACHE_SYNC_SIZE_V 0x007FFFFFU 116 #define EXTMEM_ICACHE_SYNC_SIZE_S 0 117 118 /** EXTMEM_IBUS_TO_FLASH_START_VADDR_REG register 119 * This description will be updated in the near future. 120 */ 121 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x54) 122 /** EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: 1107296256; 123 * The bits are used to configure the start virtual address of ibus to access flash. 124 * The register is used to give constraints to ibus access counter. 125 */ 126 #define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFFU 127 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_M (EXTMEM_IBUS_TO_FLASH_START_VADDR_V << EXTMEM_IBUS_TO_FLASH_START_VADDR_S) 128 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFFU 129 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 130 131 /** EXTMEM_IBUS_TO_FLASH_END_VADDR_REG register 132 * This description will be updated in the near future. 133 */ 134 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x58) 135 /** EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 1111490559; 136 * The bits are used to configure the end virtual address of ibus to access flash. The 137 * register is used to give constraints to ibus access counter. 138 */ 139 #define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFFU 140 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_M (EXTMEM_IBUS_TO_FLASH_END_VADDR_V << EXTMEM_IBUS_TO_FLASH_END_VADDR_S) 141 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFFU 142 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 143 144 /** EXTMEM_DBUS_TO_FLASH_START_VADDR_REG register 145 * This description will be updated in the near future. 146 */ 147 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x5c) 148 /** EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: 1006632960; 149 * The bits are used to configure the start virtual address of dbus to access flash. 150 * The register is used to give constraints to dbus access counter. 151 */ 152 #define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFFU 153 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_M (EXTMEM_DBUS_TO_FLASH_START_VADDR_V << EXTMEM_DBUS_TO_FLASH_START_VADDR_S) 154 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFFU 155 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 156 157 /** EXTMEM_DBUS_TO_FLASH_END_VADDR_REG register 158 * This description will be updated in the near future. 159 */ 160 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x60) 161 /** EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 1010827263; 162 * The bits are used to configure the end virtual address of dbus to access flash. The 163 * register is used to give constraints to dbus access counter. 164 */ 165 #define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFFU 166 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_M (EXTMEM_DBUS_TO_FLASH_END_VADDR_V << EXTMEM_DBUS_TO_FLASH_END_VADDR_S) 167 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFFU 168 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 169 170 /** EXTMEM_CACHE_ACS_CNT_CLR_REG register 171 * This description will be updated in the near future. 172 */ 173 #define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x64) 174 /** EXTMEM_IBUS_ACS_CNT_CLR : WOD; bitpos: [0]; default: 0; 175 * The bit is used to clear ibus counter. 176 */ 177 #define EXTMEM_IBUS_ACS_CNT_CLR (BIT(0)) 178 #define EXTMEM_IBUS_ACS_CNT_CLR_M (EXTMEM_IBUS_ACS_CNT_CLR_V << EXTMEM_IBUS_ACS_CNT_CLR_S) 179 #define EXTMEM_IBUS_ACS_CNT_CLR_V 0x00000001U 180 #define EXTMEM_IBUS_ACS_CNT_CLR_S 0 181 /** EXTMEM_DBUS_ACS_CNT_CLR : WOD; bitpos: [1]; default: 0; 182 * The bit is used to clear dbus counter. 183 */ 184 #define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1)) 185 #define EXTMEM_DBUS_ACS_CNT_CLR_M (EXTMEM_DBUS_ACS_CNT_CLR_V << EXTMEM_DBUS_ACS_CNT_CLR_S) 186 #define EXTMEM_DBUS_ACS_CNT_CLR_V 0x00000001U 187 #define EXTMEM_DBUS_ACS_CNT_CLR_S 1 188 189 /** EXTMEM_CACHE_ILG_INT_ENA_REG register 190 * This description will be updated in the near future. 191 */ 192 #define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x78) 193 /** EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [0]; default: 0; 194 * The bit is used to enable interrupt by sync configurations fault. 195 */ 196 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) 197 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S) 198 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001U 199 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 200 /** EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [1]; default: 0; 201 * The bit is used to enable interrupt by preload configurations fault. 202 */ 203 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) 204 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S) 205 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001U 206 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 207 /** EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W; bitpos: [5]; default: 0; 208 * The bit is used to enable interrupt by mmu entry fault. 209 */ 210 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) 211 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V << EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S) 212 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x00000001U 213 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 214 /** EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W; bitpos: [7]; default: 0; 215 * The bit is used to enable interrupt by ibus counter overflow. 216 */ 217 #define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) 218 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (EXTMEM_IBUS_CNT_OVF_INT_ENA_V << EXTMEM_IBUS_CNT_OVF_INT_ENA_S) 219 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x00000001U 220 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 221 /** EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W; bitpos: [8]; default: 0; 222 * The bit is used to enable interrupt by dbus counter overflow. 223 */ 224 #define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) 225 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (EXTMEM_DBUS_CNT_OVF_INT_ENA_V << EXTMEM_DBUS_CNT_OVF_INT_ENA_S) 226 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x00000001U 227 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 228 229 /** EXTMEM_CACHE_ILG_INT_CLR_REG register 230 * This description will be updated in the near future. 231 */ 232 #define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x7c) 233 /** EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [0]; default: 0; 234 * The bit is used to clear interrupt by sync configurations fault. 235 */ 236 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) 237 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S) 238 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001U 239 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 240 /** EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [1]; default: 0; 241 * The bit is used to clear interrupt by preload configurations fault. 242 */ 243 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) 244 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S) 245 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001U 246 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 247 /** EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD; bitpos: [5]; default: 0; 248 * The bit is used to clear interrupt by mmu entry fault. 249 */ 250 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) 251 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V << EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S) 252 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x00000001U 253 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 254 /** EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD; bitpos: [7]; default: 0; 255 * The bit is used to clear interrupt by ibus counter overflow. 256 */ 257 #define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) 258 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (EXTMEM_IBUS_CNT_OVF_INT_CLR_V << EXTMEM_IBUS_CNT_OVF_INT_CLR_S) 259 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x00000001U 260 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 261 /** EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD; bitpos: [8]; default: 0; 262 * The bit is used to clear interrupt by dbus counter overflow. 263 */ 264 #define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) 265 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (EXTMEM_DBUS_CNT_OVF_INT_CLR_V << EXTMEM_DBUS_CNT_OVF_INT_CLR_S) 266 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x00000001U 267 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 268 269 /** EXTMEM_CACHE_ILG_INT_ST_REG register 270 * This description will be updated in the near future. 271 */ 272 #define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x80) 273 /** EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO; bitpos: [0]; default: 0; 274 * The bit is used to indicate interrupt by sync configurations fault. 275 */ 276 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) 277 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V << EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S) 278 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x00000001U 279 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 280 /** EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO; bitpos: [1]; default: 0; 281 * The bit is used to indicate interrupt by preload configurations fault. 282 */ 283 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) 284 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S) 285 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x00000001U 286 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 287 /** EXTMEM_MMU_ENTRY_FAULT_ST : RO; bitpos: [5]; default: 0; 288 * The bit is used to indicate interrupt by mmu entry fault. 289 */ 290 #define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) 291 #define EXTMEM_MMU_ENTRY_FAULT_ST_M (EXTMEM_MMU_ENTRY_FAULT_ST_V << EXTMEM_MMU_ENTRY_FAULT_ST_S) 292 #define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x00000001U 293 #define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 294 /** EXTMEM_IBUS_ACS_CNT_OVF_ST : RO; bitpos: [7]; default: 0; 295 * The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. 296 */ 297 #define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) 298 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_CNT_OVF_ST_S) 299 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x00000001U 300 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 301 /** EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0; 302 * The bit is used to indicate interrupt by ibus access flash/spiram miss counter 303 * overflow. 304 */ 305 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) 306 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S) 307 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x00000001U 308 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 309 /** EXTMEM_DBUS_ACS_CNT_OVF_ST : RO; bitpos: [9]; default: 0; 310 * The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. 311 */ 312 #define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) 313 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_CNT_OVF_ST_S) 314 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x00000001U 315 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 316 /** EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0; 317 * The bit is used to indicate interrupt by dbus access flash miss counter overflow. 318 */ 319 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) 320 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S) 321 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x00000001U 322 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 323 324 /** EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG register 325 * This description will be updated in the near future. 326 */ 327 #define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x84) 328 /** EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [0]; default: 0; 329 * The bit is used to enable interrupt by cpu access icache while the corresponding 330 * ibus is disabled which include speculative access. 331 */ 332 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) 333 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S) 334 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001U 335 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 336 /** EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W; bitpos: [1]; default: 0; 337 * The bit is used to enable interrupt by ibus trying to write icache 338 */ 339 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) 340 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S) 341 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x00000001U 342 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 343 /** EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W; bitpos: [2]; default: 0; 344 * The bit is used to enable interrupt by authentication fail. 345 */ 346 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) 347 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S) 348 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x00000001U 349 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 350 /** EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [3]; default: 0; 351 * The bit is used to enable interrupt by cpu access icache while the corresponding 352 * dbus is disabled which include speculative access. 353 */ 354 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3)) 355 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S) 356 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x00000001U 357 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3 358 /** EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W; bitpos: [4]; default: 0; 359 * The bit is used to enable interrupt by authentication fail. 360 */ 361 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) 362 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S) 363 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x00000001U 364 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 365 /** EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W; bitpos: [5]; default: 0; 366 * The bit is used to enable interrupt by dbus trying to write icache 367 */ 368 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5)) 369 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V << EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S) 370 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x00000001U 371 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5 372 373 /** EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG register 374 * This description will be updated in the near future. 375 */ 376 #define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x88) 377 /** EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0; 378 * The bit is used to clear interrupt by cpu access icache while the corresponding 379 * ibus is disabled or icache is disabled which include speculative access. 380 */ 381 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) 382 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S) 383 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001U 384 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 385 /** EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD; bitpos: [1]; default: 0; 386 * The bit is used to clear interrupt by ibus trying to write icache 387 */ 388 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) 389 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S) 390 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x00000001U 391 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 392 /** EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD; bitpos: [2]; default: 0; 393 * The bit is used to clear interrupt by authentication fail. 394 */ 395 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) 396 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S) 397 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x00000001U 398 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 399 /** EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [3]; default: 0; 400 * The bit is used to clear interrupt by cpu access icache while the corresponding 401 * dbus is disabled or icache is disabled which include speculative access. 402 */ 403 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3)) 404 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S) 405 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x00000001U 406 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3 407 /** EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0; 408 * The bit is used to clear interrupt by authentication fail. 409 */ 410 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) 411 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S) 412 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x00000001U 413 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 414 /** EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD; bitpos: [5]; default: 0; 415 * The bit is used to clear interrupt by dbus trying to write icache 416 */ 417 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5)) 418 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V << EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S) 419 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x00000001U 420 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5 421 422 /** EXTMEM_CORE0_ACS_CACHE_INT_ST_REG register 423 * This description will be updated in the near future. 424 */ 425 #define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x8c) 426 /** EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0; 427 * The bit is used to indicate interrupt by cpu access icache while the core0_ibus is 428 * disabled or icache is disabled which include speculative access. 429 */ 430 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) 431 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S) 432 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x00000001U 433 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 434 /** EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO; bitpos: [1]; default: 0; 435 * The bit is used to indicate interrupt by ibus trying to write icache 436 */ 437 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) 438 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V << EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S) 439 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x00000001U 440 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 441 /** EXTMEM_CORE0_IBUS_REJECT_ST : RO; bitpos: [2]; default: 0; 442 * The bit is used to indicate interrupt by authentication fail. 443 */ 444 #define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) 445 #define EXTMEM_CORE0_IBUS_REJECT_ST_M (EXTMEM_CORE0_IBUS_REJECT_ST_V << EXTMEM_CORE0_IBUS_REJECT_ST_S) 446 #define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x00000001U 447 #define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 448 /** EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [3]; default: 0; 449 * The bit is used to indicate interrupt by cpu access icache while the core0_dbus is 450 * disabled or icache is disabled which include speculative access. 451 */ 452 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3)) 453 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S) 454 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x00000001U 455 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3 456 /** EXTMEM_CORE0_DBUS_REJECT_ST : RO; bitpos: [4]; default: 0; 457 * The bit is used to indicate interrupt by authentication fail. 458 */ 459 #define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) 460 #define EXTMEM_CORE0_DBUS_REJECT_ST_M (EXTMEM_CORE0_DBUS_REJECT_ST_V << EXTMEM_CORE0_DBUS_REJECT_ST_S) 461 #define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x00000001U 462 #define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 463 /** EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO; bitpos: [5]; default: 0; 464 * The bit is used to indicate interrupt by dbus trying to write icache 465 */ 466 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5)) 467 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V << EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S) 468 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x00000001U 469 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5 470 471 /** EXTMEM_CORE0_DBUS_REJECT_ST_REG register 472 * This description will be updated in the near future. 473 */ 474 #define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x90) 475 /** EXTMEM_CORE0_DBUS_ATTR : RO; bitpos: [2:0]; default: 0; 476 * The bits are used to indicate the attribute of CPU access dbus when authentication 477 * fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. 478 */ 479 #define EXTMEM_CORE0_DBUS_ATTR 0x00000007U 480 #define EXTMEM_CORE0_DBUS_ATTR_M (EXTMEM_CORE0_DBUS_ATTR_V << EXTMEM_CORE0_DBUS_ATTR_S) 481 #define EXTMEM_CORE0_DBUS_ATTR_V 0x00000007U 482 #define EXTMEM_CORE0_DBUS_ATTR_S 0 483 /** EXTMEM_CORE0_DBUS_WORLD : RO; bitpos: [3]; default: 0; 484 * The bit is used to indicate the world of CPU access dbus when authentication fail. 485 * 0: WORLD0, 1: WORLD1 486 */ 487 #define EXTMEM_CORE0_DBUS_WORLD (BIT(3)) 488 #define EXTMEM_CORE0_DBUS_WORLD_M (EXTMEM_CORE0_DBUS_WORLD_V << EXTMEM_CORE0_DBUS_WORLD_S) 489 #define EXTMEM_CORE0_DBUS_WORLD_V 0x00000001U 490 #define EXTMEM_CORE0_DBUS_WORLD_S 3 491 492 /** EXTMEM_CORE0_DBUS_REJECT_VADDR_REG register 493 * This description will be updated in the near future. 494 */ 495 #define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x94) 496 /** EXTMEM_CORE0_DBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; 497 * The bits are used to indicate the virtual address of CPU access dbus when 498 * authentication fail. 499 */ 500 #define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFFU 501 #define EXTMEM_CORE0_DBUS_VADDR_M (EXTMEM_CORE0_DBUS_VADDR_V << EXTMEM_CORE0_DBUS_VADDR_S) 502 #define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFFU 503 #define EXTMEM_CORE0_DBUS_VADDR_S 0 504 505 /** EXTMEM_CORE0_IBUS_REJECT_ST_REG register 506 * This description will be updated in the near future. 507 */ 508 #define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x98) 509 /** EXTMEM_CORE0_IBUS_ATTR : RO; bitpos: [2:0]; default: 0; 510 * The bits are used to indicate the attribute of CPU access ibus when authentication 511 * fail. 0: invalidate, 1: execute-able, 2: read-able 512 */ 513 #define EXTMEM_CORE0_IBUS_ATTR 0x00000007U 514 #define EXTMEM_CORE0_IBUS_ATTR_M (EXTMEM_CORE0_IBUS_ATTR_V << EXTMEM_CORE0_IBUS_ATTR_S) 515 #define EXTMEM_CORE0_IBUS_ATTR_V 0x00000007U 516 #define EXTMEM_CORE0_IBUS_ATTR_S 0 517 /** EXTMEM_CORE0_IBUS_WORLD : RO; bitpos: [3]; default: 0; 518 * The bit is used to indicate the world of CPU access ibus when authentication fail. 519 * 0: WORLD0, 1: WORLD1 520 */ 521 #define EXTMEM_CORE0_IBUS_WORLD (BIT(3)) 522 #define EXTMEM_CORE0_IBUS_WORLD_M (EXTMEM_CORE0_IBUS_WORLD_V << EXTMEM_CORE0_IBUS_WORLD_S) 523 #define EXTMEM_CORE0_IBUS_WORLD_V 0x00000001U 524 #define EXTMEM_CORE0_IBUS_WORLD_S 3 525 526 /** EXTMEM_CORE0_IBUS_REJECT_VADDR_REG register 527 * This description will be updated in the near future. 528 */ 529 #define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x9c) 530 /** EXTMEM_CORE0_IBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; 531 * The bits are used to indicate the virtual address of CPU access ibus when 532 * authentication fail. 533 */ 534 #define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFFU 535 #define EXTMEM_CORE0_IBUS_VADDR_M (EXTMEM_CORE0_IBUS_VADDR_V << EXTMEM_CORE0_IBUS_VADDR_S) 536 #define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFFU 537 #define EXTMEM_CORE0_IBUS_VADDR_S 0 538 539 /** EXTMEM_CACHE_MMU_FAULT_CONTENT_REG register 540 * This description will be updated in the near future. 541 */ 542 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0xa0) 543 /** EXTMEM_CACHE_MMU_FAULT_CONTENT : RO; bitpos: [7:0]; default: 0; 544 * The bits are used to indicate the content of mmu entry which cause mmu fault.. 545 */ 546 #define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000000FFU 547 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_M (EXTMEM_CACHE_MMU_FAULT_CONTENT_V << EXTMEM_CACHE_MMU_FAULT_CONTENT_S) 548 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x000000FFU 549 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 550 /** EXTMEM_CACHE_MMU_FAULT_CODE : RO; bitpos: [13:10]; default: 0; 551 * The right-most 3 bits are used to indicate the operations which cause mmu fault 552 * occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss 553 * evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: 554 * external dma rx. The most significant bit is used to indicate this operation occurs 555 * in which one icache. 556 */ 557 #define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000FU 558 #define EXTMEM_CACHE_MMU_FAULT_CODE_M (EXTMEM_CACHE_MMU_FAULT_CODE_V << EXTMEM_CACHE_MMU_FAULT_CODE_S) 559 #define EXTMEM_CACHE_MMU_FAULT_CODE_V 0x0000000FU 560 #define EXTMEM_CACHE_MMU_FAULT_CODE_S 10 561 562 /** EXTMEM_CACHE_MMU_FAULT_VADDR_REG register 563 * This description will be updated in the near future. 564 */ 565 #define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0xa4) 566 /** EXTMEM_CACHE_MMU_FAULT_VADDR : RO; bitpos: [31:0]; default: 0; 567 * The bits are used to indicate the virtual address which cause mmu fault.. 568 */ 569 #define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFFU 570 #define EXTMEM_CACHE_MMU_FAULT_VADDR_M (EXTMEM_CACHE_MMU_FAULT_VADDR_V << EXTMEM_CACHE_MMU_FAULT_VADDR_S) 571 #define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFFU 572 #define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 573 574 /** EXTMEM_CACHE_WRAP_AROUND_CTRL_REG register 575 * This description will be updated in the near future. 576 */ 577 #define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0xa8) 578 /** EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W; bitpos: [0]; default: 0; 579 * The bit is used to enable wrap around mode when read data from flash. 580 */ 581 #define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) 582 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (EXTMEM_CACHE_FLASH_WRAP_AROUND_V << EXTMEM_CACHE_FLASH_WRAP_AROUND_S) 583 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x00000001U 584 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 585 586 /** EXTMEM_CACHE_MMU_POWER_CTRL_REG register 587 * This description will be updated in the near future. 588 */ 589 #define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0xac) 590 /** EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; 591 * The bit is used to enable clock gating to save power when access mmu memory, 0: 592 * enable, 1: disable 593 */ 594 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) 595 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (EXTMEM_CACHE_MMU_MEM_FORCE_ON_V << EXTMEM_CACHE_MMU_MEM_FORCE_ON_S) 596 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x00000001U 597 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 598 /** EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; 599 * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down 600 */ 601 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) 602 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (EXTMEM_CACHE_MMU_MEM_FORCE_PD_V << EXTMEM_CACHE_MMU_MEM_FORCE_PD_S) 603 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x00000001U 604 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 605 /** EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; 606 * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up 607 */ 608 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) 609 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (EXTMEM_CACHE_MMU_MEM_FORCE_PU_V << EXTMEM_CACHE_MMU_MEM_FORCE_PU_S) 610 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x00000001U 611 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 612 613 /** EXTMEM_CACHE_STATE_REG register 614 * This description will be updated in the near future. 615 */ 616 #define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0xb0) 617 /** EXTMEM_ICACHE_STATE : RO; bitpos: [11:0]; default: 1; 618 * The bit is used to indicate whether icache main fsm is in idle state or not. 1: in 619 * idle state, 0: not in idle state 620 */ 621 #define EXTMEM_ICACHE_STATE 0x00000FFFU 622 #define EXTMEM_ICACHE_STATE_M (EXTMEM_ICACHE_STATE_V << EXTMEM_ICACHE_STATE_S) 623 #define EXTMEM_ICACHE_STATE_V 0x00000FFFU 624 #define EXTMEM_ICACHE_STATE_S 0 625 626 /** EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG register 627 * This description will be updated in the near future. 628 */ 629 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0xb4) 630 /** EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W; bitpos: [0]; default: 0; 631 * Reserved. 632 */ 633 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) 634 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V << EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S) 635 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x00000001U 636 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 637 /** EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W; bitpos: [1]; default: 0; 638 * Reserved. 639 */ 640 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) 641 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V << EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S) 642 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x00000001U 643 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 644 645 /** EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG register 646 * This description will be updated in the near future. 647 */ 648 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0xb8) 649 /** EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W; bitpos: [0]; default: 1; 650 * The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: 651 * open clock gating. 652 */ 653 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) 654 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V << EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S) 655 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x00000001U 656 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 657 /** EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W; bitpos: [1]; default: 1; 658 * The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: 659 * open clock gating. 660 */ 661 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) 662 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V << EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S) 663 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x00000001U 664 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 665 /** EXTMEM_CLK_FORCE_ON_CRYPT : R/W; bitpos: [2]; default: 1; 666 * The bit is used to close clock gating of external memory encrypt and decrypt clock. 667 * 1: close gating, 0: open clock gating. 668 */ 669 #define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) 670 #define EXTMEM_CLK_FORCE_ON_CRYPT_M (EXTMEM_CLK_FORCE_ON_CRYPT_V << EXTMEM_CLK_FORCE_ON_CRYPT_S) 671 #define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x00000001U 672 #define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 673 674 /** EXTMEM_CACHE_PRELOAD_INT_CTRL_REG register 675 * This description will be updated in the near future. 676 */ 677 #define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xbc) 678 /** EXTMEM_ICACHE_PRELOAD_INT_ST : RO; bitpos: [0]; default: 0; 679 * The bit is used to indicate the interrupt by icache pre-load done. 680 */ 681 #define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) 682 #define EXTMEM_ICACHE_PRELOAD_INT_ST_M (EXTMEM_ICACHE_PRELOAD_INT_ST_V << EXTMEM_ICACHE_PRELOAD_INT_ST_S) 683 #define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x00000001U 684 #define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 685 /** EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W; bitpos: [1]; default: 0; 686 * The bit is used to enable the interrupt by icache pre-load done. 687 */ 688 #define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) 689 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_INT_ENA_S) 690 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x00000001U 691 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 692 /** EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD; bitpos: [2]; default: 0; 693 * The bit is used to clear the interrupt by icache pre-load done. 694 */ 695 #define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) 696 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_INT_CLR_S) 697 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x00000001U 698 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 699 700 /** EXTMEM_CACHE_SYNC_INT_CTRL_REG register 701 * This description will be updated in the near future. 702 */ 703 #define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xc0) 704 /** EXTMEM_ICACHE_SYNC_INT_ST : RO; bitpos: [0]; default: 0; 705 * The bit is used to indicate the interrupt by icache sync done. 706 */ 707 #define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) 708 #define EXTMEM_ICACHE_SYNC_INT_ST_M (EXTMEM_ICACHE_SYNC_INT_ST_V << EXTMEM_ICACHE_SYNC_INT_ST_S) 709 #define EXTMEM_ICACHE_SYNC_INT_ST_V 0x00000001U 710 #define EXTMEM_ICACHE_SYNC_INT_ST_S 0 711 /** EXTMEM_ICACHE_SYNC_INT_ENA : R/W; bitpos: [1]; default: 0; 712 * The bit is used to enable the interrupt by icache sync done. 713 */ 714 #define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) 715 #define EXTMEM_ICACHE_SYNC_INT_ENA_M (EXTMEM_ICACHE_SYNC_INT_ENA_V << EXTMEM_ICACHE_SYNC_INT_ENA_S) 716 #define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x00000001U 717 #define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 718 /** EXTMEM_ICACHE_SYNC_INT_CLR : WOD; bitpos: [2]; default: 0; 719 * The bit is used to clear the interrupt by icache sync done. 720 */ 721 #define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) 722 #define EXTMEM_ICACHE_SYNC_INT_CLR_M (EXTMEM_ICACHE_SYNC_INT_CLR_V << EXTMEM_ICACHE_SYNC_INT_CLR_S) 723 #define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x00000001U 724 #define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 725 726 /** EXTMEM_CACHE_MMU_OWNER_REG register 727 * This description will be updated in the near future. 728 */ 729 #define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0xc4) 730 /** EXTMEM_CACHE_MMU_OWNER : R/W; bitpos: [3:0]; default: 0; 731 * The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus 732 */ 733 #define EXTMEM_CACHE_MMU_OWNER 0x0000000FU 734 #define EXTMEM_CACHE_MMU_OWNER_M (EXTMEM_CACHE_MMU_OWNER_V << EXTMEM_CACHE_MMU_OWNER_S) 735 #define EXTMEM_CACHE_MMU_OWNER_V 0x0000000FU 736 #define EXTMEM_CACHE_MMU_OWNER_S 0 737 738 /** EXTMEM_CACHE_CONF_MISC_REG register 739 * This description will be updated in the near future. 740 */ 741 #define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0xc8) 742 /** EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W; bitpos: [0]; default: 1; 743 * The bit is used to disable checking mmu entry fault by preload operation. 744 */ 745 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) 746 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S) 747 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x00000001U 748 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 749 /** EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W; bitpos: [1]; default: 1; 750 * The bit is used to disable checking mmu entry fault by sync operation. 751 */ 752 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) 753 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S) 754 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x00000001U 755 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 756 /** EXTMEM_CACHE_TRACE_ENA : R/W; bitpos: [2]; default: 1; 757 * The bit is used to enable cache trace function. 758 */ 759 #define EXTMEM_CACHE_TRACE_ENA (BIT(2)) 760 #define EXTMEM_CACHE_TRACE_ENA_M (EXTMEM_CACHE_TRACE_ENA_V << EXTMEM_CACHE_TRACE_ENA_S) 761 #define EXTMEM_CACHE_TRACE_ENA_V 0x00000001U 762 #define EXTMEM_CACHE_TRACE_ENA_S 2 763 /** EXTMEM_CACHE_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; 764 * This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB 765 */ 766 #define EXTMEM_CACHE_MMU_PAGE_SIZE 0x00000003U 767 #define EXTMEM_CACHE_MMU_PAGE_SIZE_M (EXTMEM_CACHE_MMU_PAGE_SIZE_V << EXTMEM_CACHE_MMU_PAGE_SIZE_S) 768 #define EXTMEM_CACHE_MMU_PAGE_SIZE_V 0x00000003U 769 #define EXTMEM_CACHE_MMU_PAGE_SIZE_S 3 770 771 /** EXTMEM_ICACHE_FREEZE_REG register 772 * This description will be updated in the near future. 773 */ 774 #define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0xcc) 775 /** EXTMEM_ICACHE_FREEZE_ENA : R/W; bitpos: [0]; default: 0; 776 * The bit is used to enable icache freeze mode 777 */ 778 #define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) 779 #define EXTMEM_ICACHE_FREEZE_ENA_M (EXTMEM_ICACHE_FREEZE_ENA_V << EXTMEM_ICACHE_FREEZE_ENA_S) 780 #define EXTMEM_ICACHE_FREEZE_ENA_V 0x00000001U 781 #define EXTMEM_ICACHE_FREEZE_ENA_S 0 782 /** EXTMEM_ICACHE_FREEZE_MODE : R/W; bitpos: [1]; default: 0; 783 * The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit 784 * if CPU miss 785 */ 786 #define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) 787 #define EXTMEM_ICACHE_FREEZE_MODE_M (EXTMEM_ICACHE_FREEZE_MODE_V << EXTMEM_ICACHE_FREEZE_MODE_S) 788 #define EXTMEM_ICACHE_FREEZE_MODE_V 0x00000001U 789 #define EXTMEM_ICACHE_FREEZE_MODE_S 1 790 /** EXTMEM_ICACHE_FREEZE_DONE : RO; bitpos: [2]; default: 0; 791 * The bit is used to indicate icache freeze success 792 */ 793 #define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) 794 #define EXTMEM_ICACHE_FREEZE_DONE_M (EXTMEM_ICACHE_FREEZE_DONE_V << EXTMEM_ICACHE_FREEZE_DONE_S) 795 #define EXTMEM_ICACHE_FREEZE_DONE_V 0x00000001U 796 #define EXTMEM_ICACHE_FREEZE_DONE_S 2 797 798 /** EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG register 799 * This description will be updated in the near future. 800 */ 801 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0xd0) 802 /** EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W; bitpos: [0]; default: 1; 803 * The bit is used to activate icache atomic operation protection. In this case, 804 * sync/lock operation can not interrupt miss-work. This feature does not work during 805 * invalidateAll operation. 806 */ 807 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) 808 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V << EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S) 809 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x00000001U 810 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 811 812 /** EXTMEM_CACHE_REQUEST_REG register 813 * This description will be updated in the near future. 814 */ 815 #define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0xd4) 816 /** EXTMEM_CACHE_REQUEST_BYPASS : R/W; bitpos: [0]; default: 0; 817 * The bit is used to disable request recording which could cause performance issue 818 */ 819 #define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) 820 #define EXTMEM_CACHE_REQUEST_BYPASS_M (EXTMEM_CACHE_REQUEST_BYPASS_V << EXTMEM_CACHE_REQUEST_BYPASS_S) 821 #define EXTMEM_CACHE_REQUEST_BYPASS_V 0x00000001U 822 #define EXTMEM_CACHE_REQUEST_BYPASS_S 0 823 824 /** EXTMEM_CLOCK_GATE_REG register 825 * This description will be updated in the near future. 826 */ 827 #define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100) 828 /** EXTMEM_CLK_EN : R/W; bitpos: [0]; default: 1; 829 * clock gate enable. 830 */ 831 #define EXTMEM_CLK_EN (BIT(0)) 832 #define EXTMEM_CLK_EN_M (EXTMEM_CLK_EN_V << EXTMEM_CLK_EN_S) 833 #define EXTMEM_CLK_EN_V 0x00000001U 834 #define EXTMEM_CLK_EN_S 0 835 836 /** EXTMEM_REG_DATE_REG register 837 * This description will be updated in the near future. 838 */ 839 #define EXTMEM_REG_DATE_REG (DR_REG_EXTMEM_BASE + 0x3fc) 840 /** EXTMEM_DATE : R/W; bitpos: [27:0]; default: 34631760; 841 * version information 842 */ 843 #define EXTMEM_DATE 0x0FFFFFFFU 844 #define EXTMEM_DATE_M (EXTMEM_DATE_V << EXTMEM_DATE_S) 845 #define EXTMEM_DATE_V 0x0FFFFFFFU 846 #define EXTMEM_DATE_S 0 847 848 #ifdef __cplusplus 849 } 850 #endif 851
