Searched refs:EXTMEM_ICACHE_CTRL1_REG (Results 1 – 6 of 6) sorted by relevance
| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | cache_ll.h | 100 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_enable_bus()
104 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_enable_bus()
122 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_disable_bus()
126 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | cache_ll.h | 101 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_enable_bus()
105 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_enable_bus()
123 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_disable_bus()
127 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | cache_ll.h | 116 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_enable_bus()
141 uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG); in cache_ll_l1_get_enabled_bus()
177 REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); in cache_ll_l1_disable_bus()
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | extmem_reg.h | 29 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) macro
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | extmem_reg.h | 30 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) macro
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | extmem_reg.h | 405 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64) macro
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