1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_EXTMEM_REG_H_ 15 #define _SOC_EXTMEM_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) 23 /* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 24 /*description: The bit is used to activate the data cache. 0: disable 1: enable*/ 25 #define EXTMEM_ICACHE_ENABLE (BIT(0)) 26 #define EXTMEM_ICACHE_ENABLE_M (BIT(0)) 27 #define EXTMEM_ICACHE_ENABLE_V 0x1 28 #define EXTMEM_ICACHE_ENABLE_S 0 29 30 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) 31 /* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 32 /*description: The bit is used to disable core1 ibus 0: enable 1: disable*/ 33 #define EXTMEM_ICACHE_SHUT_DBUS (BIT(1)) 34 #define EXTMEM_ICACHE_SHUT_DBUS_M (BIT(1)) 35 #define EXTMEM_ICACHE_SHUT_DBUS_V 0x1 36 #define EXTMEM_ICACHE_SHUT_DBUS_S 1 37 /* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ 38 /*description: The bit is used to disable core0 ibus 0: enable 1: disable*/ 39 #define EXTMEM_ICACHE_SHUT_IBUS (BIT(0)) 40 #define EXTMEM_ICACHE_SHUT_IBUS_M (BIT(0)) 41 #define EXTMEM_ICACHE_SHUT_IBUS_V 0x1 42 #define EXTMEM_ICACHE_SHUT_IBUS_S 0 43 44 #define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) 45 /* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 46 /*description: The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/ 47 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) 48 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) 49 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 50 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 51 /* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 52 /*description: The bit is used to power icache tag memory down 0: follow rtc_lslp 53 1: power down*/ 54 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) 55 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) 56 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 57 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 58 /* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 59 /*description: The bit is used to close clock gating of icache tag memory. 60 1: close gating 0: open clock gating.*/ 61 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) 62 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) 63 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 64 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 65 66 #define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C) 67 /* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 68 /*description: The bit is used to enable the second section of prelock function.*/ 69 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) 70 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1)) 71 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1 72 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 73 /* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 74 /*description: The bit is used to enable the first section of prelock function.*/ 75 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) 76 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0)) 77 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1 78 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 79 80 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010) 81 /* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 82 /*description: The bits are used to configure the first start virtual address 83 of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/ 84 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF 85 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)) 86 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF 87 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 88 89 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) 90 /* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 91 /*description: The bits are used to configure the second start virtual address 92 of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ 93 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF 94 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)) 95 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF 96 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 97 98 #define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) 99 /* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 100 /*description: The bits are used to configure the first length of data locking 101 which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ 102 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF 103 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) 104 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF 105 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 106 /* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 107 /*description: The bits are used to configure the second length of data locking 108 which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ 109 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF 110 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) 111 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF 112 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 113 114 #define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C) 115 /* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ 116 /*description: The bit is used to indicate unlock/lock operation is finished.*/ 117 #define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) 118 #define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2)) 119 #define EXTMEM_ICACHE_LOCK_DONE_V 0x1 120 #define EXTMEM_ICACHE_LOCK_DONE_S 2 121 /* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 122 /*description: The bit is used to enable unlock operation. It will be cleared 123 by hardware after unlock operation done.*/ 124 #define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) 125 #define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1)) 126 #define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1 127 #define EXTMEM_ICACHE_UNLOCK_ENA_S 1 128 /* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 129 /*description: The bit is used to enable lock operation. It will be cleared 130 by hardware after lock operation done.*/ 131 #define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) 132 #define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0)) 133 #define EXTMEM_ICACHE_LOCK_ENA_V 0x1 134 #define EXTMEM_ICACHE_LOCK_ENA_S 0 135 136 #define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020) 137 /* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 138 /*description: The bits are used to configure the start virtual address for 139 lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ 140 #define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF 141 #define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S)) 142 #define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF 143 #define EXTMEM_ICACHE_LOCK_ADDR_S 0 144 145 #define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024) 146 /* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 147 /*description: The bits are used to configure the length for lock operations. 148 The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ 149 #define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF 150 #define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S)) 151 #define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF 152 #define EXTMEM_ICACHE_LOCK_SIZE_S 0 153 154 #define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x028) 155 /* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ 156 /*description: The bit is used to indicate invalidate operation is finished.*/ 157 #define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) 158 #define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) 159 #define EXTMEM_ICACHE_SYNC_DONE_V 0x1 160 #define EXTMEM_ICACHE_SYNC_DONE_S 1 161 /* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 162 /*description: The bit is used to enable invalidate operation. It will be cleared 163 by hardware after invalidate operation done.*/ 164 #define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) 165 #define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) 166 #define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 167 #define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 168 169 #define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x02C) 170 /* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 171 /*description: The bits are used to configure the start virtual address for 172 clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ 173 #define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF 174 #define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) 175 #define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF 176 #define EXTMEM_ICACHE_SYNC_ADDR_S 0 177 178 #define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x030) 179 /* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ 180 /*description: The bits are used to configure the length for sync operations. 181 The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ 182 #define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF 183 #define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) 184 #define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF 185 #define EXTMEM_ICACHE_SYNC_SIZE_S 0 186 187 #define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x034) 188 /* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ 189 /*description: The bit is used to configure the direction of preload operation. 190 1: descending 0: ascending.*/ 191 #define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) 192 #define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2)) 193 #define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1 194 #define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 195 /* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ 196 /*description: The bit is used to indicate preload operation is finished.*/ 197 #define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) 198 #define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1)) 199 #define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1 200 #define EXTMEM_ICACHE_PRELOAD_DONE_S 1 201 /* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 202 /*description: The bit is used to enable preload operation. It will be cleared 203 by hardware after preload operation done.*/ 204 #define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) 205 #define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0)) 206 #define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1 207 #define EXTMEM_ICACHE_PRELOAD_ENA_S 0 208 209 #define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) 210 /* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 211 /*description: The bits are used to configure the start virtual address for 212 preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ 213 #define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF 214 #define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S)) 215 #define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF 216 #define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 217 218 #define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) 219 /* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 220 /*description: The bits are used to configure the length for preload operation. 221 The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ 222 #define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF 223 #define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S)) 224 #define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF 225 #define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 226 227 #define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) 228 /* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ 229 /*description: The bits are used to configure trigger conditions for autoload. 230 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ 231 #define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 232 #define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S)) 233 #define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3 234 #define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 235 /* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ 236 /*description: The bits are used to configure the direction of autoload. 1: 237 descending 0: ascending.*/ 238 #define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) 239 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4)) 240 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1 241 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 242 /* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */ 243 /*description: The bit is used to indicate autoload operation is finished.*/ 244 #define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) 245 #define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3)) 246 #define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1 247 #define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 248 /* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 249 /*description: The bit is used to enable and disable autoload operation. It 250 is combined with icache_autoload_done. 1: enable 0: disable.*/ 251 #define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) 252 #define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2)) 253 #define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1 254 #define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 255 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 256 /*description: The bits are used to enable the second section for autoload operation.*/ 257 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) 258 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) 259 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 260 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 261 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 262 /*description: The bits are used to enable the first section for autoload operation.*/ 263 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) 264 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) 265 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 266 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 267 268 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x044) 269 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 270 /*description: The bits are used to configure the start virtual address of the 271 first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ 272 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF 273 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) 274 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF 275 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 276 277 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x048) 278 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 279 /*description: The bits are used to configure the length of the first section 280 for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ 281 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF 282 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)) 283 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF 284 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 285 286 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x04C) 287 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 288 /*description: The bits are used to configure the start virtual address of the 289 second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ 290 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF 291 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)) 292 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF 293 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 294 295 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x050) 296 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 297 /*description: The bits are used to configure the length of the second section 298 for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ 299 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF 300 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)) 301 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF 302 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 303 304 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x054) 305 /* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */ 306 /*description: The bits are used to configure the start virtual address of ibus 307 to access flash. The register is used to give constraints to ibus access counter.*/ 308 #define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF 309 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) 310 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF 311 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 312 313 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x058) 314 /* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h427FFFFF ; */ 315 /*description: The bits are used to configure the end virtual address of ibus 316 to access flash. The register is used to give constraints to ibus access counter.*/ 317 #define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF 318 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) 319 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF 320 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 321 322 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x05C) 323 /* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C000000 ; */ 324 /*description: The bits are used to configure the start virtual address of dbus 325 to access flash. The register is used to give constraints to dbus access counter.*/ 326 #define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF 327 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) 328 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF 329 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 330 331 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x060) 332 /* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C7FFFFF ; */ 333 /*description: The bits are used to configure the end virtual address of dbus 334 to access flash. The register is used to give constraints to dbus access counter.*/ 335 #define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF 336 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) 337 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF 338 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 339 340 #define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x064) 341 /* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 342 /*description: The bit is used to clear dbus counter.*/ 343 #define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1)) 344 #define EXTMEM_DBUS_ACS_CNT_CLR_M (BIT(1)) 345 #define EXTMEM_DBUS_ACS_CNT_CLR_V 0x1 346 #define EXTMEM_DBUS_ACS_CNT_CLR_S 1 347 /* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 348 /*description: The bit is used to clear ibus counter.*/ 349 #define EXTMEM_IBUS_ACS_CNT_CLR (BIT(0)) 350 #define EXTMEM_IBUS_ACS_CNT_CLR_M (BIT(0)) 351 #define EXTMEM_IBUS_ACS_CNT_CLR_V 0x1 352 #define EXTMEM_IBUS_ACS_CNT_CLR_S 0 353 354 #define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x068) 355 /* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 356 /*description: The bits are used to count the number of the cache miss caused 357 by ibus access flash.*/ 358 #define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF 359 #define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S)) 360 #define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF 361 #define EXTMEM_IBUS_ACS_MISS_CNT_S 0 362 363 #define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x06C) 364 /* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 365 /*description: The bits are used to count the number of ibus access flash through icache.*/ 366 #define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF 367 #define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S)) 368 #define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF 369 #define EXTMEM_IBUS_ACS_CNT_S 0 370 371 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x070) 372 /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 373 /*description: The bits are used to count the number of the cache miss caused 374 by dbus access flash.*/ 375 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF 376 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)) 377 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF 378 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 379 380 #define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x074) 381 /* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 382 /*description: The bits are used to count the number of dbus access flash through icache.*/ 383 #define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF 384 #define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S)) 385 #define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF 386 #define EXTMEM_DBUS_ACS_CNT_S 0 387 388 #define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x078) 389 /* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 390 /*description: The bit is used to enable interrupt by dbus counter overflow.*/ 391 #define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) 392 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) 393 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 394 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 395 /* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 396 /*description: The bit is used to enable interrupt by ibus counter overflow.*/ 397 #define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) 398 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) 399 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 400 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 401 /* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 402 /*description: The bit is used to enable interrupt by mmu entry fault.*/ 403 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) 404 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) 405 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 406 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 407 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 408 /*description: The bit is used to enable interrupt by preload configurations fault.*/ 409 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) 410 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) 411 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 412 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 413 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 414 /*description: The bit is used to enable interrupt by sync configurations fault.*/ 415 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) 416 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) 417 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 418 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 419 420 #define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x07C) 421 /* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ 422 /*description: The bit is used to clear interrupt by dbus counter overflow.*/ 423 #define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) 424 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) 425 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 426 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 427 /* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ 428 /*description: The bit is used to clear interrupt by ibus counter overflow.*/ 429 #define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) 430 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) 431 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 432 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 433 /* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 434 /*description: The bit is used to clear interrupt by mmu entry fault.*/ 435 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) 436 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) 437 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 438 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 439 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 440 /*description: The bit is used to clear interrupt by preload configurations fault.*/ 441 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) 442 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) 443 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 444 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 445 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 446 /*description: The bit is used to clear interrupt by sync configurations fault.*/ 447 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) 448 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) 449 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 450 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 451 452 #define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x080) 453 /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 454 /*description: The bit is used to indicate interrupt by dbus access flash miss 455 counter overflow.*/ 456 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) 457 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) 458 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 459 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 460 /* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 461 /*description: The bit is used to indicate interrupt by dbus access flash/spiram 462 counter overflow.*/ 463 #define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) 464 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) 465 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 466 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 467 /* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 468 /*description: The bit is used to indicate interrupt by ibus access flash/spiram 469 miss counter overflow.*/ 470 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) 471 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) 472 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 473 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 474 /* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 475 /*description: The bit is used to indicate interrupt by ibus access flash/spiram 476 counter overflow.*/ 477 #define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) 478 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) 479 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 480 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 481 /* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 482 /*description: The bit is used to indicate interrupt by mmu entry fault.*/ 483 #define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) 484 #define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) 485 #define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 486 #define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 487 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 488 /*description: The bit is used to indicate interrupt by preload configurations fault.*/ 489 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) 490 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) 491 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 492 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 493 /* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 494 /*description: The bit is used to indicate interrupt by sync configurations fault.*/ 495 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) 496 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) 497 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 498 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 499 500 #define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x084) 501 /* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 502 /*description: The bit is used to enable interrupt by dbus trying to write icache*/ 503 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5)) 504 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (BIT(5)) 505 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x1 506 #define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5 507 /* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 508 /*description: The bit is used to enable interrupt by authentication fail.*/ 509 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) 510 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) 511 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 512 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 513 /* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 514 /*description: The bit is used to enable interrupt by cpu access icache while 515 the corresponding dbus is disabled which include speculative access.*/ 516 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3)) 517 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (BIT(3)) 518 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x1 519 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3 520 /* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 521 /*description: The bit is used to enable interrupt by authentication fail.*/ 522 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) 523 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) 524 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 525 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 526 /* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 527 /*description: The bit is used to enable interrupt by ibus trying to write icache*/ 528 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) 529 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) 530 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 531 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 532 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 533 /*description: The bit is used to enable interrupt by cpu access icache while 534 the corresponding ibus is disabled which include speculative access.*/ 535 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) 536 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) 537 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 538 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 539 540 #define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x088) 541 /* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 542 /*description: The bit is used to clear interrupt by dbus trying to write icache*/ 543 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5)) 544 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (BIT(5)) 545 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x1 546 #define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5 547 /* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ 548 /*description: The bit is used to clear interrupt by authentication fail.*/ 549 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) 550 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) 551 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 552 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 553 /* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ 554 /*description: The bit is used to clear interrupt by cpu access icache while 555 the corresponding dbus is disabled or icache is disabled which include speculative access.*/ 556 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3)) 557 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (BIT(3)) 558 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x1 559 #define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3 560 /* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 561 /*description: The bit is used to clear interrupt by authentication fail.*/ 562 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) 563 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) 564 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 565 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 566 /* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 567 /*description: The bit is used to clear interrupt by ibus trying to write icache*/ 568 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) 569 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) 570 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 571 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 572 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 573 /*description: The bit is used to clear interrupt by cpu access icache while 574 the corresponding ibus is disabled or icache is disabled which include speculative access.*/ 575 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) 576 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) 577 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 578 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 579 580 #define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x08C) 581 /* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 582 /*description: The bit is used to indicate interrupt by dbus trying to write icache*/ 583 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5)) 584 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (BIT(5)) 585 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x1 586 #define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5 587 /* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 588 /*description: The bit is used to indicate interrupt by authentication fail.*/ 589 #define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) 590 #define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) 591 #define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 592 #define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 593 /* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 594 /*description: The bit is used to indicate interrupt by cpu access icache while 595 the core0_dbus is disabled or icache is disabled which include speculative access.*/ 596 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3)) 597 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (BIT(3)) 598 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x1 599 #define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3 600 /* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 601 /*description: The bit is used to indicate interrupt by authentication fail.*/ 602 #define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) 603 #define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) 604 #define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 605 #define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 606 /* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 607 /*description: The bit is used to indicate interrupt by ibus trying to write icache*/ 608 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) 609 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) 610 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 611 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 612 /* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 613 /*description: The bit is used to indicate interrupt by cpu access icache while 614 the core0_ibus is disabled or icache is disabled which include speculative access.*/ 615 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) 616 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) 617 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 618 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 619 620 #define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x090) 621 /* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ 622 /*description: The bit is used to indicate the world of CPU access dbus when 623 authentication fail. 0: WORLD0 1: WORLD1*/ 624 #define EXTMEM_CORE0_DBUS_WORLD (BIT(3)) 625 #define EXTMEM_CORE0_DBUS_WORLD_M (BIT(3)) 626 #define EXTMEM_CORE0_DBUS_WORLD_V 0x1 627 #define EXTMEM_CORE0_DBUS_WORLD_S 3 628 /* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 629 /*description: The bits are used to indicate the attribute of CPU access dbus 630 when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ 631 #define EXTMEM_CORE0_DBUS_ATTR 0x00000007 632 #define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) 633 #define EXTMEM_CORE0_DBUS_ATTR_V 0x7 634 #define EXTMEM_CORE0_DBUS_ATTR_S 0 635 636 #define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x094) 637 /* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ 638 /*description: The bits are used to indicate the virtual address of CPU access 639 dbus when authentication fail.*/ 640 #define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF 641 #define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) 642 #define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF 643 #define EXTMEM_CORE0_DBUS_VADDR_S 0 644 645 #define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x098) 646 /* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ 647 /*description: The bit is used to indicate the world of CPU access ibus when 648 authentication fail. 0: WORLD0 1: WORLD1*/ 649 #define EXTMEM_CORE0_IBUS_WORLD (BIT(3)) 650 #define EXTMEM_CORE0_IBUS_WORLD_M (BIT(3)) 651 #define EXTMEM_CORE0_IBUS_WORLD_V 0x1 652 #define EXTMEM_CORE0_IBUS_WORLD_S 3 653 /* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 654 /*description: The bits are used to indicate the attribute of CPU access ibus 655 when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ 656 #define EXTMEM_CORE0_IBUS_ATTR 0x00000007 657 #define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) 658 #define EXTMEM_CORE0_IBUS_ATTR_V 0x7 659 #define EXTMEM_CORE0_IBUS_ATTR_S 0 660 661 #define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x09C) 662 /* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ 663 /*description: The bits are used to indicate the virtual address of CPU access 664 ibus when authentication fail.*/ 665 #define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF 666 #define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) 667 #define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF 668 #define EXTMEM_CORE0_IBUS_VADDR_S 0 669 670 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x0A0) 671 /* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */ 672 /*description: The right-most 3 bits are used to indicate the operations which 673 cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ 674 #define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F 675 #define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) 676 #define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF 677 #define EXTMEM_CACHE_MMU_FAULT_CODE_S 10 678 /* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 679 /*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/ 680 #define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000003FF 681 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) 682 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x3FF 683 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 684 685 #define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0A4) 686 /* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 687 /*description: The bits are used to indicate the virtual address which cause mmu fault..*/ 688 #define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF 689 #define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) 690 #define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF 691 #define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 692 693 #define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0A8) 694 /* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ 695 /*description: The bit is used to enable wrap around mode when read data from flash.*/ 696 #define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) 697 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) 698 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 699 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 700 701 #define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0AC) 702 /* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 703 /*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ 704 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) 705 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) 706 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 707 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 708 /* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 709 /*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ 710 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) 711 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) 712 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 713 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 714 /* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 715 /*description: The bit is used to enable clock gating to save power when access 716 mmu memory 0: enable 1: disable*/ 717 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) 718 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) 719 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 720 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 721 722 #define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x0B0) 723 /* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */ 724 /*description: The bit is used to indicate whether icache main fsm is in idle 725 state or not. 1: in idle state 0: not in idle state*/ 726 #define EXTMEM_ICACHE_STATE 0x00000FFF 727 #define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) 728 #define EXTMEM_ICACHE_STATE_V 0xFFF 729 #define EXTMEM_ICACHE_STATE_S 0 730 731 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x0B4) 732 /* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 733 /*description: Reserved.*/ 734 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) 735 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) 736 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 737 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 738 /* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 739 /*description: Reserved.*/ 740 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) 741 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) 742 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 743 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 744 745 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x0B8) 746 /* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ 747 /*description: The bit is used to close clock gating of external memory encrypt 748 and decrypt clock. 1: close gating 0: open clock gating.*/ 749 #define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) 750 #define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) 751 #define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 752 #define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 753 /* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ 754 /*description: The bit is used to close clock gating of automatic crypt clock. 755 1: close gating 0: open clock gating.*/ 756 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) 757 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) 758 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 759 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 760 /* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ 761 /*description: The bit is used to close clock gating of manual crypt clock. 762 1: close gating 0: open clock gating.*/ 763 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) 764 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) 765 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 766 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 767 768 #define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0BC) 769 /* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 770 /*description: The bit is used to clear the interrupt by icache pre-load done.*/ 771 #define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) 772 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) 773 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 774 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 775 /* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 776 /*description: The bit is used to enable the interrupt by icache pre-load done.*/ 777 #define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) 778 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) 779 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 780 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 781 /* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 782 /*description: The bit is used to indicate the interrupt by icache pre-load done.*/ 783 #define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) 784 #define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) 785 #define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 786 #define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 787 788 #define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0C0) 789 /* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 790 /*description: The bit is used to clear the interrupt by icache sync done.*/ 791 #define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) 792 #define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) 793 #define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 794 #define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 795 /* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 796 /*description: The bit is used to enable the interrupt by icache sync done.*/ 797 #define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) 798 #define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) 799 #define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 800 #define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 801 /* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 802 /*description: The bit is used to indicate the interrupt by icache sync done.*/ 803 #define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) 804 #define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) 805 #define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 806 #define EXTMEM_ICACHE_SYNC_INT_ST_S 0 807 808 #define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x0C4) 809 /* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ 810 /*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus bit1/bit3: dbus*/ 811 #define EXTMEM_CACHE_MMU_OWNER 0x0000000F 812 #define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) 813 #define EXTMEM_CACHE_MMU_OWNER_V 0xF 814 #define EXTMEM_CACHE_MMU_OWNER_S 0 815 816 #define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x0C8) 817 /* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ 818 /*description: The bit is used to enable cache trace function.*/ 819 #define EXTMEM_CACHE_TRACE_ENA (BIT(2)) 820 #define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) 821 #define EXTMEM_CACHE_TRACE_ENA_V 0x1 822 #define EXTMEM_CACHE_TRACE_ENA_S 2 823 /* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ 824 /*description: The bit is used to disable checking mmu entry fault by sync operation.*/ 825 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) 826 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) 827 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 828 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 829 /* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ 830 /*description: The bit is used to disable checking mmu entry fault by preload operation.*/ 831 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) 832 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) 833 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 834 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 835 836 #define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x0CC) 837 /* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ 838 /*description: The bit is used to indicate icache freeze success*/ 839 #define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) 840 #define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) 841 #define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 842 #define EXTMEM_ICACHE_FREEZE_DONE_S 2 843 /* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 844 /*description: The bit is used to configure freeze mode 0: assert busy if 845 CPU miss 1: assert hit if CPU miss*/ 846 #define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) 847 #define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) 848 #define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 849 #define EXTMEM_ICACHE_FREEZE_MODE_S 1 850 /* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 851 /*description: The bit is used to enable icache freeze mode*/ 852 #define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) 853 #define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) 854 #define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 855 #define EXTMEM_ICACHE_FREEZE_ENA_S 0 856 857 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x0D0) 858 /* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 859 /*description: The bit is used to activate icache atomic operation protection. 860 In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ 861 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) 862 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) 863 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 864 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 865 866 #define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x0D4) 867 /* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 868 /*description: The bit is used to disable request recording which could cause performance issue*/ 869 #define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) 870 #define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) 871 #define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 872 #define EXTMEM_CACHE_REQUEST_BYPASS_S 0 873 874 #define EXTMEM_IBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0D8) 875 /* EXTMEM_IBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 876 /*description: The bit is used to configure the ibus permission control section boundary0*/ 877 #define EXTMEM_IBUS_PMS_LOCK (BIT(0)) 878 #define EXTMEM_IBUS_PMS_LOCK_M (BIT(0)) 879 #define EXTMEM_IBUS_PMS_LOCK_V 0x1 880 #define EXTMEM_IBUS_PMS_LOCK_S 0 881 882 #define EXTMEM_IBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0DC) 883 /* EXTMEM_IBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ 884 /*description: The bit is used to configure the ibus permission control section boundary0*/ 885 #define EXTMEM_IBUS_PMS_BOUNDARY0 0x00000FFF 886 #define EXTMEM_IBUS_PMS_BOUNDARY0_M ((EXTMEM_IBUS_PMS_BOUNDARY0_V)<<(EXTMEM_IBUS_PMS_BOUNDARY0_S)) 887 #define EXTMEM_IBUS_PMS_BOUNDARY0_V 0xFFF 888 #define EXTMEM_IBUS_PMS_BOUNDARY0_S 0 889 890 #define EXTMEM_IBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0E0) 891 /* EXTMEM_IBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ 892 /*description: The bit is used to configure the ibus permission control section boundary1*/ 893 #define EXTMEM_IBUS_PMS_BOUNDARY1 0x00000FFF 894 #define EXTMEM_IBUS_PMS_BOUNDARY1_M ((EXTMEM_IBUS_PMS_BOUNDARY1_V)<<(EXTMEM_IBUS_PMS_BOUNDARY1_S)) 895 #define EXTMEM_IBUS_PMS_BOUNDARY1_V 0xFFF 896 #define EXTMEM_IBUS_PMS_BOUNDARY1_S 0 897 898 #define EXTMEM_IBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0E4) 899 /* EXTMEM_IBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ 900 /*description: The bit is used to configure the ibus permission control section boundary2*/ 901 #define EXTMEM_IBUS_PMS_BOUNDARY2 0x00000FFF 902 #define EXTMEM_IBUS_PMS_BOUNDARY2_M ((EXTMEM_IBUS_PMS_BOUNDARY2_V)<<(EXTMEM_IBUS_PMS_BOUNDARY2_S)) 903 #define EXTMEM_IBUS_PMS_BOUNDARY2_V 0xFFF 904 #define EXTMEM_IBUS_PMS_BOUNDARY2_S 0 905 906 #define EXTMEM_IBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0E8) 907 /* EXTMEM_IBUS_PMS_SCT2_ATTR : R/W ;bitpos:[7:4] ;default: 4'hF ; */ 908 /*description: The bit is used to configure attribute of the ibus permission 909 control section2 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/ 910 #define EXTMEM_IBUS_PMS_SCT2_ATTR 0x0000000F 911 #define EXTMEM_IBUS_PMS_SCT2_ATTR_M ((EXTMEM_IBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT2_ATTR_S)) 912 #define EXTMEM_IBUS_PMS_SCT2_ATTR_V 0xF 913 #define EXTMEM_IBUS_PMS_SCT2_ATTR_S 4 914 /* EXTMEM_IBUS_PMS_SCT1_ATTR : R/W ;bitpos:[3:0] ;default: 4'hF ; */ 915 /*description: The bit is used to configure attribute of the ibus permission 916 control section1 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/ 917 #define EXTMEM_IBUS_PMS_SCT1_ATTR 0x0000000F 918 #define EXTMEM_IBUS_PMS_SCT1_ATTR_M ((EXTMEM_IBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT1_ATTR_S)) 919 #define EXTMEM_IBUS_PMS_SCT1_ATTR_V 0xF 920 #define EXTMEM_IBUS_PMS_SCT1_ATTR_S 0 921 922 #define EXTMEM_DBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0EC) 923 /* EXTMEM_DBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 924 /*description: The bit is used to configure the ibus permission control section boundary0*/ 925 #define EXTMEM_DBUS_PMS_LOCK (BIT(0)) 926 #define EXTMEM_DBUS_PMS_LOCK_M (BIT(0)) 927 #define EXTMEM_DBUS_PMS_LOCK_V 0x1 928 #define EXTMEM_DBUS_PMS_LOCK_S 0 929 930 #define EXTMEM_DBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0F0) 931 /* EXTMEM_DBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ 932 /*description: The bit is used to configure the dbus permission control section boundary0*/ 933 #define EXTMEM_DBUS_PMS_BOUNDARY0 0x00000FFF 934 #define EXTMEM_DBUS_PMS_BOUNDARY0_M ((EXTMEM_DBUS_PMS_BOUNDARY0_V)<<(EXTMEM_DBUS_PMS_BOUNDARY0_S)) 935 #define EXTMEM_DBUS_PMS_BOUNDARY0_V 0xFFF 936 #define EXTMEM_DBUS_PMS_BOUNDARY0_S 0 937 938 #define EXTMEM_DBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0F4) 939 /* EXTMEM_DBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ 940 /*description: The bit is used to configure the dbus permission control section boundary1*/ 941 #define EXTMEM_DBUS_PMS_BOUNDARY1 0x00000FFF 942 #define EXTMEM_DBUS_PMS_BOUNDARY1_M ((EXTMEM_DBUS_PMS_BOUNDARY1_V)<<(EXTMEM_DBUS_PMS_BOUNDARY1_S)) 943 #define EXTMEM_DBUS_PMS_BOUNDARY1_V 0xFFF 944 #define EXTMEM_DBUS_PMS_BOUNDARY1_S 0 945 946 #define EXTMEM_DBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0F8) 947 /* EXTMEM_DBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ 948 /*description: The bit is used to configure the dbus permission control section boundary2*/ 949 #define EXTMEM_DBUS_PMS_BOUNDARY2 0x00000FFF 950 #define EXTMEM_DBUS_PMS_BOUNDARY2_M ((EXTMEM_DBUS_PMS_BOUNDARY2_V)<<(EXTMEM_DBUS_PMS_BOUNDARY2_S)) 951 #define EXTMEM_DBUS_PMS_BOUNDARY2_V 0xFFF 952 #define EXTMEM_DBUS_PMS_BOUNDARY2_S 0 953 954 #define EXTMEM_DBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0FC) 955 /* EXTMEM_DBUS_PMS_SCT2_ATTR : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ 956 /*description: The bit is used to configure attribute of the dbus permission 957 control section2 bit0: load in world0 bit2: load in world1*/ 958 #define EXTMEM_DBUS_PMS_SCT2_ATTR 0x00000003 959 #define EXTMEM_DBUS_PMS_SCT2_ATTR_M ((EXTMEM_DBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT2_ATTR_S)) 960 #define EXTMEM_DBUS_PMS_SCT2_ATTR_V 0x3 961 #define EXTMEM_DBUS_PMS_SCT2_ATTR_S 2 962 /* EXTMEM_DBUS_PMS_SCT1_ATTR : R/W ;bitpos:[1:0] ;default: 2'd3 ; */ 963 /*description: The bit is used to configure attribute of the dbus permission 964 control section1 bit0: load in world0 bit2: load in world1*/ 965 #define EXTMEM_DBUS_PMS_SCT1_ATTR 0x00000003 966 #define EXTMEM_DBUS_PMS_SCT1_ATTR_M ((EXTMEM_DBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT1_ATTR_S)) 967 #define EXTMEM_DBUS_PMS_SCT1_ATTR_V 0x3 968 #define EXTMEM_DBUS_PMS_SCT1_ATTR_S 0 969 970 #define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100) 971 /* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 972 /*description: Reserved.*/ 973 #define EXTMEM_CLK_EN (BIT(0)) 974 #define EXTMEM_CLK_EN_M (BIT(0)) 975 #define EXTMEM_CLK_EN_V 0x1 976 #define EXTMEM_CLK_EN_S 0 977 978 #define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) 979 /* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */ 980 /*description: Reserved.*/ 981 #define EXTMEM_DATE 0x0FFFFFFF 982 #define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) 983 #define EXTMEM_DATE_V 0xFFFFFFF 984 #define EXTMEM_DATE_S 0 985 986 #ifdef __cplusplus 987 } 988 #endif 989 990 991 992 #endif /*_SOC_EXTMEM_REG_H_ */ 993
