1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #include "efuse_defs.h" 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** EFUSE_PGM_DATA0_REG register 16 * Register 0 that stores data to be programmed. 17 */ 18 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) 19 /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; 20 * The content of the 0th 32-bit data to be programmed. 21 */ 22 #define EFUSE_PGM_DATA_0 0xFFFFFFFFU 23 #define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) 24 #define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU 25 #define EFUSE_PGM_DATA_0_S 0 26 27 /** EFUSE_PGM_DATA1_REG register 28 * Register 1 that stores data to be programmed. 29 */ 30 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) 31 /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; 32 * The content of the 1st 32-bit data to be programmed. 33 */ 34 #define EFUSE_PGM_DATA_1 0xFFFFFFFFU 35 #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) 36 #define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU 37 #define EFUSE_PGM_DATA_1_S 0 38 39 /** EFUSE_PGM_DATA2_REG register 40 * Register 2 that stores data to be programmed. 41 */ 42 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) 43 /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; 44 * The content of the 2nd 32-bit data to be programmed. 45 */ 46 #define EFUSE_PGM_DATA_2 0xFFFFFFFFU 47 #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) 48 #define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU 49 #define EFUSE_PGM_DATA_2_S 0 50 51 /** EFUSE_PGM_DATA3_REG register 52 * Register 3 that stores data to be programmed. 53 */ 54 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) 55 /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; 56 * The content of the 3rd 32-bit data to be programmed. 57 */ 58 #define EFUSE_PGM_DATA_3 0xFFFFFFFFU 59 #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) 60 #define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU 61 #define EFUSE_PGM_DATA_3_S 0 62 63 /** EFUSE_PGM_DATA4_REG register 64 * Register 4 that stores data to be programmed. 65 */ 66 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) 67 /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; 68 * The content of the 4th 32-bit data to be programmed. 69 */ 70 #define EFUSE_PGM_DATA_4 0xFFFFFFFFU 71 #define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) 72 #define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU 73 #define EFUSE_PGM_DATA_4_S 0 74 75 /** EFUSE_PGM_DATA5_REG register 76 * Register 5 that stores data to be programmed. 77 */ 78 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) 79 /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; 80 * The content of the 5th 32-bit data to be programmed. 81 */ 82 #define EFUSE_PGM_DATA_5 0xFFFFFFFFU 83 #define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) 84 #define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU 85 #define EFUSE_PGM_DATA_5_S 0 86 87 /** EFUSE_PGM_DATA6_REG register 88 * Register 6 that stores data to be programmed. 89 */ 90 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) 91 /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; 92 * The content of the 6th 32-bit data to be programmed. 93 */ 94 #define EFUSE_PGM_DATA_6 0xFFFFFFFFU 95 #define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) 96 #define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU 97 #define EFUSE_PGM_DATA_6_S 0 98 99 /** EFUSE_PGM_DATA7_REG register 100 * Register 7 that stores data to be programmed. 101 */ 102 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) 103 /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; 104 * The content of the 7th 32-bit data to be programmed. 105 */ 106 #define EFUSE_PGM_DATA_7 0xFFFFFFFFU 107 #define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) 108 #define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU 109 #define EFUSE_PGM_DATA_7_S 0 110 111 /** EFUSE_PGM_CHECK_VALUE0_REG register 112 * Register 0 that stores the RS code to be programmed. 113 */ 114 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) 115 /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; 116 * The content of the 0th 32-bit RS code to be programmed. 117 */ 118 #define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU 119 #define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) 120 #define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU 121 #define EFUSE_PGM_RS_DATA_0_S 0 122 123 /** EFUSE_PGM_CHECK_VALUE1_REG register 124 * Register 1 that stores the RS code to be programmed. 125 */ 126 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) 127 /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; 128 * The content of the 1st 32-bit RS code to be programmed. 129 */ 130 #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU 131 #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) 132 #define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU 133 #define EFUSE_PGM_RS_DATA_1_S 0 134 135 /** EFUSE_PGM_CHECK_VALUE2_REG register 136 * Register 2 that stores the RS code to be programmed. 137 */ 138 #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) 139 /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; 140 * The content of the 2nd 32-bit RS code to be programmed. 141 */ 142 #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU 143 #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) 144 #define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU 145 #define EFUSE_PGM_RS_DATA_2_S 0 146 147 /** EFUSE_RD_WR_DIS_REG register 148 * BLOCK0 data register 0. 149 */ 150 #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) 151 /** EFUSE_WR_DIS : RO; bitpos: [7:0]; default: 0; 152 * Disable programming of individual eFuses. 153 */ 154 #define EFUSE_WR_DIS 0x000000FFU 155 #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) 156 #define EFUSE_WR_DIS_V 0x000000FFU 157 #define EFUSE_WR_DIS_S 0 158 /** EFUSE_RESERVED_0_8 : RW; bitpos: [31:8]; default: 0; */ 159 #define EFUSE_RESERVED_0_8 0x00FFFFFFU 160 #define EFUSE_RESERVED_0_8_M (EFUSE_RESERVED_0_8_V << EFUSE_RESERVED_0_8_S) 161 #define EFUSE_RESERVED_0_8_V 0x00FFFFFFU 162 #define EFUSE_RESERVED_0_8_S 8 163 164 /** EFUSE_RD_REPEAT_DATA0_REG register 165 * BLOCK0 data register 1. 166 */ 167 #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) 168 /** EFUSE_RD_DIS : RO; bitpos: [1:0]; default: 0; 169 * The bit be set to disable software read high/low 128-bit of BLK3. 170 */ 171 #define EFUSE_RD_DIS 0x00000003U 172 #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) 173 #define EFUSE_RD_DIS_V 0x00000003U 174 #define EFUSE_RD_DIS_S 0 175 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [3:2]; default: 0; 176 * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 177 * 80000. 2: 160000. 3:320000. 178 */ 179 #define EFUSE_WDT_DELAY_SEL 0x00000003U 180 #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) 181 #define EFUSE_WDT_DELAY_SEL_V 0x00000003U 182 #define EFUSE_WDT_DELAY_SEL_S 2 183 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [4]; default: 0; 184 * Set this bit to disable pad jtag. 185 */ 186 #define EFUSE_DIS_PAD_JTAG (BIT(4)) 187 #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) 188 #define EFUSE_DIS_PAD_JTAG_V 0x00000001U 189 #define EFUSE_DIS_PAD_JTAG_S 4 190 /** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [5]; default: 0; 191 * The bit be set to disable icache in download mode. 192 */ 193 #define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(5)) 194 #define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) 195 #define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U 196 #define EFUSE_DIS_DOWNLOAD_ICACHE_S 5 197 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [6]; default: 0; 198 * The bit be set to disable manual encryption. 199 */ 200 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(6)) 201 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) 202 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U 203 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 6 204 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [9:7]; default: 0; 205 * These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even 206 * number of 1: disable. 207 */ 208 #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U 209 #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) 210 #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U 211 #define EFUSE_SPI_BOOT_CRYPT_CNT_S 7 212 /** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [10]; default: 0; 213 * The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, 214 * XTS_AES use 128-bit eFuse data in BLOCK3. 215 */ 216 #define EFUSE_XTS_KEY_LENGTH_256 (BIT(10)) 217 #define EFUSE_XTS_KEY_LENGTH_256_M (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S) 218 #define EFUSE_XTS_KEY_LENGTH_256_V 0x00000001U 219 #define EFUSE_XTS_KEY_LENGTH_256_S 10 220 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [12:11]; default: 0; 221 * Set this bit to disable usb printing. 222 */ 223 #define EFUSE_UART_PRINT_CONTROL 0x00000003U 224 #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) 225 #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U 226 #define EFUSE_UART_PRINT_CONTROL_S 11 227 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; 228 * Set this bit to force ROM code to send a resume command during SPI boot. 229 */ 230 #define EFUSE_FORCE_SEND_RESUME (BIT(13)) 231 #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) 232 #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U 233 #define EFUSE_FORCE_SEND_RESUME_S 13 234 /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [14]; default: 0; 235 * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). 236 */ 237 #define EFUSE_DIS_DOWNLOAD_MODE (BIT(14)) 238 #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) 239 #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U 240 #define EFUSE_DIS_DOWNLOAD_MODE_S 14 241 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [15]; default: 0; 242 * This bit set means disable direct_boot mode. 243 */ 244 #define EFUSE_DIS_DIRECT_BOOT (BIT(15)) 245 #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) 246 #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U 247 #define EFUSE_DIS_DIRECT_BOOT_S 15 248 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [16]; default: 0; 249 * Set this bit to enable secure UART download mode. 250 */ 251 #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(16)) 252 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) 253 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U 254 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 16 255 /** EFUSE_FLASH_TPUW : RO; bitpos: [20:17]; default: 0; 256 * Configures flash waiting time after power-up, in unit of ms. If the value is less 257 * than 15, the waiting time is the configurable value. Otherwise, the waiting time 258 * is twice the configurable value. 259 */ 260 #define EFUSE_FLASH_TPUW 0x0000000FU 261 #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) 262 #define EFUSE_FLASH_TPUW_V 0x0000000FU 263 #define EFUSE_FLASH_TPUW_S 17 264 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [21]; default: 0; 265 * The bit be set to enable secure boot. 266 */ 267 #define EFUSE_SECURE_BOOT_EN (BIT(21)) 268 #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) 269 #define EFUSE_SECURE_BOOT_EN_V 0x00000001U 270 #define EFUSE_SECURE_BOOT_EN_S 21 271 /** EFUSE_SECURE_VERSION : R; bitpos: [25:22]; default: 0; 272 * Secure version for anti-rollback 273 */ 274 #define EFUSE_SECURE_VERSION 0x0000000FU 275 #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) 276 #define EFUSE_SECURE_VERSION_V 0x0000000FU 277 #define EFUSE_SECURE_VERSION_S 22 278 /** EFUSE_CUSTOM_MAC_USED : R; bitpos: [26]; default: 0; 279 * True if MAC_CUSTOM is burned 280 */ 281 #define EFUSE_CUSTOM_MAC_USED (BIT(26)) 282 #define EFUSE_CUSTOM_MAC_USED_M (EFUSE_CUSTOM_MAC_USED_V << EFUSE_CUSTOM_MAC_USED_S) 283 #define EFUSE_CUSTOM_MAC_USED_V 0x00000001U 284 #define EFUSE_CUSTOM_MAC_USED_S 26 285 /** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [27]; default: 0; 286 * Disables check of wafer version major 287 */ 288 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(27)) 289 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) 290 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U 291 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 27 292 /** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [28]; default: 0; 293 * Disables check of blk version major 294 */ 295 #define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(28)) 296 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) 297 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U 298 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 28 299 /** EFUSE_RESERVED_0_61 : R; bitpos: [31:29]; default: 0; 300 * reserved 301 */ 302 #define EFUSE_RESERVED_0_61 0x00000007U 303 #define EFUSE_RESERVED_0_61_M (EFUSE_RESERVED_0_61_V << EFUSE_RESERVED_0_61_S) 304 #define EFUSE_RESERVED_0_61_V 0x00000007U 305 #define EFUSE_RESERVED_0_61_S 29 306 307 /** EFUSE_RD_BLK1_DATA0_REG register 308 * BLOCK1 data register 0. 309 */ 310 #define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34) 311 /** EFUSE_CUSTOM_MAC : R; bitpos: [31:0]; default: 0; 312 * Custom MAC address 313 */ 314 #define EFUSE_CUSTOM_MAC 0xFFFFFFFFU 315 #define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) 316 #define EFUSE_CUSTOM_MAC_V 0xFFFFFFFFU 317 #define EFUSE_CUSTOM_MAC_S 0 318 319 /** EFUSE_RD_BLK1_DATA1_REG register 320 * BLOCK1 data register 1. 321 */ 322 #define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38) 323 /** EFUSE_CUSTOM_MAC_1 : R; bitpos: [15:0]; default: 0; 324 * Custom MAC address 325 */ 326 #define EFUSE_CUSTOM_MAC_1 0x0000FFFFU 327 #define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) 328 #define EFUSE_CUSTOM_MAC_1_V 0x0000FFFFU 329 #define EFUSE_CUSTOM_MAC_1_S 0 330 /** EFUSE_RESERVED_1_48 : R; bitpos: [31:16]; default: 0; 331 * reserved 332 */ 333 #define EFUSE_RESERVED_1_48 0x0000FFFFU 334 #define EFUSE_RESERVED_1_48_M (EFUSE_RESERVED_1_48_V << EFUSE_RESERVED_1_48_S) 335 #define EFUSE_RESERVED_1_48_V 0x0000FFFFU 336 #define EFUSE_RESERVED_1_48_S 16 337 338 /** EFUSE_RD_BLK1_DATA2_REG register 339 * BLOCK1 data register 2. 340 */ 341 #define EFUSE_RD_BLK1_DATA2_REG (DR_REG_EFUSE_BASE + 0x3c) 342 /** EFUSE_SYSTEM_DATA2 : RO; bitpos: [23:0]; default: 0; 343 * Stores the bits [64:87] of system data. 344 */ 345 #define EFUSE_SYSTEM_DATA2 0x00FFFFFFU 346 #define EFUSE_SYSTEM_DATA2_M (EFUSE_SYSTEM_DATA2_V << EFUSE_SYSTEM_DATA2_S) 347 #define EFUSE_SYSTEM_DATA2_V 0x00FFFFFFU 348 #define EFUSE_SYSTEM_DATA2_S 0 349 350 /** EFUSE_RD_BLK2_DATA0_REG register 351 * Register 0 of BLOCK2. 352 */ 353 #define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40) 354 /** EFUSE_MAC : R; bitpos: [31:0]; default: 0; 355 * MAC address 356 */ 357 #define EFUSE_MAC 0xFFFFFFFFU 358 #define EFUSE_MAC_M (EFUSE_MAC_V << EFUSE_MAC_S) 359 #define EFUSE_MAC_V 0xFFFFFFFFU 360 #define EFUSE_MAC_S 0 361 362 /** EFUSE_RD_BLK2_DATA1_REG register 363 * Register 1 of BLOCK2. 364 */ 365 #define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44) 366 /** EFUSE_MAC_1 : R; bitpos: [15:0]; default: 0; 367 * MAC address 368 */ 369 #define EFUSE_MAC_1 0x0000FFFFU 370 #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) 371 #define EFUSE_MAC_1_V 0x0000FFFFU 372 #define EFUSE_MAC_1_S 0 373 /** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [19:16]; default: 0; 374 * WAFER_VERSION_MINOR 375 */ 376 #define EFUSE_WAFER_VERSION_MINOR 0x0000000FU 377 #define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) 378 #define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU 379 #define EFUSE_WAFER_VERSION_MINOR_S 16 380 /** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [21:20]; default: 0; 381 * WAFER_VERSION_MAJOR 382 */ 383 #define EFUSE_WAFER_VERSION_MAJOR 0x00000003U 384 #define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) 385 #define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U 386 #define EFUSE_WAFER_VERSION_MAJOR_S 20 387 /** EFUSE_PKG_VERSION : R; bitpos: [24:22]; default: 0; 388 * EFUSE_PKG_VERSION 389 */ 390 #define EFUSE_PKG_VERSION 0x00000007U 391 #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) 392 #define EFUSE_PKG_VERSION_V 0x00000007U 393 #define EFUSE_PKG_VERSION_S 22 394 /** EFUSE_BLK_VERSION_MINOR : R; bitpos: [27:25]; default: 0; 395 * Minor version of BLOCK2 396 */ 397 #define EFUSE_BLK_VERSION_MINOR 0x00000007U 398 #define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) 399 #define EFUSE_BLK_VERSION_MINOR_V 0x00000007U 400 #define EFUSE_BLK_VERSION_MINOR_S 25 401 /** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [29:28]; default: 0; 402 * Major version of BLOCK2 403 */ 404 #define EFUSE_BLK_VERSION_MAJOR 0x00000003U 405 #define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) 406 #define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U 407 #define EFUSE_BLK_VERSION_MAJOR_S 28 408 /** EFUSE_OCODE : R; bitpos: [31:30]; default: 0; 409 * OCode 410 */ 411 #define EFUSE_OCODE 0x00000003U 412 #define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) 413 #define EFUSE_OCODE_V 0x00000003U 414 #define EFUSE_OCODE_S 30 415 416 /** EFUSE_RD_BLK2_DATA2_REG register 417 * Register 2 of BLOCK2. 418 */ 419 #define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48) 420 /** EFUSE_OCODE_1 : R; bitpos: [4:0]; default: 0; 421 * OCode 422 */ 423 #define EFUSE_OCODE_1 0x0000001FU 424 #define EFUSE_OCODE_1_M (EFUSE_OCODE_1_V << EFUSE_OCODE_1_S) 425 #define EFUSE_OCODE_1_V 0x0000001FU 426 #define EFUSE_OCODE_1_S 0 427 /** EFUSE_TEMP_CALIB : R; bitpos: [13:5]; default: 0; 428 * Temperature calibration data 429 */ 430 #define EFUSE_TEMP_CALIB 0x000001FFU 431 #define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) 432 #define EFUSE_TEMP_CALIB_V 0x000001FFU 433 #define EFUSE_TEMP_CALIB_S 5 434 /** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [21:14]; default: 0; 435 * ADC1 init code at atten0 436 */ 437 #define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000000FFU 438 #define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S) 439 #define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000000FFU 440 #define EFUSE_ADC1_INIT_CODE_ATTEN0_S 14 441 /** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [26:22]; default: 0; 442 * ADC1 init code at atten3 443 */ 444 #define EFUSE_ADC1_INIT_CODE_ATTEN3 0x0000001FU 445 #define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S) 446 #define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x0000001FU 447 #define EFUSE_ADC1_INIT_CODE_ATTEN3_S 22 448 /** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:27]; default: 0; 449 * ADC1 calibration voltage at atten0 450 */ 451 #define EFUSE_ADC1_CAL_VOL_ATTEN0 0x0000001FU 452 #define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S) 453 #define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x0000001FU 454 #define EFUSE_ADC1_CAL_VOL_ATTEN0_S 27 455 456 /** EFUSE_RD_BLK2_DATA3_REG register 457 * Register 3 of BLOCK2. 458 */ 459 #define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4c) 460 /** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0; 461 * ADC1 calibration voltage at atten0 462 */ 463 #define EFUSE_ADC1_CAL_VOL_ATTEN0_1 0x00000007U 464 #define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S) 465 #define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V 0x00000007U 466 #define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S 0 467 /** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:3]; default: 0; 468 * ADC1 calibration voltage at atten3 469 */ 470 #define EFUSE_ADC1_CAL_VOL_ATTEN3 0x0000003FU 471 #define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S) 472 #define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x0000003FU 473 #define EFUSE_ADC1_CAL_VOL_ATTEN3_S 3 474 /** EFUSE_DIG_DBIAS_HVT : R; bitpos: [13:9]; default: 0; 475 * BLOCK2 digital dbias when hvt 476 */ 477 #define EFUSE_DIG_DBIAS_HVT 0x0000001FU 478 #define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) 479 #define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU 480 #define EFUSE_DIG_DBIAS_HVT_S 9 481 /** EFUSE_DIG_LDO_SLP_DBIAS2 : R; bitpos: [20:14]; default: 0; 482 * BLOCK2 DIG_LDO_DBG0_DBIAS2 483 */ 484 #define EFUSE_DIG_LDO_SLP_DBIAS2 0x0000007FU 485 #define EFUSE_DIG_LDO_SLP_DBIAS2_M (EFUSE_DIG_LDO_SLP_DBIAS2_V << EFUSE_DIG_LDO_SLP_DBIAS2_S) 486 #define EFUSE_DIG_LDO_SLP_DBIAS2_V 0x0000007FU 487 #define EFUSE_DIG_LDO_SLP_DBIAS2_S 14 488 /** EFUSE_DIG_LDO_SLP_DBIAS26 : R; bitpos: [28:21]; default: 0; 489 * BLOCK2 DIG_LDO_DBG0_DBIAS26 490 */ 491 #define EFUSE_DIG_LDO_SLP_DBIAS26 0x000000FFU 492 #define EFUSE_DIG_LDO_SLP_DBIAS26_M (EFUSE_DIG_LDO_SLP_DBIAS26_V << EFUSE_DIG_LDO_SLP_DBIAS26_S) 493 #define EFUSE_DIG_LDO_SLP_DBIAS26_V 0x000000FFU 494 #define EFUSE_DIG_LDO_SLP_DBIAS26_S 21 495 /** EFUSE_DIG_LDO_ACT_DBIAS26 : R; bitpos: [31:29]; default: 0; 496 * BLOCK2 DIG_LDO_ACT_DBIAS26 497 */ 498 #define EFUSE_DIG_LDO_ACT_DBIAS26 0x00000007U 499 #define EFUSE_DIG_LDO_ACT_DBIAS26_M (EFUSE_DIG_LDO_ACT_DBIAS26_V << EFUSE_DIG_LDO_ACT_DBIAS26_S) 500 #define EFUSE_DIG_LDO_ACT_DBIAS26_V 0x00000007U 501 #define EFUSE_DIG_LDO_ACT_DBIAS26_S 29 502 503 /** EFUSE_RD_BLK2_DATA4_REG register 504 * Register 4 of BLOCK2. 505 */ 506 #define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50) 507 /** EFUSE_DIG_LDO_ACT_DBIAS26_1 : R; bitpos: [2:0]; default: 0; 508 * BLOCK2 DIG_LDO_ACT_DBIAS26 509 */ 510 #define EFUSE_DIG_LDO_ACT_DBIAS26_1 0x00000007U 511 #define EFUSE_DIG_LDO_ACT_DBIAS26_1_M (EFUSE_DIG_LDO_ACT_DBIAS26_1_V << EFUSE_DIG_LDO_ACT_DBIAS26_1_S) 512 #define EFUSE_DIG_LDO_ACT_DBIAS26_1_V 0x00000007U 513 #define EFUSE_DIG_LDO_ACT_DBIAS26_1_S 0 514 /** EFUSE_DIG_LDO_ACT_STEPD10 : R; bitpos: [6:3]; default: 0; 515 * BLOCK2 DIG_LDO_ACT_STEPD10 516 */ 517 #define EFUSE_DIG_LDO_ACT_STEPD10 0x0000000FU 518 #define EFUSE_DIG_LDO_ACT_STEPD10_M (EFUSE_DIG_LDO_ACT_STEPD10_V << EFUSE_DIG_LDO_ACT_STEPD10_S) 519 #define EFUSE_DIG_LDO_ACT_STEPD10_V 0x0000000FU 520 #define EFUSE_DIG_LDO_ACT_STEPD10_S 3 521 /** EFUSE_RTC_LDO_SLP_DBIAS13 : R; bitpos: [13:7]; default: 0; 522 * BLOCK2 DIG_LDO_SLP_DBIAS13 523 */ 524 #define EFUSE_RTC_LDO_SLP_DBIAS13 0x0000007FU 525 #define EFUSE_RTC_LDO_SLP_DBIAS13_M (EFUSE_RTC_LDO_SLP_DBIAS13_V << EFUSE_RTC_LDO_SLP_DBIAS13_S) 526 #define EFUSE_RTC_LDO_SLP_DBIAS13_V 0x0000007FU 527 #define EFUSE_RTC_LDO_SLP_DBIAS13_S 7 528 /** EFUSE_RTC_LDO_SLP_DBIAS29 : R; bitpos: [22:14]; default: 0; 529 * BLOCK2 DIG_LDO_SLP_DBIAS29 530 */ 531 #define EFUSE_RTC_LDO_SLP_DBIAS29 0x000001FFU 532 #define EFUSE_RTC_LDO_SLP_DBIAS29_M (EFUSE_RTC_LDO_SLP_DBIAS29_V << EFUSE_RTC_LDO_SLP_DBIAS29_S) 533 #define EFUSE_RTC_LDO_SLP_DBIAS29_V 0x000001FFU 534 #define EFUSE_RTC_LDO_SLP_DBIAS29_S 14 535 /** EFUSE_RTC_LDO_SLP_DBIAS31 : R; bitpos: [28:23]; default: 0; 536 * BLOCK2 DIG_LDO_SLP_DBIAS31 537 */ 538 #define EFUSE_RTC_LDO_SLP_DBIAS31 0x0000003FU 539 #define EFUSE_RTC_LDO_SLP_DBIAS31_M (EFUSE_RTC_LDO_SLP_DBIAS31_V << EFUSE_RTC_LDO_SLP_DBIAS31_S) 540 #define EFUSE_RTC_LDO_SLP_DBIAS31_V 0x0000003FU 541 #define EFUSE_RTC_LDO_SLP_DBIAS31_S 23 542 /** EFUSE_RTC_LDO_ACT_DBIAS31 : R; bitpos: [31:29]; default: 0; 543 * BLOCK2 DIG_LDO_ACT_DBIAS31 544 */ 545 #define EFUSE_RTC_LDO_ACT_DBIAS31 0x00000007U 546 #define EFUSE_RTC_LDO_ACT_DBIAS31_M (EFUSE_RTC_LDO_ACT_DBIAS31_V << EFUSE_RTC_LDO_ACT_DBIAS31_S) 547 #define EFUSE_RTC_LDO_ACT_DBIAS31_V 0x00000007U 548 #define EFUSE_RTC_LDO_ACT_DBIAS31_S 29 549 550 /** EFUSE_RD_BLK2_DATA5_REG register 551 * Register 5 of BLOCK2. 552 */ 553 #define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54) 554 /** EFUSE_RTC_LDO_ACT_DBIAS31_1 : R; bitpos: [2:0]; default: 0; 555 * BLOCK2 DIG_LDO_ACT_DBIAS31 556 */ 557 #define EFUSE_RTC_LDO_ACT_DBIAS31_1 0x00000007U 558 #define EFUSE_RTC_LDO_ACT_DBIAS31_1_M (EFUSE_RTC_LDO_ACT_DBIAS31_1_V << EFUSE_RTC_LDO_ACT_DBIAS31_1_S) 559 #define EFUSE_RTC_LDO_ACT_DBIAS31_1_V 0x00000007U 560 #define EFUSE_RTC_LDO_ACT_DBIAS31_1_S 0 561 /** EFUSE_RTC_LDO_ACT_DBIAS13 : R; bitpos: [10:3]; default: 0; 562 * BLOCK2 DIG_LDO_ACT_DBIAS13 563 */ 564 #define EFUSE_RTC_LDO_ACT_DBIAS13 0x000000FFU 565 #define EFUSE_RTC_LDO_ACT_DBIAS13_M (EFUSE_RTC_LDO_ACT_DBIAS13_V << EFUSE_RTC_LDO_ACT_DBIAS13_S) 566 #define EFUSE_RTC_LDO_ACT_DBIAS13_V 0x000000FFU 567 #define EFUSE_RTC_LDO_ACT_DBIAS13_S 3 568 /** EFUSE_RESERVED_2_171 : R; bitpos: [31:11]; default: 0; 569 * reserved 570 */ 571 #define EFUSE_RESERVED_2_171 0x001FFFFFU 572 #define EFUSE_RESERVED_2_171_M (EFUSE_RESERVED_2_171_V << EFUSE_RESERVED_2_171_S) 573 #define EFUSE_RESERVED_2_171_V 0x001FFFFFU 574 #define EFUSE_RESERVED_2_171_S 11 575 576 /** EFUSE_RD_BLK2_DATA6_REG register 577 * Register 6 of BLOCK2. 578 */ 579 #define EFUSE_RD_BLK2_DATA6_REG (DR_REG_EFUSE_BASE + 0x58) 580 /** EFUSE_ADC_CALIBRATION_3 : RO; bitpos: [10:0]; default: 0; 581 * Store the bit [86:96] of ADC calibration data. 582 */ 583 #define EFUSE_ADC_CALIBRATION_3 0x000007FFU 584 #define EFUSE_ADC_CALIBRATION_3_M (EFUSE_ADC_CALIBRATION_3_V << EFUSE_ADC_CALIBRATION_3_S) 585 #define EFUSE_ADC_CALIBRATION_3_V 0x000007FFU 586 #define EFUSE_ADC_CALIBRATION_3_S 0 587 /** EFUSE_BLK2_RESERVED_DATA_0 : RO; bitpos: [31:11]; default: 0; 588 * Store the bit [0:20] of block2 reserved data. 589 */ 590 #define EFUSE_BLK2_RESERVED_DATA_0 0x001FFFFFU 591 #define EFUSE_BLK2_RESERVED_DATA_0_M (EFUSE_BLK2_RESERVED_DATA_0_V << EFUSE_BLK2_RESERVED_DATA_0_S) 592 #define EFUSE_BLK2_RESERVED_DATA_0_V 0x001FFFFFU 593 #define EFUSE_BLK2_RESERVED_DATA_0_S 11 594 595 /** EFUSE_RD_BLK2_DATA7_REG register 596 * Register 7 of BLOCK2. 597 */ 598 #define EFUSE_RD_BLK2_DATA7_REG (DR_REG_EFUSE_BASE + 0x5c) 599 /** EFUSE_BLK2_RESERVED_DATA_1 : RO; bitpos: [31:0]; default: 0; 600 * Store the bit [21:52] of block2 reserved data. 601 */ 602 #define EFUSE_BLK2_RESERVED_DATA_1 0xFFFFFFFFU 603 #define EFUSE_BLK2_RESERVED_DATA_1_M (EFUSE_BLK2_RESERVED_DATA_1_V << EFUSE_BLK2_RESERVED_DATA_1_S) 604 #define EFUSE_BLK2_RESERVED_DATA_1_V 0xFFFFFFFFU 605 #define EFUSE_BLK2_RESERVED_DATA_1_S 0 606 607 /** EFUSE_RD_BLK3_DATA0_REG register 608 * Register 0 of BLOCK3. 609 */ 610 #define EFUSE_RD_BLK3_DATA0_REG (DR_REG_EFUSE_BASE + 0x60) 611 /** EFUSE_BLK3_DATA0 : RO; bitpos: [31:0]; default: 0; 612 * Store the first 32-bit of Block3. 613 */ 614 #define EFUSE_BLK3_DATA0 0xFFFFFFFFU 615 #define EFUSE_BLK3_DATA0_M (EFUSE_BLK3_DATA0_V << EFUSE_BLK3_DATA0_S) 616 #define EFUSE_BLK3_DATA0_V 0xFFFFFFFFU 617 #define EFUSE_BLK3_DATA0_S 0 618 619 /** EFUSE_RD_BLK3_DATA1_REG register 620 * Register 1 of BLOCK3. 621 */ 622 #define EFUSE_RD_BLK3_DATA1_REG (DR_REG_EFUSE_BASE + 0x64) 623 /** EFUSE_BLK3_DATA1 : RO; bitpos: [31:0]; default: 0; 624 * Store the second 32-bit of Block3. 625 */ 626 #define EFUSE_BLK3_DATA1 0xFFFFFFFFU 627 #define EFUSE_BLK3_DATA1_M (EFUSE_BLK3_DATA1_V << EFUSE_BLK3_DATA1_S) 628 #define EFUSE_BLK3_DATA1_V 0xFFFFFFFFU 629 #define EFUSE_BLK3_DATA1_S 0 630 631 /** EFUSE_RD_BLK3_DATA2_REG register 632 * Register 2 of BLOCK3. 633 */ 634 #define EFUSE_RD_BLK3_DATA2_REG (DR_REG_EFUSE_BASE + 0x68) 635 /** EFUSE_BLK3_DATA2 : RO; bitpos: [31:0]; default: 0; 636 * Store the third 32-bit of Block3. 637 */ 638 #define EFUSE_BLK3_DATA2 0xFFFFFFFFU 639 #define EFUSE_BLK3_DATA2_M (EFUSE_BLK3_DATA2_V << EFUSE_BLK3_DATA2_S) 640 #define EFUSE_BLK3_DATA2_V 0xFFFFFFFFU 641 #define EFUSE_BLK3_DATA2_S 0 642 643 /** EFUSE_RD_BLK3_DATA3_REG register 644 * Register 3 of BLOCK3. 645 */ 646 #define EFUSE_RD_BLK3_DATA3_REG (DR_REG_EFUSE_BASE + 0x6c) 647 /** EFUSE_BLK3_DATA3 : RO; bitpos: [31:0]; default: 0; 648 * Store the fourth 32-bit of Block3. 649 */ 650 #define EFUSE_BLK3_DATA3 0xFFFFFFFFU 651 #define EFUSE_BLK3_DATA3_M (EFUSE_BLK3_DATA3_V << EFUSE_BLK3_DATA3_S) 652 #define EFUSE_BLK3_DATA3_V 0xFFFFFFFFU 653 #define EFUSE_BLK3_DATA3_S 0 654 655 /** EFUSE_RD_BLK3_DATA4_REG register 656 * Register 4 of BLOCK3. 657 */ 658 #define EFUSE_RD_BLK3_DATA4_REG (DR_REG_EFUSE_BASE + 0x70) 659 /** EFUSE_BLK3_DATA4 : RO; bitpos: [31:0]; default: 0; 660 * Store the fifth 32-bit of Block3. 661 */ 662 #define EFUSE_BLK3_DATA4 0xFFFFFFFFU 663 #define EFUSE_BLK3_DATA4_M (EFUSE_BLK3_DATA4_V << EFUSE_BLK3_DATA4_S) 664 #define EFUSE_BLK3_DATA4_V 0xFFFFFFFFU 665 #define EFUSE_BLK3_DATA4_S 0 666 667 /** EFUSE_RD_BLK3_DATA5_REG register 668 * Register 5 of BLOCK3. 669 */ 670 #define EFUSE_RD_BLK3_DATA5_REG (DR_REG_EFUSE_BASE + 0x74) 671 /** EFUSE_BLK3_DATA5 : RO; bitpos: [31:0]; default: 0; 672 * Store the sixth 32-bit of Block3. 673 */ 674 #define EFUSE_BLK3_DATA5 0xFFFFFFFFU 675 #define EFUSE_BLK3_DATA5_M (EFUSE_BLK3_DATA5_V << EFUSE_BLK3_DATA5_S) 676 #define EFUSE_BLK3_DATA5_V 0xFFFFFFFFU 677 #define EFUSE_BLK3_DATA5_S 0 678 679 /** EFUSE_RD_BLK3_DATA6_REG register 680 * Register 6 of BLOCK3. 681 */ 682 #define EFUSE_RD_BLK3_DATA6_REG (DR_REG_EFUSE_BASE + 0x78) 683 /** EFUSE_BLK3_DATA6 : RO; bitpos: [31:0]; default: 0; 684 * Store the seventh 32-bit of Block3. 685 */ 686 #define EFUSE_BLK3_DATA6 0xFFFFFFFFU 687 #define EFUSE_BLK3_DATA6_M (EFUSE_BLK3_DATA6_V << EFUSE_BLK3_DATA6_S) 688 #define EFUSE_BLK3_DATA6_V 0xFFFFFFFFU 689 #define EFUSE_BLK3_DATA6_S 0 690 691 /** EFUSE_RD_BLK3_DATA7_REG register 692 * Register 7 of BLOCK3. 693 */ 694 #define EFUSE_RD_BLK3_DATA7_REG (DR_REG_EFUSE_BASE + 0x7c) 695 /** EFUSE_BLK3_DATA7 : RO; bitpos: [31:0]; default: 0; 696 * Store the eighth 32-bit of Block3. 697 */ 698 #define EFUSE_BLK3_DATA7 0xFFFFFFFFU 699 #define EFUSE_BLK3_DATA7_M (EFUSE_BLK3_DATA7_V << EFUSE_BLK3_DATA7_S) 700 #define EFUSE_BLK3_DATA7_V 0xFFFFFFFFU 701 #define EFUSE_BLK3_DATA7_S 0 702 703 /** EFUSE_RD_REPEAT_ERR_REG register 704 * Programming error record register 0 of BLOCK0. 705 */ 706 #define EFUSE_RD_REPEAT_ERR_REG (DR_REG_EFUSE_BASE + 0x80) 707 /** EFUSE_RD_DIS_ERR : RO; bitpos: [1:0]; default: 0; 708 * If any bit in RD_DIS is 1, then it indicates a programming error. 709 */ 710 #define EFUSE_RD_DIS_ERR 0x00000003U 711 #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) 712 #define EFUSE_RD_DIS_ERR_V 0x00000003U 713 #define EFUSE_RD_DIS_ERR_S 0 714 /** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [3:2]; default: 0; 715 * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. 716 */ 717 #define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U 718 #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) 719 #define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U 720 #define EFUSE_WDT_DELAY_SEL_ERR_S 2 721 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [4]; default: 0; 722 * If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error. 723 */ 724 #define EFUSE_DIS_PAD_JTAG_ERR (BIT(4)) 725 #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) 726 #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U 727 #define EFUSE_DIS_PAD_JTAG_ERR_S 4 728 /** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [5]; default: 0; 729 * If any bit in this filed is 1, then it indicates a programming error. 730 */ 731 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(5)) 732 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) 733 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U 734 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 5 735 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [6]; default: 0; 736 * If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming 737 * error. 738 */ 739 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(6)) 740 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) 741 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U 742 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 6 743 /** EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR : RO; bitpos: [9:7]; default: 0; 744 * If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming 745 * error. 746 */ 747 #define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR 0x00000007U 748 #define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S) 749 #define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V 0x00000007U 750 #define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S 7 751 /** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [10]; default: 0; 752 * If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error. 753 */ 754 #define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(10)) 755 #define EFUSE_XTS_KEY_LENGTH_256_ERR_M (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S) 756 #define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x00000001U 757 #define EFUSE_XTS_KEY_LENGTH_256_ERR_S 10 758 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [12:11]; default: 0; 759 * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. 760 */ 761 #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U 762 #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) 763 #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U 764 #define EFUSE_UART_PRINT_CONTROL_ERR_S 11 765 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; 766 * If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error. 767 */ 768 #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) 769 #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) 770 #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U 771 #define EFUSE_FORCE_SEND_RESUME_ERR_S 13 772 /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [14]; default: 0; 773 * If any bit in this filed is 1, then it indicates a programming error. 774 */ 775 #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(14)) 776 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) 777 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U 778 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 14 779 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [15]; default: 0; 780 * If any bit in this filed is 1, then it indicates a programming error. 781 */ 782 #define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(15)) 783 #define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) 784 #define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U 785 #define EFUSE_DIS_DIRECT_BOOT_ERR_S 15 786 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [16]; default: 0; 787 * If any bit in this filed is 1, then it indicates a programming error. 788 */ 789 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(16)) 790 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) 791 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U 792 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 16 793 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [20:17]; default: 0; 794 * If any bit in this filed is 1, then it indicates a programming error. 795 */ 796 #define EFUSE_FLASH_TPUW_ERR 0x0000000FU 797 #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) 798 #define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU 799 #define EFUSE_FLASH_TPUW_ERR_S 17 800 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [21]; default: 0; 801 * If any bit in this filed is 1, then it indicates a programming error. 802 */ 803 #define EFUSE_SECURE_BOOT_EN_ERR (BIT(21)) 804 #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) 805 #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U 806 #define EFUSE_SECURE_BOOT_EN_ERR_S 21 807 /** EFUSE_RPT4_RESERVED_ERR : RO; bitpos: [31:22]; default: 0; 808 * Reserved. 809 */ 810 #define EFUSE_RPT4_RESERVED_ERR 0x000003FFU 811 #define EFUSE_RPT4_RESERVED_ERR_M (EFUSE_RPT4_RESERVED_ERR_V << EFUSE_RPT4_RESERVED_ERR_S) 812 #define EFUSE_RPT4_RESERVED_ERR_V 0x000003FFU 813 #define EFUSE_RPT4_RESERVED_ERR_S 22 814 815 /** EFUSE_RD_RS_ERR_REG register 816 * Programming error record register 0 of BLOCK1-10. 817 */ 818 #define EFUSE_RD_RS_ERR_REG (DR_REG_EFUSE_BASE + 0x84) 819 /** EFUSE_BLK1_ERR_NUM : RO; bitpos: [2:0]; default: 0; 820 * The value of this signal means the number of error bytes in block1. 821 */ 822 #define EFUSE_BLK1_ERR_NUM 0x00000007U 823 #define EFUSE_BLK1_ERR_NUM_M (EFUSE_BLK1_ERR_NUM_V << EFUSE_BLK1_ERR_NUM_S) 824 #define EFUSE_BLK1_ERR_NUM_V 0x00000007U 825 #define EFUSE_BLK1_ERR_NUM_S 0 826 /** EFUSE_BLK1_FAIL : RO; bitpos: [3]; default: 0; 827 * 0: Means no failure and that the data of block1 is reliable 1: Means that 828 * programming user data failed and the number of error bytes is over 6. 829 */ 830 #define EFUSE_BLK1_FAIL (BIT(3)) 831 #define EFUSE_BLK1_FAIL_M (EFUSE_BLK1_FAIL_V << EFUSE_BLK1_FAIL_S) 832 #define EFUSE_BLK1_FAIL_V 0x00000001U 833 #define EFUSE_BLK1_FAIL_S 3 834 /** EFUSE_BLK2_ERR_NUM : RO; bitpos: [6:4]; default: 0; 835 * The value of this signal means the number of error bytes in block2. 836 */ 837 #define EFUSE_BLK2_ERR_NUM 0x00000007U 838 #define EFUSE_BLK2_ERR_NUM_M (EFUSE_BLK2_ERR_NUM_V << EFUSE_BLK2_ERR_NUM_S) 839 #define EFUSE_BLK2_ERR_NUM_V 0x00000007U 840 #define EFUSE_BLK2_ERR_NUM_S 4 841 /** EFUSE_BLK2_FAIL : RO; bitpos: [7]; default: 0; 842 * 0: Means no failure and that the data of block2 is reliable 1: Means that 843 * programming user data failed and the number of error bytes is over 6. 844 */ 845 #define EFUSE_BLK2_FAIL (BIT(7)) 846 #define EFUSE_BLK2_FAIL_M (EFUSE_BLK2_FAIL_V << EFUSE_BLK2_FAIL_S) 847 #define EFUSE_BLK2_FAIL_V 0x00000001U 848 #define EFUSE_BLK2_FAIL_S 7 849 /** EFUSE_BLK3_ERR_NUM : RO; bitpos: [10:8]; default: 0; 850 * The value of this signal means the number of error bytes in block3. 851 */ 852 #define EFUSE_BLK3_ERR_NUM 0x00000007U 853 #define EFUSE_BLK3_ERR_NUM_M (EFUSE_BLK3_ERR_NUM_V << EFUSE_BLK3_ERR_NUM_S) 854 #define EFUSE_BLK3_ERR_NUM_V 0x00000007U 855 #define EFUSE_BLK3_ERR_NUM_S 8 856 /** EFUSE_BLK3_FAIL : RO; bitpos: [11]; default: 0; 857 * 0: Means no failure and that the block3 data is reliable 1: Means that programming 858 * user data failed and the number of error bytes is over 6. 859 */ 860 #define EFUSE_BLK3_FAIL (BIT(11)) 861 #define EFUSE_BLK3_FAIL_M (EFUSE_BLK3_FAIL_V << EFUSE_BLK3_FAIL_S) 862 #define EFUSE_BLK3_FAIL_V 0x00000001U 863 #define EFUSE_BLK3_FAIL_S 11 864 865 /** EFUSE_CLK_REG register 866 * eFuse clcok configuration register. 867 */ 868 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x88) 869 /** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; 870 * Set this bit to force eFuse SRAM into power-saving mode. 871 */ 872 #define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) 873 #define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) 874 #define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U 875 #define EFUSE_EFUSE_MEM_FORCE_PD_S 0 876 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; 877 * Set this bit and force to activate clock signal of eFuse SRAM. 878 */ 879 #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) 880 #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) 881 #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U 882 #define EFUSE_MEM_CLK_FORCE_ON_S 1 883 /** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; 884 * Set this bit to force eFuse SRAM into working mode. 885 */ 886 #define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) 887 #define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) 888 #define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U 889 #define EFUSE_EFUSE_MEM_FORCE_PU_S 2 890 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; 891 * Set this bit and force to enable clock signal of eFuse memory. 892 */ 893 #define EFUSE_CLK_EN (BIT(16)) 894 #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) 895 #define EFUSE_CLK_EN_V 0x00000001U 896 #define EFUSE_CLK_EN_S 16 897 898 /** EFUSE_CONF_REG register 899 * eFuse operation mode configuraiton register 900 */ 901 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8c) 902 /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; 903 * 0x5A5A: Operate programming command 0x5AA5: Operate read command. 904 */ 905 #define EFUSE_OP_CODE 0x0000FFFFU 906 #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) 907 #define EFUSE_OP_CODE_V 0x0000FFFFU 908 #define EFUSE_OP_CODE_S 0 909 910 /** EFUSE_STATUS_REG register 911 * eFuse status register. 912 */ 913 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x90) 914 /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; 915 * Indicates the state of the eFuse state machine. 916 */ 917 #define EFUSE_STATE 0x0000000FU 918 #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) 919 #define EFUSE_STATE_V 0x0000000FU 920 #define EFUSE_STATE_S 0 921 /** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; 922 * The value of OTP_LOAD_SW. 923 */ 924 #define EFUSE_OTP_LOAD_SW (BIT(4)) 925 #define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) 926 #define EFUSE_OTP_LOAD_SW_V 0x00000001U 927 #define EFUSE_OTP_LOAD_SW_S 4 928 /** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; 929 * The value of OTP_VDDQ_C_SYNC2. 930 */ 931 #define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) 932 #define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) 933 #define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U 934 #define EFUSE_OTP_VDDQ_C_SYNC2_S 5 935 /** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; 936 * The value of OTP_STROBE_SW. 937 */ 938 #define EFUSE_OTP_STROBE_SW (BIT(6)) 939 #define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) 940 #define EFUSE_OTP_STROBE_SW_V 0x00000001U 941 #define EFUSE_OTP_STROBE_SW_S 6 942 /** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; 943 * The value of OTP_CSB_SW. 944 */ 945 #define EFUSE_OTP_CSB_SW (BIT(7)) 946 #define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) 947 #define EFUSE_OTP_CSB_SW_V 0x00000001U 948 #define EFUSE_OTP_CSB_SW_S 7 949 /** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; 950 * The value of OTP_PGENB_SW. 951 */ 952 #define EFUSE_OTP_PGENB_SW (BIT(8)) 953 #define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) 954 #define EFUSE_OTP_PGENB_SW_V 0x00000001U 955 #define EFUSE_OTP_PGENB_SW_S 8 956 /** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; 957 * The value of OTP_VDDQ_IS_SW. 958 */ 959 #define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) 960 #define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) 961 #define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U 962 #define EFUSE_OTP_VDDQ_IS_SW_S 9 963 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [15:10]; default: 0; 964 * Record the number of bit '1' in BLOCK0. 965 */ 966 #define EFUSE_BLK0_VALID_BIT_CNT 0x0000003FU 967 #define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) 968 #define EFUSE_BLK0_VALID_BIT_CNT_V 0x0000003FU 969 #define EFUSE_BLK0_VALID_BIT_CNT_S 10 970 971 /** EFUSE_CMD_REG register 972 * eFuse command register. 973 */ 974 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x94) 975 /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; 976 * Set this bit to send read command. 977 */ 978 #define EFUSE_READ_CMD (BIT(0)) 979 #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) 980 #define EFUSE_READ_CMD_V 0x00000001U 981 #define EFUSE_READ_CMD_S 0 982 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; 983 * Set this bit to send programming command. 984 */ 985 #define EFUSE_PGM_CMD (BIT(1)) 986 #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) 987 #define EFUSE_PGM_CMD_V 0x00000001U 988 #define EFUSE_PGM_CMD_S 1 989 /** EFUSE_BLK_NUM : R/W; bitpos: [3:2]; default: 0; 990 * The serial number of the block to be programmed. Value 0-3 corresponds to block 991 * number 0-3, respectively. 992 */ 993 #define EFUSE_BLK_NUM 0x00000003U 994 #define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) 995 #define EFUSE_BLK_NUM_V 0x00000003U 996 #define EFUSE_BLK_NUM_S 2 997 998 /** EFUSE_INT_RAW_REG register 999 * eFuse raw interrupt register. 1000 */ 1001 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x98) 1002 /** EFUSE_READ_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; 1003 * The raw bit signal for read_done interrupt. 1004 */ 1005 #define EFUSE_READ_DONE_INT_RAW (BIT(0)) 1006 #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) 1007 #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U 1008 #define EFUSE_READ_DONE_INT_RAW_S 0 1009 /** EFUSE_PGM_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; 1010 * The raw bit signal for pgm_done interrupt. 1011 */ 1012 #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) 1013 #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) 1014 #define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U 1015 #define EFUSE_PGM_DONE_INT_RAW_S 1 1016 1017 /** EFUSE_INT_ST_REG register 1018 * eFuse interrupt status register. 1019 */ 1020 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x9c) 1021 /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; 1022 * The status signal for read_done interrupt. 1023 */ 1024 #define EFUSE_READ_DONE_INT_ST (BIT(0)) 1025 #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) 1026 #define EFUSE_READ_DONE_INT_ST_V 0x00000001U 1027 #define EFUSE_READ_DONE_INT_ST_S 0 1028 /** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; 1029 * The status signal for pgm_done interrupt. 1030 */ 1031 #define EFUSE_PGM_DONE_INT_ST (BIT(1)) 1032 #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) 1033 #define EFUSE_PGM_DONE_INT_ST_V 0x00000001U 1034 #define EFUSE_PGM_DONE_INT_ST_S 1 1035 1036 /** EFUSE_INT_ENA_REG register 1037 * eFuse interrupt enable register. 1038 */ 1039 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x100) 1040 /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; 1041 * The enable signal for read_done interrupt. 1042 */ 1043 #define EFUSE_READ_DONE_INT_ENA (BIT(0)) 1044 #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) 1045 #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U 1046 #define EFUSE_READ_DONE_INT_ENA_S 0 1047 /** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; 1048 * The enable signal for pgm_done interrupt. 1049 */ 1050 #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) 1051 #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) 1052 #define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U 1053 #define EFUSE_PGM_DONE_INT_ENA_S 1 1054 1055 /** EFUSE_INT_CLR_REG register 1056 * eFuse interrupt clear register. 1057 */ 1058 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x104) 1059 /** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; 1060 * The clear signal for read_done interrupt. 1061 */ 1062 #define EFUSE_READ_DONE_INT_CLR (BIT(0)) 1063 #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) 1064 #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U 1065 #define EFUSE_READ_DONE_INT_CLR_S 0 1066 /** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; 1067 * The clear signal for pgm_done interrupt. 1068 */ 1069 #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) 1070 #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) 1071 #define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U 1072 #define EFUSE_PGM_DONE_INT_CLR_S 1 1073 1074 /** EFUSE_DAC_CONF_REG register 1075 * Controls the eFuse programming voltage. 1076 */ 1077 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x108) 1078 /** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; 1079 * Controls the division factor of the rising clock of the programming voltage. 1080 */ 1081 #define EFUSE_DAC_CLK_DIV 0x000000FFU 1082 #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) 1083 #define EFUSE_DAC_CLK_DIV_V 0x000000FFU 1084 #define EFUSE_DAC_CLK_DIV_S 0 1085 /** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; 1086 * Don't care. 1087 */ 1088 #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) 1089 #define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) 1090 #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U 1091 #define EFUSE_DAC_CLK_PAD_SEL_S 8 1092 /** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; 1093 * Controls the rising period of the programming voltage. 1094 */ 1095 #define EFUSE_DAC_NUM 0x000000FFU 1096 #define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) 1097 #define EFUSE_DAC_NUM_V 0x000000FFU 1098 #define EFUSE_DAC_NUM_S 9 1099 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; 1100 * Reduces the power supply of the programming voltage. 1101 */ 1102 #define EFUSE_OE_CLR (BIT(17)) 1103 #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) 1104 #define EFUSE_OE_CLR_V 0x00000001U 1105 #define EFUSE_OE_CLR_S 17 1106 1107 /** EFUSE_RD_TIM_CONF_REG register 1108 * Configures read timing parameters. 1109 */ 1110 #define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x10c) 1111 /** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; 1112 * Configures hold time for efuse read. 1113 */ 1114 #define EFUSE_THR_A 0x000000FFU 1115 #define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) 1116 #define EFUSE_THR_A_V 0x000000FFU 1117 #define EFUSE_THR_A_S 0 1118 /** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; 1119 * Configures pulse time for efuse read. 1120 */ 1121 #define EFUSE_TRD 0x000000FFU 1122 #define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) 1123 #define EFUSE_TRD_V 0x000000FFU 1124 #define EFUSE_TRD_S 8 1125 /** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; 1126 * Configures setup time for efuse read. 1127 */ 1128 #define EFUSE_TSUR_A 0x000000FFU 1129 #define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) 1130 #define EFUSE_TSUR_A_V 0x000000FFU 1131 #define EFUSE_TSUR_A_S 16 1132 /** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; 1133 * Configures the initial read time of eFuse. 1134 */ 1135 #define EFUSE_READ_INIT_NUM 0x000000FFU 1136 #define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) 1137 #define EFUSE_READ_INIT_NUM_V 0x000000FFU 1138 #define EFUSE_READ_INIT_NUM_S 24 1139 1140 /** EFUSE_WR_TIM_CONF0_REG register 1141 * Configurarion register 0 of eFuse programming timing parameters. 1142 */ 1143 #define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x110) 1144 /** EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; 1145 * Configures hold time for efuse program. 1146 */ 1147 #define EFUSE_THP_A 0x000000FFU 1148 #define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) 1149 #define EFUSE_THP_A_V 0x000000FFU 1150 #define EFUSE_THP_A_S 0 1151 /** EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; 1152 * Configures pulse time for burning '0' bit. 1153 */ 1154 #define EFUSE_TPGM_INACTIVE 0x000000FFU 1155 #define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) 1156 #define EFUSE_TPGM_INACTIVE_V 0x000000FFU 1157 #define EFUSE_TPGM_INACTIVE_S 8 1158 /** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; 1159 * Configures pulse time for burning '1' bit. 1160 */ 1161 #define EFUSE_TPGM 0x0000FFFFU 1162 #define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) 1163 #define EFUSE_TPGM_V 0x0000FFFFU 1164 #define EFUSE_TPGM_S 16 1165 1166 /** EFUSE_WR_TIM_CONF1_REG register 1167 * Configurarion register 1 of eFuse programming timing parameters. 1168 */ 1169 #define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x114) 1170 /** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; 1171 * Configures setup time for efuse program. 1172 */ 1173 #define EFUSE_TSUP_A 0x000000FFU 1174 #define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) 1175 #define EFUSE_TSUP_A_V 0x000000FFU 1176 #define EFUSE_TSUP_A_S 0 1177 /** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288; 1178 * Configures the power up time for VDDQ. 1179 */ 1180 #define EFUSE_PWR_ON_NUM 0x0000FFFFU 1181 #define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) 1182 #define EFUSE_PWR_ON_NUM_V 0x0000FFFFU 1183 #define EFUSE_PWR_ON_NUM_S 8 1184 1185 /** EFUSE_WR_TIM_CONF2_REG register 1186 * Configurarion register 2 of eFuse programming timing parameters. 1187 */ 1188 #define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x118) 1189 /** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; 1190 * Configures the power outage time for VDDQ. 1191 */ 1192 #define EFUSE_PWR_OFF_NUM 0x0000FFFFU 1193 #define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) 1194 #define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU 1195 #define EFUSE_PWR_OFF_NUM_S 0 1196 1197 /** EFUSE_DATE_REG register 1198 * eFuse version register. 1199 */ 1200 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) 1201 /** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34636176; 1202 * Stores eFuse version. 1203 */ 1204 #define EFUSE_DATE 0x0FFFFFFFU 1205 #define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) 1206 #define EFUSE_DATE_V 0x0FFFFFFFU 1207 #define EFUSE_DATE_S 0 1208 1209 #ifdef __cplusplus 1210 } 1211 #endif 1212
