1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #include "efuse_defs.h" 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** EFUSE_PGM_DATA0_REG register 16 * Register 0 that stores data to be programmed. 17 */ 18 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) 19 /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; 20 * The content of the 0th 32-bit data to be programmed. 21 */ 22 #define EFUSE_PGM_DATA_0 0xFFFFFFFFU 23 #define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) 24 #define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU 25 #define EFUSE_PGM_DATA_0_S 0 26 27 /** EFUSE_PGM_DATA1_REG register 28 * Register 1 that stores data to be programmed. 29 */ 30 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) 31 /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; 32 * The content of the 1st 32-bit data to be programmed. 33 */ 34 #define EFUSE_PGM_DATA_1 0xFFFFFFFFU 35 #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) 36 #define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU 37 #define EFUSE_PGM_DATA_1_S 0 38 39 /** EFUSE_PGM_DATA2_REG register 40 * Register 2 that stores data to be programmed. 41 */ 42 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) 43 /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; 44 * The content of the 2nd 32-bit data to be programmed. 45 */ 46 #define EFUSE_PGM_DATA_2 0xFFFFFFFFU 47 #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) 48 #define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU 49 #define EFUSE_PGM_DATA_2_S 0 50 51 /** EFUSE_PGM_DATA3_REG register 52 * Register 3 that stores data to be programmed. 53 */ 54 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) 55 /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; 56 * The content of the 3rd 32-bit data to be programmed. 57 */ 58 #define EFUSE_PGM_DATA_3 0xFFFFFFFFU 59 #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) 60 #define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU 61 #define EFUSE_PGM_DATA_3_S 0 62 63 /** EFUSE_PGM_DATA4_REG register 64 * Register 4 that stores data to be programmed. 65 */ 66 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) 67 /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; 68 * The content of the 4th 32-bit data to be programmed. 69 */ 70 #define EFUSE_PGM_DATA_4 0xFFFFFFFFU 71 #define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) 72 #define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU 73 #define EFUSE_PGM_DATA_4_S 0 74 75 /** EFUSE_PGM_DATA5_REG register 76 * Register 5 that stores data to be programmed. 77 */ 78 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) 79 /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; 80 * The content of the 5th 32-bit data to be programmed. 81 */ 82 #define EFUSE_PGM_DATA_5 0xFFFFFFFFU 83 #define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) 84 #define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU 85 #define EFUSE_PGM_DATA_5_S 0 86 87 /** EFUSE_PGM_DATA6_REG register 88 * Register 6 that stores data to be programmed. 89 */ 90 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) 91 /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; 92 * The content of the 6th 32-bit data to be programmed. 93 */ 94 #define EFUSE_PGM_DATA_6 0xFFFFFFFFU 95 #define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) 96 #define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU 97 #define EFUSE_PGM_DATA_6_S 0 98 99 /** EFUSE_PGM_DATA7_REG register 100 * Register 7 that stores data to be programmed. 101 */ 102 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) 103 /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; 104 * The content of the 7th 32-bit data to be programmed. 105 */ 106 #define EFUSE_PGM_DATA_7 0xFFFFFFFFU 107 #define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) 108 #define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU 109 #define EFUSE_PGM_DATA_7_S 0 110 111 /** EFUSE_PGM_CHECK_VALUE0_REG register 112 * Register 0 that stores the RS code to be programmed. 113 */ 114 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) 115 /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; 116 * The content of the 0th 32-bit RS code to be programmed. 117 */ 118 #define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU 119 #define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) 120 #define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU 121 #define EFUSE_PGM_RS_DATA_0_S 0 122 123 /** EFUSE_PGM_CHECK_VALUE1_REG register 124 * Register 1 that stores the RS code to be programmed. 125 */ 126 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) 127 /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; 128 * The content of the 1st 32-bit RS code to be programmed. 129 */ 130 #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU 131 #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) 132 #define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU 133 #define EFUSE_PGM_RS_DATA_1_S 0 134 135 /** EFUSE_PGM_CHECK_VALUE2_REG register 136 * Register 2 that stores the RS code to be programmed. 137 */ 138 #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) 139 /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; 140 * The content of the 2nd 32-bit RS code to be programmed. 141 */ 142 #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU 143 #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) 144 #define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU 145 #define EFUSE_PGM_RS_DATA_2_S 0 146 147 /** EFUSE_RD_WR_DIS_REG register 148 * BLOCK0 data register 0. 149 */ 150 #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) 151 /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; 152 * Disable programming of individual eFuses. 153 */ 154 #define EFUSE_WR_DIS 0xFFFFFFFFU 155 #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) 156 #define EFUSE_WR_DIS_V 0xFFFFFFFFU 157 #define EFUSE_WR_DIS_S 0 158 159 /** EFUSE_RD_REPEAT_DATA0_REG register 160 * BLOCK0 data register 1. 161 */ 162 #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) 163 /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; 164 * Set this bit to disable reading from BlOCK4-10. 165 */ 166 #define EFUSE_RD_DIS 0x0000007FU 167 #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) 168 #define EFUSE_RD_DIS_V 0x0000007FU 169 #define EFUSE_RD_DIS_S 0 170 /** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; 171 * Set this bit to disable boot from RTC RAM. 172 */ 173 #define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) 174 #define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) 175 #define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001U 176 #define EFUSE_DIS_RTC_RAM_BOOT_S 7 177 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; 178 * Set this bit to disable Icache. 179 */ 180 #define EFUSE_DIS_ICACHE (BIT(8)) 181 #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) 182 #define EFUSE_DIS_ICACHE_V 0x00000001U 183 #define EFUSE_DIS_ICACHE_S 8 184 /** EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; 185 * Set this bit to disable Dcache. 186 */ 187 #define EFUSE_DIS_DCACHE (BIT(9)) 188 #define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) 189 #define EFUSE_DIS_DCACHE_V 0x00000001U 190 #define EFUSE_DIS_DCACHE_S 9 191 /** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; 192 * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 193 * 7). 194 */ 195 #define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) 196 #define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) 197 #define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U 198 #define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 199 /** EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; 200 * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 201 * 7). 202 */ 203 #define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) 204 #define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) 205 #define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001U 206 #define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 207 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; 208 * Set this bit to disable the function that forces chip into download mode. 209 */ 210 #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) 211 #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) 212 #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U 213 #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 214 /** EFUSE_DIS_USB_OTG : RO; bitpos: [13]; default: 0; 215 * Set this bit to disable USB function. 216 */ 217 #define EFUSE_DIS_USB_OTG (BIT(13)) 218 #define EFUSE_DIS_USB_OTG_M (EFUSE_DIS_USB_OTG_V << EFUSE_DIS_USB_OTG_S) 219 #define EFUSE_DIS_USB_OTG_V 0x00000001U 220 #define EFUSE_DIS_USB_OTG_S 13 221 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; 222 * Set this bit to disable CAN function. 223 */ 224 #define EFUSE_DIS_TWAI (BIT(14)) 225 #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) 226 #define EFUSE_DIS_TWAI_V 0x00000001U 227 #define EFUSE_DIS_TWAI_S 14 228 /** EFUSE_DIS_APP_CPU : RO; bitpos: [15]; default: 0; 229 * Disable app cpu. 230 */ 231 #define EFUSE_DIS_APP_CPU (BIT(15)) 232 #define EFUSE_DIS_APP_CPU_M (EFUSE_DIS_APP_CPU_V << EFUSE_DIS_APP_CPU_S) 233 #define EFUSE_DIS_APP_CPU_V 0x00000001U 234 #define EFUSE_DIS_APP_CPU_S 15 235 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; 236 * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG 237 * can be enabled in HMAC module. 238 */ 239 #define EFUSE_SOFT_DIS_JTAG 0x00000007U 240 #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) 241 #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U 242 #define EFUSE_SOFT_DIS_JTAG_S 16 243 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; 244 * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. 245 */ 246 #define EFUSE_DIS_PAD_JTAG (BIT(19)) 247 #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) 248 #define EFUSE_DIS_PAD_JTAG_V 0x00000001U 249 #define EFUSE_DIS_PAD_JTAG_S 19 250 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; 251 * Set this bit to disable flash encryption when in download boot modes. 252 */ 253 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) 254 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) 255 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U 256 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 257 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; 258 * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored 259 * in eFuse. 260 */ 261 #define EFUSE_USB_DREFH 0x00000003U 262 #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) 263 #define EFUSE_USB_DREFH_V 0x00000003U 264 #define EFUSE_USB_DREFH_S 21 265 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; 266 * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, 267 * stored in eFuse. 268 */ 269 #define EFUSE_USB_DREFL 0x00000003U 270 #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) 271 #define EFUSE_USB_DREFL_V 0x00000003U 272 #define EFUSE_USB_DREFL_S 23 273 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; 274 * Set this bit to exchange USB D+ and D- pins. 275 */ 276 #define EFUSE_USB_EXCHG_PINS (BIT(25)) 277 #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) 278 #define EFUSE_USB_EXCHG_PINS_V 0x00000001U 279 #define EFUSE_USB_EXCHG_PINS_S 25 280 /** EFUSE_USB_EXT_PHY_ENABLE : RO; bitpos: [26]; default: 0; 281 * Set this bit to enable external PHY. 282 */ 283 #define EFUSE_USB_EXT_PHY_ENABLE (BIT(26)) 284 #define EFUSE_USB_EXT_PHY_ENABLE_M (EFUSE_USB_EXT_PHY_ENABLE_V << EFUSE_USB_EXT_PHY_ENABLE_S) 285 #define EFUSE_USB_EXT_PHY_ENABLE_V 0x00000001U 286 #define EFUSE_USB_EXT_PHY_ENABLE_S 26 287 /** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0; 288 * Bluetooth GPIO signal output security level control. 289 */ 290 #define EFUSE_BTLC_GPIO_ENABLE 0x00000003U 291 #define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S) 292 #define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003U 293 #define EFUSE_BTLC_GPIO_ENABLE_S 27 294 /** EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; 295 * SPI regulator switches current limit mode. 296 */ 297 #define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) 298 #define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) 299 #define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001U 300 #define EFUSE_VDD_SPI_MODECURLIM_S 29 301 /** EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; 302 * SPI regulator high voltage reference. 303 */ 304 #define EFUSE_VDD_SPI_DREFH 0x00000003U 305 #define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) 306 #define EFUSE_VDD_SPI_DREFH_V 0x00000003U 307 #define EFUSE_VDD_SPI_DREFH_S 30 308 309 /** EFUSE_RD_REPEAT_DATA1_REG register 310 * BLOCK0 data register 2. 311 */ 312 #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) 313 /** EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; 314 * SPI regulator medium voltage reference. 315 */ 316 #define EFUSE_VDD_SPI_DREFM 0x00000003U 317 #define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) 318 #define EFUSE_VDD_SPI_DREFM_V 0x00000003U 319 #define EFUSE_VDD_SPI_DREFM_S 0 320 /** EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; 321 * SPI regulator low voltage reference. 322 */ 323 #define EFUSE_VDD_SPI_DREFL 0x00000003U 324 #define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) 325 #define EFUSE_VDD_SPI_DREFL_V 0x00000003U 326 #define EFUSE_VDD_SPI_DREFL_S 2 327 /** EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; 328 * SPI regulator power up signal. 329 */ 330 #define EFUSE_VDD_SPI_XPD (BIT(4)) 331 #define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) 332 #define EFUSE_VDD_SPI_XPD_V 0x00000001U 333 #define EFUSE_VDD_SPI_XPD_S 4 334 /** EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; 335 * SPI regulator output is short connected to VDD3P3_RTC_IO. 336 */ 337 #define EFUSE_VDD_SPI_TIEH (BIT(5)) 338 #define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) 339 #define EFUSE_VDD_SPI_TIEH_V 0x00000001U 340 #define EFUSE_VDD_SPI_TIEH_S 5 341 /** EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; 342 * Set this bit and force to use the configuration of eFuse to configure VDD_SPI. 343 */ 344 #define EFUSE_VDD_SPI_FORCE (BIT(6)) 345 #define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) 346 #define EFUSE_VDD_SPI_FORCE_V 0x00000001U 347 #define EFUSE_VDD_SPI_FORCE_S 6 348 /** EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; 349 * Set SPI regulator to 0 to configure init[1:0]=0. 350 */ 351 #define EFUSE_VDD_SPI_EN_INIT (BIT(7)) 352 #define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) 353 #define EFUSE_VDD_SPI_EN_INIT_V 0x00000001U 354 #define EFUSE_VDD_SPI_EN_INIT_S 7 355 /** EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; 356 * Set SPI regulator to 1 to enable output current limit. 357 */ 358 #define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) 359 #define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) 360 #define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001U 361 #define EFUSE_VDD_SPI_ENCURLIM_S 8 362 /** EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; 363 * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). 364 */ 365 #define EFUSE_VDD_SPI_DCURLIM 0x00000007U 366 #define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) 367 #define EFUSE_VDD_SPI_DCURLIM_V 0x00000007U 368 #define EFUSE_VDD_SPI_DCURLIM_S 9 369 /** EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; 370 * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. 371 */ 372 #define EFUSE_VDD_SPI_INIT 0x00000003U 373 #define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) 374 #define EFUSE_VDD_SPI_INIT_V 0x00000003U 375 #define EFUSE_VDD_SPI_INIT_S 12 376 /** EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; 377 * Prevents SPI regulator from overshoot. 378 */ 379 #define EFUSE_VDD_SPI_DCAP 0x00000003U 380 #define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) 381 #define EFUSE_VDD_SPI_DCAP_V 0x00000003U 382 #define EFUSE_VDD_SPI_DCAP_S 14 383 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; 384 * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 385 * 80000. 2: 160000. 3:320000. 386 */ 387 #define EFUSE_WDT_DELAY_SEL 0x00000003U 388 #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) 389 #define EFUSE_WDT_DELAY_SEL_V 0x00000003U 390 #define EFUSE_WDT_DELAY_SEL_S 16 391 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; 392 * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even 393 * number of 1: disable. 394 */ 395 #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U 396 #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) 397 #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U 398 #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 399 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; 400 * Set this bit to enable revoking first secure boot key. 401 */ 402 #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) 403 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) 404 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U 405 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 406 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; 407 * Set this bit to enable revoking second secure boot key. 408 */ 409 #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) 410 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) 411 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U 412 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 413 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; 414 * Set this bit to enable revoking third secure boot key. 415 */ 416 #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) 417 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) 418 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U 419 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 420 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; 421 * Purpose of Key0. 422 */ 423 #define EFUSE_KEY_PURPOSE_0 0x0000000FU 424 #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) 425 #define EFUSE_KEY_PURPOSE_0_V 0x0000000FU 426 #define EFUSE_KEY_PURPOSE_0_S 24 427 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; 428 * Purpose of Key1. 429 */ 430 #define EFUSE_KEY_PURPOSE_1 0x0000000FU 431 #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) 432 #define EFUSE_KEY_PURPOSE_1_V 0x0000000FU 433 #define EFUSE_KEY_PURPOSE_1_S 28 434 435 /** EFUSE_RD_REPEAT_DATA2_REG register 436 * BLOCK0 data register 3. 437 */ 438 #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) 439 /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; 440 * Purpose of Key2. 441 */ 442 #define EFUSE_KEY_PURPOSE_2 0x0000000FU 443 #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) 444 #define EFUSE_KEY_PURPOSE_2_V 0x0000000FU 445 #define EFUSE_KEY_PURPOSE_2_S 0 446 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; 447 * Purpose of Key3. 448 */ 449 #define EFUSE_KEY_PURPOSE_3 0x0000000FU 450 #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) 451 #define EFUSE_KEY_PURPOSE_3_V 0x0000000FU 452 #define EFUSE_KEY_PURPOSE_3_S 4 453 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; 454 * Purpose of Key4. 455 */ 456 #define EFUSE_KEY_PURPOSE_4 0x0000000FU 457 #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) 458 #define EFUSE_KEY_PURPOSE_4_V 0x0000000FU 459 #define EFUSE_KEY_PURPOSE_4_S 8 460 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; 461 * Purpose of Key5. 462 */ 463 #define EFUSE_KEY_PURPOSE_5 0x0000000FU 464 #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) 465 #define EFUSE_KEY_PURPOSE_5_V 0x0000000FU 466 #define EFUSE_KEY_PURPOSE_5_S 12 467 /** EFUSE_RPT4_RESERVED0 : RO; bitpos: [19:16]; default: 0; 468 * Reserved (used for four backups method). 469 */ 470 #define EFUSE_RPT4_RESERVED0 0x0000000FU 471 #define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) 472 #define EFUSE_RPT4_RESERVED0_V 0x0000000FU 473 #define EFUSE_RPT4_RESERVED0_S 16 474 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; 475 * Set this bit to enable secure boot. 476 */ 477 #define EFUSE_SECURE_BOOT_EN (BIT(20)) 478 #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) 479 #define EFUSE_SECURE_BOOT_EN_V 0x00000001U 480 #define EFUSE_SECURE_BOOT_EN_S 20 481 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; 482 * Set this bit to enable revoking aggressive secure boot. 483 */ 484 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) 485 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) 486 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U 487 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 488 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [22]; default: 0; 489 * Set this bit to disable function of usb switch to jtag in module of usb device. 490 */ 491 #define EFUSE_DIS_USB_JTAG (BIT(22)) 492 #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) 493 #define EFUSE_DIS_USB_JTAG_V 0x00000001U 494 #define EFUSE_DIS_USB_JTAG_S 22 495 /** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [23]; default: 0; 496 * Set this bit to disable usb device. 497 */ 498 #define EFUSE_DIS_USB_SERIAL_JTAG (BIT(23)) 499 #define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) 500 #define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U 501 #define EFUSE_DIS_USB_SERIAL_JTAG_S 23 502 /** EFUSE_STRAP_JTAG_SEL : RO; bitpos: [24]; default: 0; 503 * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through 504 * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. 505 */ 506 #define EFUSE_STRAP_JTAG_SEL (BIT(24)) 507 #define EFUSE_STRAP_JTAG_SEL_M (EFUSE_STRAP_JTAG_SEL_V << EFUSE_STRAP_JTAG_SEL_S) 508 #define EFUSE_STRAP_JTAG_SEL_V 0x00000001U 509 #define EFUSE_STRAP_JTAG_SEL_S 24 510 /** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0; 511 * This bit is used to switch internal PHY and external PHY for USB OTG and USB 512 * Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to 513 * USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to 514 * USB Device. 515 */ 516 #define EFUSE_USB_PHY_SEL (BIT(25)) 517 #define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S) 518 #define EFUSE_USB_PHY_SEL_V 0x00000001U 519 #define EFUSE_USB_PHY_SEL_S 25 520 /** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [27:26]; default: 0; 521 * Sample delay configuration of power glitch. 522 */ 523 #define EFUSE_POWER_GLITCH_DSENSE 0x00000003U 524 #define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S) 525 #define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003U 526 #define EFUSE_POWER_GLITCH_DSENSE_S 26 527 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; 528 * Configures flash waiting time after power-up, in unit of ms. If the value is less 529 * than 15, the waiting time is the configurable value. Otherwise, the waiting time 530 * is twice the configurable value. 531 */ 532 #define EFUSE_FLASH_TPUW 0x0000000FU 533 #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) 534 #define EFUSE_FLASH_TPUW_V 0x0000000FU 535 #define EFUSE_FLASH_TPUW_S 28 536 537 /** EFUSE_RD_REPEAT_DATA3_REG register 538 * BLOCK0 data register 4. 539 */ 540 #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) 541 /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; 542 * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). 543 */ 544 #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) 545 #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) 546 #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U 547 #define EFUSE_DIS_DOWNLOAD_MODE_S 0 548 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; 549 * Disable direct boot mode 550 */ 551 #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) 552 #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) 553 #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U 554 #define EFUSE_DIS_DIRECT_BOOT_S 1 555 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; 556 * Selectes the default UART print channel. 0: UART0. 1: UART1. 557 */ 558 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) 559 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) 560 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U 561 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 562 /** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0; 563 * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would 564 * use 16to17 byte mode. 565 */ 566 #define EFUSE_FLASH_ECC_MODE (BIT(3)) 567 #define EFUSE_FLASH_ECC_MODE_M (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S) 568 #define EFUSE_FLASH_ECC_MODE_V 0x00000001U 569 #define EFUSE_FLASH_ECC_MODE_S 3 570 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; 571 * Set this bit to disable UART download mode through USB. 572 */ 573 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) 574 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) 575 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U 576 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 577 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; 578 * Set this bit to enable secure UART download mode. 579 */ 580 #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) 581 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) 582 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U 583 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 584 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; 585 * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 586 * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. 587 */ 588 #define EFUSE_UART_PRINT_CONTROL 0x00000003U 589 #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) 590 #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U 591 #define EFUSE_UART_PRINT_CONTROL_S 6 592 /** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; 593 * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. 594 */ 595 #define EFUSE_PIN_POWER_SELECTION (BIT(8)) 596 #define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) 597 #define EFUSE_PIN_POWER_SELECTION_V 0x00000001U 598 #define EFUSE_PIN_POWER_SELECTION_S 8 599 /** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; 600 * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. 601 */ 602 #define EFUSE_FLASH_TYPE (BIT(9)) 603 #define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) 604 #define EFUSE_FLASH_TYPE_V 0x00000001U 605 #define EFUSE_FLASH_TYPE_S 9 606 /** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0; 607 * Set Flash page size. 608 */ 609 #define EFUSE_FLASH_PAGE_SIZE 0x00000003U 610 #define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) 611 #define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U 612 #define EFUSE_FLASH_PAGE_SIZE_S 10 613 /** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0; 614 * Set 1 to enable ECC for flash boot. 615 */ 616 #define EFUSE_FLASH_ECC_EN (BIT(12)) 617 #define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) 618 #define EFUSE_FLASH_ECC_EN_V 0x00000001U 619 #define EFUSE_FLASH_ECC_EN_S 12 620 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; 621 * Set this bit to force ROM code to send a resume command during SPI boot. 622 */ 623 #define EFUSE_FORCE_SEND_RESUME (BIT(13)) 624 #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) 625 #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U 626 #define EFUSE_FORCE_SEND_RESUME_S 13 627 /** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; 628 * Secure version (used by ESP-IDF anti-rollback feature). 629 */ 630 #define EFUSE_SECURE_VERSION 0x0000FFFFU 631 #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) 632 #define EFUSE_SECURE_VERSION_V 0x0000FFFFU 633 #define EFUSE_SECURE_VERSION_S 14 634 /** EFUSE_POWERGLITCH_EN : RO; bitpos: [30]; default: 0; 635 * Set this bit to enable power glitch function. 636 */ 637 #define EFUSE_POWERGLITCH_EN (BIT(30)) 638 #define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) 639 #define EFUSE_POWERGLITCH_EN_V 0x00000001U 640 #define EFUSE_POWERGLITCH_EN_S 30 641 /** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : R; bitpos: [31]; default: 0; 642 * Set this bit to disable download through USB-OTG 643 */ 644 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE (BIT(31)) 645 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S) 646 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U 647 #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 31 648 649 /** EFUSE_RD_REPEAT_DATA4_REG register 650 * BLOCK0 data register 5. 651 */ 652 #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) 653 /** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0; 654 * Disables check of wafer version major 655 */ 656 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0)) 657 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) 658 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U 659 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0 660 /** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0; 661 * Disables check of blk version major 662 */ 663 #define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1)) 664 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) 665 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U 666 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1 667 /** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0; 668 * reserved 669 */ 670 #define EFUSE_RESERVED_0_162 0x003FFFFFU 671 #define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S) 672 #define EFUSE_RESERVED_0_162_V 0x003FFFFFU 673 #define EFUSE_RESERVED_0_162_S 2 674 675 /** EFUSE_RD_MAC_SPI_SYS_0_REG register 676 * BLOCK1 data register 0. 677 */ 678 #define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) 679 /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; 680 * Stores the low 32 bits of MAC address. 681 */ 682 #define EFUSE_MAC_0 0xFFFFFFFFU 683 #define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) 684 #define EFUSE_MAC_0_V 0xFFFFFFFFU 685 #define EFUSE_MAC_0_S 0 686 687 /** EFUSE_RD_MAC_SPI_SYS_1_REG register 688 * BLOCK1 data register 1. 689 */ 690 #define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) 691 /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; 692 * Stores the high 16 bits of MAC address. 693 */ 694 #define EFUSE_MAC_1 0x0000FFFFU 695 #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) 696 #define EFUSE_MAC_1_V 0x0000FFFFU 697 #define EFUSE_MAC_1_S 0 698 /** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0; 699 * SPI_PAD_configure CLK 700 */ 701 #define EFUSE_SPI_PAD_CONFIG_CLK 0x0000003FU 702 #define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) 703 #define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000003FU 704 #define EFUSE_SPI_PAD_CONFIG_CLK_S 16 705 /** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0; 706 * SPI_PAD_configure Q(D1) 707 */ 708 #define EFUSE_SPI_PAD_CONFIG_Q 0x0000003FU 709 #define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) 710 #define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000003FU 711 #define EFUSE_SPI_PAD_CONFIG_Q_S 22 712 /** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0; 713 * SPI_PAD_configure D(D0) 714 */ 715 #define EFUSE_SPI_PAD_CONFIG_D 0x0000000FU 716 #define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) 717 #define EFUSE_SPI_PAD_CONFIG_D_V 0x0000000FU 718 #define EFUSE_SPI_PAD_CONFIG_D_S 28 719 720 /** EFUSE_RD_MAC_SPI_SYS_2_REG register 721 * BLOCK1 data register 2. 722 */ 723 #define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) 724 /* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 725 /*description: Stores the first part of SPI_PAD_CONF..*/ 726 #define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF 727 #define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) 728 #define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF 729 #define EFUSE_SPI_PAD_CONF_1_S 0 730 /** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0; 731 * SPI_PAD_configure D(D0) 732 */ 733 #define EFUSE_SPI_PAD_CONFIG_D_1 0x00000003U 734 #define EFUSE_SPI_PAD_CONFIG_D_1_M (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S) 735 #define EFUSE_SPI_PAD_CONFIG_D_1_V 0x00000003U 736 #define EFUSE_SPI_PAD_CONFIG_D_1_S 0 737 /** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0; 738 * SPI_PAD_configure CS 739 */ 740 #define EFUSE_SPI_PAD_CONFIG_CS 0x0000003FU 741 #define EFUSE_SPI_PAD_CONFIG_CS_M (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S) 742 #define EFUSE_SPI_PAD_CONFIG_CS_V 0x0000003FU 743 #define EFUSE_SPI_PAD_CONFIG_CS_S 2 744 /** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0; 745 * SPI_PAD_configure HD(D3) 746 */ 747 #define EFUSE_SPI_PAD_CONFIG_HD 0x0000003FU 748 #define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) 749 #define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000003FU 750 #define EFUSE_SPI_PAD_CONFIG_HD_S 8 751 /** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0; 752 * SPI_PAD_configure WP(D2) 753 */ 754 #define EFUSE_SPI_PAD_CONFIG_WP 0x0000003FU 755 #define EFUSE_SPI_PAD_CONFIG_WP_M (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S) 756 #define EFUSE_SPI_PAD_CONFIG_WP_V 0x0000003FU 757 #define EFUSE_SPI_PAD_CONFIG_WP_S 14 758 /** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0; 759 * SPI_PAD_configure DQS 760 */ 761 #define EFUSE_SPI_PAD_CONFIG_DQS 0x0000003FU 762 #define EFUSE_SPI_PAD_CONFIG_DQS_M (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S) 763 #define EFUSE_SPI_PAD_CONFIG_DQS_V 0x0000003FU 764 #define EFUSE_SPI_PAD_CONFIG_DQS_S 20 765 /** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0; 766 * SPI_PAD_configure D4 767 */ 768 #define EFUSE_SPI_PAD_CONFIG_D4 0x0000003FU 769 #define EFUSE_SPI_PAD_CONFIG_D4_M (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S) 770 #define EFUSE_SPI_PAD_CONFIG_D4_V 0x0000003FU 771 #define EFUSE_SPI_PAD_CONFIG_D4_S 26 772 773 /** EFUSE_RD_MAC_SPI_SYS_3_REG register 774 * BLOCK1 data register 3. 775 */ 776 #define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) 777 /** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; 778 * SPI_PAD_configure D5 779 */ 780 #define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU 781 #define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) 782 #define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU 783 #define EFUSE_SPI_PAD_CONFIG_D5_S 0 784 /** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; 785 * SPI_PAD_configure D6 786 */ 787 #define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU 788 #define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) 789 #define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU 790 #define EFUSE_SPI_PAD_CONFIG_D6_S 6 791 /** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; 792 * SPI_PAD_configure D7 793 */ 794 #define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU 795 #define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) 796 #define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU 797 #define EFUSE_SPI_PAD_CONFIG_D7_S 12 798 /** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0; 799 * WAFER_VERSION_MINOR least significant bits 800 */ 801 #define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U 802 #define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) 803 #define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U 804 #define EFUSE_WAFER_VERSION_MINOR_LO_S 18 805 /** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0; 806 * Package version 807 */ 808 #define EFUSE_PKG_VERSION 0x00000007U 809 #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) 810 #define EFUSE_PKG_VERSION_V 0x00000007U 811 #define EFUSE_PKG_VERSION_S 21 812 /** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0; 813 * BLK_VERSION_MINOR 814 */ 815 #define EFUSE_BLK_VERSION_MINOR 0x00000007U 816 #define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) 817 #define EFUSE_BLK_VERSION_MINOR_V 0x00000007U 818 #define EFUSE_BLK_VERSION_MINOR_S 24 819 /** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0; 820 * Flash capacity 821 */ 822 #define EFUSE_FLASH_CAP 0x00000007U 823 #define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) 824 #define EFUSE_FLASH_CAP_V 0x00000007U 825 #define EFUSE_FLASH_CAP_S 27 826 /** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0; 827 * Flash temperature 828 */ 829 #define EFUSE_FLASH_TEMP 0x00000003U 830 #define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) 831 #define EFUSE_FLASH_TEMP_V 0x00000003U 832 #define EFUSE_FLASH_TEMP_S 30 833 834 /** EFUSE_RD_MAC_SPI_SYS_4_REG register 835 * BLOCK1 data register 4. 836 */ 837 #define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) 838 /** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0; 839 * Flash vendor 840 */ 841 #define EFUSE_FLASH_VENDOR 0x00000007U 842 #define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) 843 #define EFUSE_FLASH_VENDOR_V 0x00000007U 844 #define EFUSE_FLASH_VENDOR_S 0 845 /** EFUSE_PSRAM_CAP : R; bitpos: [4:3]; default: 0; 846 * PSRAM capacity 847 */ 848 #define EFUSE_PSRAM_CAP 0x00000003U 849 #define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) 850 #define EFUSE_PSRAM_CAP_V 0x00000003U 851 #define EFUSE_PSRAM_CAP_S 3 852 /** EFUSE_PSRAM_TEMP : R; bitpos: [6:5]; default: 0; 853 * PSRAM temperature 854 */ 855 #define EFUSE_PSRAM_TEMP 0x00000003U 856 #define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S) 857 #define EFUSE_PSRAM_TEMP_V 0x00000003U 858 #define EFUSE_PSRAM_TEMP_S 5 859 /** EFUSE_PSRAM_VENDOR : R; bitpos: [8:7]; default: 0; 860 * PSRAM vendor 861 */ 862 #define EFUSE_PSRAM_VENDOR 0x00000003U 863 #define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) 864 #define EFUSE_PSRAM_VENDOR_V 0x00000003U 865 #define EFUSE_PSRAM_VENDOR_S 7 866 /** EFUSE_RESERVED_1_137 : R; bitpos: [12:9]; default: 0; 867 * reserved 868 */ 869 #define EFUSE_RESERVED_1_137 0x0000000FU 870 #define EFUSE_RESERVED_1_137_M (EFUSE_RESERVED_1_137_V << EFUSE_RESERVED_1_137_S) 871 #define EFUSE_RESERVED_1_137_V 0x0000000FU 872 #define EFUSE_RESERVED_1_137_S 9 873 /** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0; 874 * BLOCK1 K_RTC_LDO 875 */ 876 #define EFUSE_K_RTC_LDO 0x0000007FU 877 #define EFUSE_K_RTC_LDO_M (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S) 878 #define EFUSE_K_RTC_LDO_V 0x0000007FU 879 #define EFUSE_K_RTC_LDO_S 13 880 /** EFUSE_K_DIG_LDO : R; bitpos: [26:20]; default: 0; 881 * BLOCK1 K_DIG_LDO 882 */ 883 #define EFUSE_K_DIG_LDO 0x0000007FU 884 #define EFUSE_K_DIG_LDO_M (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S) 885 #define EFUSE_K_DIG_LDO_V 0x0000007FU 886 #define EFUSE_K_DIG_LDO_S 20 887 /** EFUSE_V_RTC_DBIAS20 : R; bitpos: [31:27]; default: 0; 888 * BLOCK1 voltage of rtc dbias20 889 */ 890 #define EFUSE_V_RTC_DBIAS20 0x0000001FU 891 #define EFUSE_V_RTC_DBIAS20_M (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S) 892 #define EFUSE_V_RTC_DBIAS20_V 0x0000001FU 893 #define EFUSE_V_RTC_DBIAS20_S 27 894 895 /** EFUSE_RD_MAC_SPI_SYS_5_REG register 896 * BLOCK1 data register 5. 897 */ 898 #define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) 899 /** EFUSE_V_RTC_DBIAS20_1 : R; bitpos: [2:0]; default: 0; 900 * BLOCK1 voltage of rtc dbias20 901 */ 902 #define EFUSE_V_RTC_DBIAS20_1 0x00000007U 903 #define EFUSE_V_RTC_DBIAS20_1_M (EFUSE_V_RTC_DBIAS20_1_V << EFUSE_V_RTC_DBIAS20_1_S) 904 #define EFUSE_V_RTC_DBIAS20_1_V 0x00000007U 905 #define EFUSE_V_RTC_DBIAS20_1_S 0 906 /** EFUSE_V_DIG_DBIAS20 : R; bitpos: [10:3]; default: 0; 907 * BLOCK1 voltage of digital dbias20 908 */ 909 #define EFUSE_V_DIG_DBIAS20 0x000000FFU 910 #define EFUSE_V_DIG_DBIAS20_M (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S) 911 #define EFUSE_V_DIG_DBIAS20_V 0x000000FFU 912 #define EFUSE_V_DIG_DBIAS20_S 3 913 /** EFUSE_DIG_DBIAS_HVT : R; bitpos: [15:11]; default: 0; 914 * BLOCK1 digital dbias when hvt 915 */ 916 #define EFUSE_DIG_DBIAS_HVT 0x0000001FU 917 #define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) 918 #define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU 919 #define EFUSE_DIG_DBIAS_HVT_S 11 920 /** EFUSE_RESERVED_1_176 : R; bitpos: [22:16]; default: 0; 921 * reserved 922 */ 923 #define EFUSE_RESERVED_1_176 0x0000007FU 924 #define EFUSE_RESERVED_1_176_M (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S) 925 #define EFUSE_RESERVED_1_176_V 0x0000007FU 926 #define EFUSE_RESERVED_1_176_S 16 927 /** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0; 928 * WAFER_VERSION_MINOR most significant bit 929 */ 930 #define EFUSE_WAFER_VERSION_MINOR_HI (BIT(23)) 931 #define EFUSE_WAFER_VERSION_MINOR_HI_M (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S) 932 #define EFUSE_WAFER_VERSION_MINOR_HI_V 0x00000001U 933 #define EFUSE_WAFER_VERSION_MINOR_HI_S 23 934 /** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0; 935 * WAFER_VERSION_MAJOR 936 */ 937 #define EFUSE_WAFER_VERSION_MAJOR 0x00000003U 938 #define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) 939 #define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U 940 #define EFUSE_WAFER_VERSION_MAJOR_S 24 941 /** EFUSE_ADC2_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0; 942 * ADC2 calibration voltage at atten3 943 */ 944 #define EFUSE_ADC2_CAL_VOL_ATTEN3 0x0000003FU 945 #define EFUSE_ADC2_CAL_VOL_ATTEN3_M (EFUSE_ADC2_CAL_VOL_ATTEN3_V << EFUSE_ADC2_CAL_VOL_ATTEN3_S) 946 #define EFUSE_ADC2_CAL_VOL_ATTEN3_V 0x0000003FU 947 #define EFUSE_ADC2_CAL_VOL_ATTEN3_S 26 948 949 /** EFUSE_RD_SYS_PART1_DATA0_REG register 950 * Register 0 of BLOCK2 (system). 951 */ 952 #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) 953 /** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; 954 * Optional unique 128-bit ID 955 */ 956 #define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU 957 #define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) 958 #define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU 959 #define EFUSE_OPTIONAL_UNIQUE_ID_S 0 960 961 /** EFUSE_RD_SYS_PART1_DATA1_REG register 962 * Register 1 of BLOCK2 (system). 963 */ 964 #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) 965 /** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; 966 * Optional unique 128-bit ID 967 */ 968 #define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU 969 #define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) 970 #define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU 971 #define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 972 973 /** EFUSE_RD_SYS_PART1_DATA2_REG register 974 * Register 2 of BLOCK2 (system). 975 */ 976 #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) 977 /** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; 978 * Optional unique 128-bit ID 979 */ 980 #define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU 981 #define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) 982 #define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU 983 #define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 984 985 /** EFUSE_RD_SYS_PART1_DATA3_REG register 986 * Register 3 of BLOCK2 (system). 987 */ 988 #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) 989 /** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; 990 * Optional unique 128-bit ID 991 */ 992 #define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU 993 #define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) 994 #define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU 995 #define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 996 997 /** EFUSE_RD_SYS_PART1_DATA4_REG register 998 * Register 4 of BLOCK2 (system). 999 */ 1000 #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) 1001 /** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0; 1002 * BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware 1003 */ 1004 #define EFUSE_BLK_VERSION_MAJOR 0x00000003U 1005 #define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) 1006 #define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U 1007 #define EFUSE_BLK_VERSION_MAJOR_S 0 1008 /** EFUSE_RESERVED_2_130 : R; bitpos: [3:2]; default: 0; 1009 * reserved 1010 */ 1011 #define EFUSE_RESERVED_2_130 0x00000003U 1012 #define EFUSE_RESERVED_2_130_M (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S) 1013 #define EFUSE_RESERVED_2_130_V 0x00000003U 1014 #define EFUSE_RESERVED_2_130_S 2 1015 /** EFUSE_TEMP_CALIB : R; bitpos: [12:4]; default: 0; 1016 * Temperature calibration data 1017 */ 1018 #define EFUSE_TEMP_CALIB 0x000001FFU 1019 #define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) 1020 #define EFUSE_TEMP_CALIB_V 0x000001FFU 1021 #define EFUSE_TEMP_CALIB_S 4 1022 /** EFUSE_OCODE : R; bitpos: [20:13]; default: 0; 1023 * ADC OCode 1024 */ 1025 #define EFUSE_OCODE 0x000000FFU 1026 #define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) 1027 #define EFUSE_OCODE_V 0x000000FFU 1028 #define EFUSE_OCODE_S 13 1029 /** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [28:21]; default: 0; 1030 * ADC1 init code at atten0 1031 */ 1032 #define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000000FFU 1033 #define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S) 1034 #define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000000FFU 1035 #define EFUSE_ADC1_INIT_CODE_ATTEN0_S 21 1036 /** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:29]; default: 0; 1037 * ADC1 init code at atten1 1038 */ 1039 #define EFUSE_ADC1_INIT_CODE_ATTEN1 0x00000007U 1040 #define EFUSE_ADC1_INIT_CODE_ATTEN1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S) 1041 #define EFUSE_ADC1_INIT_CODE_ATTEN1_V 0x00000007U 1042 #define EFUSE_ADC1_INIT_CODE_ATTEN1_S 29 1043 1044 /** EFUSE_RD_SYS_PART1_DATA5_REG register 1045 * Register 5 of BLOCK2 (system). 1046 */ 1047 #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) 1048 /** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [2:0]; default: 0; 1049 * ADC1 init code at atten1 1050 */ 1051 #define EFUSE_ADC1_INIT_CODE_ATTEN1_1 0x00000007U 1052 #define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S) 1053 #define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V 0x00000007U 1054 #define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S 0 1055 /** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [8:3]; default: 0; 1056 * ADC1 init code at atten2 1057 */ 1058 #define EFUSE_ADC1_INIT_CODE_ATTEN2 0x0000003FU 1059 #define EFUSE_ADC1_INIT_CODE_ATTEN2_M (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S) 1060 #define EFUSE_ADC1_INIT_CODE_ATTEN2_V 0x0000003FU 1061 #define EFUSE_ADC1_INIT_CODE_ATTEN2_S 3 1062 /** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [14:9]; default: 0; 1063 * ADC1 init code at atten3 1064 */ 1065 #define EFUSE_ADC1_INIT_CODE_ATTEN3 0x0000003FU 1066 #define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S) 1067 #define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x0000003FU 1068 #define EFUSE_ADC1_INIT_CODE_ATTEN3_S 9 1069 /** EFUSE_ADC2_INIT_CODE_ATTEN0 : R; bitpos: [22:15]; default: 0; 1070 * ADC2 init code at atten0 1071 */ 1072 #define EFUSE_ADC2_INIT_CODE_ATTEN0 0x000000FFU 1073 #define EFUSE_ADC2_INIT_CODE_ATTEN0_M (EFUSE_ADC2_INIT_CODE_ATTEN0_V << EFUSE_ADC2_INIT_CODE_ATTEN0_S) 1074 #define EFUSE_ADC2_INIT_CODE_ATTEN0_V 0x000000FFU 1075 #define EFUSE_ADC2_INIT_CODE_ATTEN0_S 15 1076 /** EFUSE_ADC2_INIT_CODE_ATTEN1 : R; bitpos: [28:23]; default: 0; 1077 * ADC2 init code at atten1 1078 */ 1079 #define EFUSE_ADC2_INIT_CODE_ATTEN1 0x0000003FU 1080 #define EFUSE_ADC2_INIT_CODE_ATTEN1_M (EFUSE_ADC2_INIT_CODE_ATTEN1_V << EFUSE_ADC2_INIT_CODE_ATTEN1_S) 1081 #define EFUSE_ADC2_INIT_CODE_ATTEN1_V 0x0000003FU 1082 #define EFUSE_ADC2_INIT_CODE_ATTEN1_S 23 1083 /** EFUSE_ADC2_INIT_CODE_ATTEN2 : R; bitpos: [31:29]; default: 0; 1084 * ADC2 init code at atten2 1085 */ 1086 #define EFUSE_ADC2_INIT_CODE_ATTEN2 0x00000007U 1087 #define EFUSE_ADC2_INIT_CODE_ATTEN2_M (EFUSE_ADC2_INIT_CODE_ATTEN2_V << EFUSE_ADC2_INIT_CODE_ATTEN2_S) 1088 #define EFUSE_ADC2_INIT_CODE_ATTEN2_V 0x00000007U 1089 #define EFUSE_ADC2_INIT_CODE_ATTEN2_S 29 1090 1091 /** EFUSE_RD_SYS_PART1_DATA6_REG register 1092 * Register 6 of BLOCK2 (system). 1093 */ 1094 #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) 1095 /** EFUSE_ADC2_INIT_CODE_ATTEN2_1 : R; bitpos: [2:0]; default: 0; 1096 * ADC2 init code at atten2 1097 */ 1098 #define EFUSE_ADC2_INIT_CODE_ATTEN2_1 0x00000007U 1099 #define EFUSE_ADC2_INIT_CODE_ATTEN2_1_M (EFUSE_ADC2_INIT_CODE_ATTEN2_1_V << EFUSE_ADC2_INIT_CODE_ATTEN2_1_S) 1100 #define EFUSE_ADC2_INIT_CODE_ATTEN2_1_V 0x00000007U 1101 #define EFUSE_ADC2_INIT_CODE_ATTEN2_1_S 0 1102 /** EFUSE_ADC2_INIT_CODE_ATTEN3 : R; bitpos: [8:3]; default: 0; 1103 * ADC2 init code at atten3 1104 */ 1105 #define EFUSE_ADC2_INIT_CODE_ATTEN3 0x0000003FU 1106 #define EFUSE_ADC2_INIT_CODE_ATTEN3_M (EFUSE_ADC2_INIT_CODE_ATTEN3_V << EFUSE_ADC2_INIT_CODE_ATTEN3_S) 1107 #define EFUSE_ADC2_INIT_CODE_ATTEN3_V 0x0000003FU 1108 #define EFUSE_ADC2_INIT_CODE_ATTEN3_S 3 1109 /** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0; 1110 * ADC1 calibration voltage at atten0 1111 */ 1112 #define EFUSE_ADC1_CAL_VOL_ATTEN0 0x000000FFU 1113 #define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S) 1114 #define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x000000FFU 1115 #define EFUSE_ADC1_CAL_VOL_ATTEN0_S 9 1116 /** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [24:17]; default: 0; 1117 * ADC1 calibration voltage at atten1 1118 */ 1119 #define EFUSE_ADC1_CAL_VOL_ATTEN1 0x000000FFU 1120 #define EFUSE_ADC1_CAL_VOL_ATTEN1_M (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S) 1121 #define EFUSE_ADC1_CAL_VOL_ATTEN1_V 0x000000FFU 1122 #define EFUSE_ADC1_CAL_VOL_ATTEN1_S 17 1123 /** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [31:25]; default: 0; 1124 * ADC1 calibration voltage at atten2 1125 */ 1126 #define EFUSE_ADC1_CAL_VOL_ATTEN2 0x0000007FU 1127 #define EFUSE_ADC1_CAL_VOL_ATTEN2_M (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S) 1128 #define EFUSE_ADC1_CAL_VOL_ATTEN2_V 0x0000007FU 1129 #define EFUSE_ADC1_CAL_VOL_ATTEN2_S 25 1130 1131 /** EFUSE_RD_SYS_PART1_DATA7_REG register 1132 * Register 7 of BLOCK2 (system). 1133 */ 1134 #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) 1135 /** EFUSE_ADC1_CAL_VOL_ATTEN2_1 : R; bitpos: [0]; default: 0; 1136 * ADC1 calibration voltage at atten2 1137 */ 1138 #define EFUSE_ADC1_CAL_VOL_ATTEN2_1 (BIT(0)) 1139 #define EFUSE_ADC1_CAL_VOL_ATTEN2_1_M (EFUSE_ADC1_CAL_VOL_ATTEN2_1_V << EFUSE_ADC1_CAL_VOL_ATTEN2_1_S) 1140 #define EFUSE_ADC1_CAL_VOL_ATTEN2_1_V 0x00000001U 1141 #define EFUSE_ADC1_CAL_VOL_ATTEN2_1_S 0 1142 /** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:1]; default: 0; 1143 * ADC1 calibration voltage at atten3 1144 */ 1145 #define EFUSE_ADC1_CAL_VOL_ATTEN3 0x000000FFU 1146 #define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S) 1147 #define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x000000FFU 1148 #define EFUSE_ADC1_CAL_VOL_ATTEN3_S 1 1149 /** EFUSE_ADC2_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0; 1150 * ADC2 calibration voltage at atten0 1151 */ 1152 #define EFUSE_ADC2_CAL_VOL_ATTEN0 0x000000FFU 1153 #define EFUSE_ADC2_CAL_VOL_ATTEN0_M (EFUSE_ADC2_CAL_VOL_ATTEN0_V << EFUSE_ADC2_CAL_VOL_ATTEN0_S) 1154 #define EFUSE_ADC2_CAL_VOL_ATTEN0_V 0x000000FFU 1155 #define EFUSE_ADC2_CAL_VOL_ATTEN0_S 9 1156 /** EFUSE_ADC2_CAL_VOL_ATTEN1 : R; bitpos: [23:17]; default: 0; 1157 * ADC2 calibration voltage at atten1 1158 */ 1159 #define EFUSE_ADC2_CAL_VOL_ATTEN1 0x0000007FU 1160 #define EFUSE_ADC2_CAL_VOL_ATTEN1_M (EFUSE_ADC2_CAL_VOL_ATTEN1_V << EFUSE_ADC2_CAL_VOL_ATTEN1_S) 1161 #define EFUSE_ADC2_CAL_VOL_ATTEN1_V 0x0000007FU 1162 #define EFUSE_ADC2_CAL_VOL_ATTEN1_S 17 1163 /** EFUSE_ADC2_CAL_VOL_ATTEN2 : R; bitpos: [30:24]; default: 0; 1164 * ADC2 calibration voltage at atten2 1165 */ 1166 #define EFUSE_ADC2_CAL_VOL_ATTEN2 0x0000007FU 1167 #define EFUSE_ADC2_CAL_VOL_ATTEN2_M (EFUSE_ADC2_CAL_VOL_ATTEN2_V << EFUSE_ADC2_CAL_VOL_ATTEN2_S) 1168 #define EFUSE_ADC2_CAL_VOL_ATTEN2_V 0x0000007FU 1169 #define EFUSE_ADC2_CAL_VOL_ATTEN2_S 24 1170 /** EFUSE_RESERVED_2_255 : R; bitpos: [31]; default: 0; 1171 * reserved 1172 */ 1173 #define EFUSE_RESERVED_2_255 (BIT(31)) 1174 #define EFUSE_RESERVED_2_255_M (EFUSE_RESERVED_2_255_V << EFUSE_RESERVED_2_255_S) 1175 #define EFUSE_RESERVED_2_255_V 0x00000001U 1176 #define EFUSE_RESERVED_2_255_S 31 1177 1178 /** EFUSE_RD_USR_DATA0_REG register 1179 * Register 0 of BLOCK3 (user). 1180 */ 1181 #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) 1182 /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; 1183 * Stores the zeroth 32 bits of BLOCK3 (user). 1184 */ 1185 #define EFUSE_USR_DATA0 0xFFFFFFFFU 1186 #define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) 1187 #define EFUSE_USR_DATA0_V 0xFFFFFFFFU 1188 #define EFUSE_USR_DATA0_S 0 1189 1190 /** EFUSE_RD_USR_DATA1_REG register 1191 * Register 1 of BLOCK3 (user). 1192 */ 1193 #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) 1194 /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; 1195 * Stores the first 32 bits of BLOCK3 (user). 1196 */ 1197 #define EFUSE_USR_DATA1 0xFFFFFFFFU 1198 #define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) 1199 #define EFUSE_USR_DATA1_V 0xFFFFFFFFU 1200 #define EFUSE_USR_DATA1_S 0 1201 1202 /** EFUSE_RD_USR_DATA2_REG register 1203 * Register 2 of BLOCK3 (user). 1204 */ 1205 #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) 1206 /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; 1207 * Stores the second 32 bits of BLOCK3 (user). 1208 */ 1209 #define EFUSE_USR_DATA2 0xFFFFFFFFU 1210 #define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) 1211 #define EFUSE_USR_DATA2_V 0xFFFFFFFFU 1212 #define EFUSE_USR_DATA2_S 0 1213 1214 /** EFUSE_RD_USR_DATA3_REG register 1215 * Register 3 of BLOCK3 (user). 1216 */ 1217 #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) 1218 /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; 1219 * Stores the third 32 bits of BLOCK3 (user). 1220 */ 1221 #define EFUSE_USR_DATA3 0xFFFFFFFFU 1222 #define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) 1223 #define EFUSE_USR_DATA3_V 0xFFFFFFFFU 1224 #define EFUSE_USR_DATA3_S 0 1225 1226 /** EFUSE_RD_USR_DATA4_REG register 1227 * Register 4 of BLOCK3 (user). 1228 */ 1229 #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) 1230 /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; 1231 * Stores the fourth 32 bits of BLOCK3 (user). 1232 */ 1233 #define EFUSE_USR_DATA4 0xFFFFFFFFU 1234 #define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) 1235 #define EFUSE_USR_DATA4_V 0xFFFFFFFFU 1236 #define EFUSE_USR_DATA4_S 0 1237 1238 /** EFUSE_RD_USR_DATA5_REG register 1239 * Register 5 of BLOCK3 (user). 1240 */ 1241 #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) 1242 /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; 1243 * Stores the fifth 32 bits of BLOCK3 (user). 1244 */ 1245 #define EFUSE_USR_DATA5 0xFFFFFFFFU 1246 #define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) 1247 #define EFUSE_USR_DATA5_V 0xFFFFFFFFU 1248 #define EFUSE_USR_DATA5_S 0 1249 1250 /** EFUSE_RD_USR_DATA6_REG register 1251 * Register 6 of BLOCK3 (user). 1252 */ 1253 #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) 1254 /** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; 1255 * reserved 1256 */ 1257 #define EFUSE_RESERVED_3_192 0x000000FFU 1258 #define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) 1259 #define EFUSE_RESERVED_3_192_V 0x000000FFU 1260 #define EFUSE_RESERVED_3_192_S 0 1261 /** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; 1262 * Custom MAC 1263 */ 1264 #define EFUSE_CUSTOM_MAC 0x00FFFFFFU 1265 #define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) 1266 #define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU 1267 #define EFUSE_CUSTOM_MAC_S 8 1268 1269 /** EFUSE_RD_USR_DATA7_REG register 1270 * Register 7 of BLOCK3 (user). 1271 */ 1272 #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) 1273 /** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; 1274 * Custom MAC 1275 */ 1276 #define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU 1277 #define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) 1278 #define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU 1279 #define EFUSE_CUSTOM_MAC_1_S 0 1280 /** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; 1281 * reserved 1282 */ 1283 #define EFUSE_RESERVED_3_248 0x000000FFU 1284 #define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) 1285 #define EFUSE_RESERVED_3_248_V 0x000000FFU 1286 #define EFUSE_RESERVED_3_248_S 24 1287 1288 /** EFUSE_RD_KEY0_DATA0_REG register 1289 * Register 0 of BLOCK4 (KEY0). 1290 */ 1291 #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) 1292 /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; 1293 * Stores the zeroth 32 bits of KEY0. 1294 */ 1295 #define EFUSE_KEY0_DATA0 0xFFFFFFFFU 1296 #define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) 1297 #define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU 1298 #define EFUSE_KEY0_DATA0_S 0 1299 1300 /** EFUSE_RD_KEY0_DATA1_REG register 1301 * Register 1 of BLOCK4 (KEY0). 1302 */ 1303 #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) 1304 /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; 1305 * Stores the first 32 bits of KEY0. 1306 */ 1307 #define EFUSE_KEY0_DATA1 0xFFFFFFFFU 1308 #define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) 1309 #define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU 1310 #define EFUSE_KEY0_DATA1_S 0 1311 1312 /** EFUSE_RD_KEY0_DATA2_REG register 1313 * Register 2 of BLOCK4 (KEY0). 1314 */ 1315 #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) 1316 /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; 1317 * Stores the second 32 bits of KEY0. 1318 */ 1319 #define EFUSE_KEY0_DATA2 0xFFFFFFFFU 1320 #define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) 1321 #define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU 1322 #define EFUSE_KEY0_DATA2_S 0 1323 1324 /** EFUSE_RD_KEY0_DATA3_REG register 1325 * Register 3 of BLOCK4 (KEY0). 1326 */ 1327 #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) 1328 /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; 1329 * Stores the third 32 bits of KEY0. 1330 */ 1331 #define EFUSE_KEY0_DATA3 0xFFFFFFFFU 1332 #define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) 1333 #define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU 1334 #define EFUSE_KEY0_DATA3_S 0 1335 1336 /** EFUSE_RD_KEY0_DATA4_REG register 1337 * Register 4 of BLOCK4 (KEY0). 1338 */ 1339 #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) 1340 /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; 1341 * Stores the fourth 32 bits of KEY0. 1342 */ 1343 #define EFUSE_KEY0_DATA4 0xFFFFFFFFU 1344 #define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) 1345 #define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU 1346 #define EFUSE_KEY0_DATA4_S 0 1347 1348 /** EFUSE_RD_KEY0_DATA5_REG register 1349 * Register 5 of BLOCK4 (KEY0). 1350 */ 1351 #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) 1352 /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; 1353 * Stores the fifth 32 bits of KEY0. 1354 */ 1355 #define EFUSE_KEY0_DATA5 0xFFFFFFFFU 1356 #define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) 1357 #define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU 1358 #define EFUSE_KEY0_DATA5_S 0 1359 1360 /** EFUSE_RD_KEY0_DATA6_REG register 1361 * Register 6 of BLOCK4 (KEY0). 1362 */ 1363 #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) 1364 /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; 1365 * Stores the sixth 32 bits of KEY0. 1366 */ 1367 #define EFUSE_KEY0_DATA6 0xFFFFFFFFU 1368 #define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) 1369 #define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU 1370 #define EFUSE_KEY0_DATA6_S 0 1371 1372 /** EFUSE_RD_KEY0_DATA7_REG register 1373 * Register 7 of BLOCK4 (KEY0). 1374 */ 1375 #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) 1376 /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; 1377 * Stores the seventh 32 bits of KEY0. 1378 */ 1379 #define EFUSE_KEY0_DATA7 0xFFFFFFFFU 1380 #define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) 1381 #define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU 1382 #define EFUSE_KEY0_DATA7_S 0 1383 1384 /** EFUSE_RD_KEY1_DATA0_REG register 1385 * Register 0 of BLOCK5 (KEY1). 1386 */ 1387 #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) 1388 /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; 1389 * Stores the zeroth 32 bits of KEY1. 1390 */ 1391 #define EFUSE_KEY1_DATA0 0xFFFFFFFFU 1392 #define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) 1393 #define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU 1394 #define EFUSE_KEY1_DATA0_S 0 1395 1396 /** EFUSE_RD_KEY1_DATA1_REG register 1397 * Register 1 of BLOCK5 (KEY1). 1398 */ 1399 #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) 1400 /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; 1401 * Stores the first 32 bits of KEY1. 1402 */ 1403 #define EFUSE_KEY1_DATA1 0xFFFFFFFFU 1404 #define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) 1405 #define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU 1406 #define EFUSE_KEY1_DATA1_S 0 1407 1408 /** EFUSE_RD_KEY1_DATA2_REG register 1409 * Register 2 of BLOCK5 (KEY1). 1410 */ 1411 #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) 1412 /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; 1413 * Stores the second 32 bits of KEY1. 1414 */ 1415 #define EFUSE_KEY1_DATA2 0xFFFFFFFFU 1416 #define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) 1417 #define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU 1418 #define EFUSE_KEY1_DATA2_S 0 1419 1420 /** EFUSE_RD_KEY1_DATA3_REG register 1421 * Register 3 of BLOCK5 (KEY1). 1422 */ 1423 #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) 1424 /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; 1425 * Stores the third 32 bits of KEY1. 1426 */ 1427 #define EFUSE_KEY1_DATA3 0xFFFFFFFFU 1428 #define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) 1429 #define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU 1430 #define EFUSE_KEY1_DATA3_S 0 1431 1432 /** EFUSE_RD_KEY1_DATA4_REG register 1433 * Register 4 of BLOCK5 (KEY1). 1434 */ 1435 #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) 1436 /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; 1437 * Stores the fourth 32 bits of KEY1. 1438 */ 1439 #define EFUSE_KEY1_DATA4 0xFFFFFFFFU 1440 #define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) 1441 #define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU 1442 #define EFUSE_KEY1_DATA4_S 0 1443 1444 /** EFUSE_RD_KEY1_DATA5_REG register 1445 * Register 5 of BLOCK5 (KEY1). 1446 */ 1447 #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) 1448 /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; 1449 * Stores the fifth 32 bits of KEY1. 1450 */ 1451 #define EFUSE_KEY1_DATA5 0xFFFFFFFFU 1452 #define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) 1453 #define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU 1454 #define EFUSE_KEY1_DATA5_S 0 1455 1456 /** EFUSE_RD_KEY1_DATA6_REG register 1457 * Register 6 of BLOCK5 (KEY1). 1458 */ 1459 #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) 1460 /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; 1461 * Stores the sixth 32 bits of KEY1. 1462 */ 1463 #define EFUSE_KEY1_DATA6 0xFFFFFFFFU 1464 #define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) 1465 #define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU 1466 #define EFUSE_KEY1_DATA6_S 0 1467 1468 /** EFUSE_RD_KEY1_DATA7_REG register 1469 * Register 7 of BLOCK5 (KEY1). 1470 */ 1471 #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) 1472 /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; 1473 * Stores the seventh 32 bits of KEY1. 1474 */ 1475 #define EFUSE_KEY1_DATA7 0xFFFFFFFFU 1476 #define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) 1477 #define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU 1478 #define EFUSE_KEY1_DATA7_S 0 1479 1480 /** EFUSE_RD_KEY2_DATA0_REG register 1481 * Register 0 of BLOCK6 (KEY2). 1482 */ 1483 #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) 1484 /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; 1485 * Stores the zeroth 32 bits of KEY2. 1486 */ 1487 #define EFUSE_KEY2_DATA0 0xFFFFFFFFU 1488 #define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) 1489 #define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU 1490 #define EFUSE_KEY2_DATA0_S 0 1491 1492 /** EFUSE_RD_KEY2_DATA1_REG register 1493 * Register 1 of BLOCK6 (KEY2). 1494 */ 1495 #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) 1496 /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; 1497 * Stores the first 32 bits of KEY2. 1498 */ 1499 #define EFUSE_KEY2_DATA1 0xFFFFFFFFU 1500 #define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) 1501 #define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU 1502 #define EFUSE_KEY2_DATA1_S 0 1503 1504 /** EFUSE_RD_KEY2_DATA2_REG register 1505 * Register 2 of BLOCK6 (KEY2). 1506 */ 1507 #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) 1508 /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; 1509 * Stores the second 32 bits of KEY2. 1510 */ 1511 #define EFUSE_KEY2_DATA2 0xFFFFFFFFU 1512 #define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) 1513 #define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU 1514 #define EFUSE_KEY2_DATA2_S 0 1515 1516 /** EFUSE_RD_KEY2_DATA3_REG register 1517 * Register 3 of BLOCK6 (KEY2). 1518 */ 1519 #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) 1520 /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; 1521 * Stores the third 32 bits of KEY2. 1522 */ 1523 #define EFUSE_KEY2_DATA3 0xFFFFFFFFU 1524 #define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) 1525 #define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU 1526 #define EFUSE_KEY2_DATA3_S 0 1527 1528 /** EFUSE_RD_KEY2_DATA4_REG register 1529 * Register 4 of BLOCK6 (KEY2). 1530 */ 1531 #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) 1532 /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; 1533 * Stores the fourth 32 bits of KEY2. 1534 */ 1535 #define EFUSE_KEY2_DATA4 0xFFFFFFFFU 1536 #define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) 1537 #define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU 1538 #define EFUSE_KEY2_DATA4_S 0 1539 1540 /** EFUSE_RD_KEY2_DATA5_REG register 1541 * Register 5 of BLOCK6 (KEY2). 1542 */ 1543 #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) 1544 /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; 1545 * Stores the fifth 32 bits of KEY2. 1546 */ 1547 #define EFUSE_KEY2_DATA5 0xFFFFFFFFU 1548 #define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) 1549 #define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU 1550 #define EFUSE_KEY2_DATA5_S 0 1551 1552 /** EFUSE_RD_KEY2_DATA6_REG register 1553 * Register 6 of BLOCK6 (KEY2). 1554 */ 1555 #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) 1556 /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; 1557 * Stores the sixth 32 bits of KEY2. 1558 */ 1559 #define EFUSE_KEY2_DATA6 0xFFFFFFFFU 1560 #define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) 1561 #define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU 1562 #define EFUSE_KEY2_DATA6_S 0 1563 1564 /** EFUSE_RD_KEY2_DATA7_REG register 1565 * Register 7 of BLOCK6 (KEY2). 1566 */ 1567 #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) 1568 /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; 1569 * Stores the seventh 32 bits of KEY2. 1570 */ 1571 #define EFUSE_KEY2_DATA7 0xFFFFFFFFU 1572 #define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) 1573 #define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU 1574 #define EFUSE_KEY2_DATA7_S 0 1575 1576 /** EFUSE_RD_KEY3_DATA0_REG register 1577 * Register 0 of BLOCK7 (KEY3). 1578 */ 1579 #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) 1580 /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; 1581 * Stores the zeroth 32 bits of KEY3. 1582 */ 1583 #define EFUSE_KEY3_DATA0 0xFFFFFFFFU 1584 #define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) 1585 #define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU 1586 #define EFUSE_KEY3_DATA0_S 0 1587 1588 /** EFUSE_RD_KEY3_DATA1_REG register 1589 * Register 1 of BLOCK7 (KEY3). 1590 */ 1591 #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) 1592 /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; 1593 * Stores the first 32 bits of KEY3. 1594 */ 1595 #define EFUSE_KEY3_DATA1 0xFFFFFFFFU 1596 #define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) 1597 #define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU 1598 #define EFUSE_KEY3_DATA1_S 0 1599 1600 /** EFUSE_RD_KEY3_DATA2_REG register 1601 * Register 2 of BLOCK7 (KEY3). 1602 */ 1603 #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) 1604 /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; 1605 * Stores the second 32 bits of KEY3. 1606 */ 1607 #define EFUSE_KEY3_DATA2 0xFFFFFFFFU 1608 #define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) 1609 #define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU 1610 #define EFUSE_KEY3_DATA2_S 0 1611 1612 /** EFUSE_RD_KEY3_DATA3_REG register 1613 * Register 3 of BLOCK7 (KEY3). 1614 */ 1615 #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) 1616 /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; 1617 * Stores the third 32 bits of KEY3. 1618 */ 1619 #define EFUSE_KEY3_DATA3 0xFFFFFFFFU 1620 #define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) 1621 #define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU 1622 #define EFUSE_KEY3_DATA3_S 0 1623 1624 /** EFUSE_RD_KEY3_DATA4_REG register 1625 * Register 4 of BLOCK7 (KEY3). 1626 */ 1627 #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) 1628 /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; 1629 * Stores the fourth 32 bits of KEY3. 1630 */ 1631 #define EFUSE_KEY3_DATA4 0xFFFFFFFFU 1632 #define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) 1633 #define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU 1634 #define EFUSE_KEY3_DATA4_S 0 1635 1636 /** EFUSE_RD_KEY3_DATA5_REG register 1637 * Register 5 of BLOCK7 (KEY3). 1638 */ 1639 #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) 1640 /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; 1641 * Stores the fifth 32 bits of KEY3. 1642 */ 1643 #define EFUSE_KEY3_DATA5 0xFFFFFFFFU 1644 #define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) 1645 #define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU 1646 #define EFUSE_KEY3_DATA5_S 0 1647 1648 /** EFUSE_RD_KEY3_DATA6_REG register 1649 * Register 6 of BLOCK7 (KEY3). 1650 */ 1651 #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) 1652 /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; 1653 * Stores the sixth 32 bits of KEY3. 1654 */ 1655 #define EFUSE_KEY3_DATA6 0xFFFFFFFFU 1656 #define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) 1657 #define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU 1658 #define EFUSE_KEY3_DATA6_S 0 1659 1660 /** EFUSE_RD_KEY3_DATA7_REG register 1661 * Register 7 of BLOCK7 (KEY3). 1662 */ 1663 #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) 1664 /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; 1665 * Stores the seventh 32 bits of KEY3. 1666 */ 1667 #define EFUSE_KEY3_DATA7 0xFFFFFFFFU 1668 #define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) 1669 #define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU 1670 #define EFUSE_KEY3_DATA7_S 0 1671 1672 /** EFUSE_RD_KEY4_DATA0_REG register 1673 * Register 0 of BLOCK8 (KEY4). 1674 */ 1675 #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) 1676 /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; 1677 * Stores the zeroth 32 bits of KEY4. 1678 */ 1679 #define EFUSE_KEY4_DATA0 0xFFFFFFFFU 1680 #define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) 1681 #define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU 1682 #define EFUSE_KEY4_DATA0_S 0 1683 1684 /** EFUSE_RD_KEY4_DATA1_REG register 1685 * Register 1 of BLOCK8 (KEY4). 1686 */ 1687 #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) 1688 /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; 1689 * Stores the first 32 bits of KEY4. 1690 */ 1691 #define EFUSE_KEY4_DATA1 0xFFFFFFFFU 1692 #define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) 1693 #define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU 1694 #define EFUSE_KEY4_DATA1_S 0 1695 1696 /** EFUSE_RD_KEY4_DATA2_REG register 1697 * Register 2 of BLOCK8 (KEY4). 1698 */ 1699 #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) 1700 /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; 1701 * Stores the second 32 bits of KEY4. 1702 */ 1703 #define EFUSE_KEY4_DATA2 0xFFFFFFFFU 1704 #define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) 1705 #define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU 1706 #define EFUSE_KEY4_DATA2_S 0 1707 1708 /** EFUSE_RD_KEY4_DATA3_REG register 1709 * Register 3 of BLOCK8 (KEY4). 1710 */ 1711 #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) 1712 /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; 1713 * Stores the third 32 bits of KEY4. 1714 */ 1715 #define EFUSE_KEY4_DATA3 0xFFFFFFFFU 1716 #define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) 1717 #define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU 1718 #define EFUSE_KEY4_DATA3_S 0 1719 1720 /** EFUSE_RD_KEY4_DATA4_REG register 1721 * Register 4 of BLOCK8 (KEY4). 1722 */ 1723 #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) 1724 /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; 1725 * Stores the fourth 32 bits of KEY4. 1726 */ 1727 #define EFUSE_KEY4_DATA4 0xFFFFFFFFU 1728 #define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) 1729 #define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU 1730 #define EFUSE_KEY4_DATA4_S 0 1731 1732 /** EFUSE_RD_KEY4_DATA5_REG register 1733 * Register 5 of BLOCK8 (KEY4). 1734 */ 1735 #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) 1736 /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; 1737 * Stores the fifth 32 bits of KEY4. 1738 */ 1739 #define EFUSE_KEY4_DATA5 0xFFFFFFFFU 1740 #define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) 1741 #define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU 1742 #define EFUSE_KEY4_DATA5_S 0 1743 1744 /** EFUSE_RD_KEY4_DATA6_REG register 1745 * Register 6 of BLOCK8 (KEY4). 1746 */ 1747 #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) 1748 /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; 1749 * Stores the sixth 32 bits of KEY4. 1750 */ 1751 #define EFUSE_KEY4_DATA6 0xFFFFFFFFU 1752 #define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) 1753 #define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU 1754 #define EFUSE_KEY4_DATA6_S 0 1755 1756 /** EFUSE_RD_KEY4_DATA7_REG register 1757 * Register 7 of BLOCK8 (KEY4). 1758 */ 1759 #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) 1760 /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; 1761 * Stores the seventh 32 bits of KEY4. 1762 */ 1763 #define EFUSE_KEY4_DATA7 0xFFFFFFFFU 1764 #define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) 1765 #define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU 1766 #define EFUSE_KEY4_DATA7_S 0 1767 1768 /** EFUSE_RD_KEY5_DATA0_REG register 1769 * Register 0 of BLOCK9 (KEY5). 1770 */ 1771 #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) 1772 /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; 1773 * Stores the zeroth 32 bits of KEY5. 1774 */ 1775 #define EFUSE_KEY5_DATA0 0xFFFFFFFFU 1776 #define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) 1777 #define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU 1778 #define EFUSE_KEY5_DATA0_S 0 1779 1780 /** EFUSE_RD_KEY5_DATA1_REG register 1781 * Register 1 of BLOCK9 (KEY5). 1782 */ 1783 #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) 1784 /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; 1785 * Stores the first 32 bits of KEY5. 1786 */ 1787 #define EFUSE_KEY5_DATA1 0xFFFFFFFFU 1788 #define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) 1789 #define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU 1790 #define EFUSE_KEY5_DATA1_S 0 1791 1792 /** EFUSE_RD_KEY5_DATA2_REG register 1793 * Register 2 of BLOCK9 (KEY5). 1794 */ 1795 #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) 1796 /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; 1797 * Stores the second 32 bits of KEY5. 1798 */ 1799 #define EFUSE_KEY5_DATA2 0xFFFFFFFFU 1800 #define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) 1801 #define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU 1802 #define EFUSE_KEY5_DATA2_S 0 1803 1804 /** EFUSE_RD_KEY5_DATA3_REG register 1805 * Register 3 of BLOCK9 (KEY5). 1806 */ 1807 #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) 1808 /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; 1809 * Stores the third 32 bits of KEY5. 1810 */ 1811 #define EFUSE_KEY5_DATA3 0xFFFFFFFFU 1812 #define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) 1813 #define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU 1814 #define EFUSE_KEY5_DATA3_S 0 1815 1816 /** EFUSE_RD_KEY5_DATA4_REG register 1817 * Register 4 of BLOCK9 (KEY5). 1818 */ 1819 #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) 1820 /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; 1821 * Stores the fourth 32 bits of KEY5. 1822 */ 1823 #define EFUSE_KEY5_DATA4 0xFFFFFFFFU 1824 #define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) 1825 #define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU 1826 #define EFUSE_KEY5_DATA4_S 0 1827 1828 /** EFUSE_RD_KEY5_DATA5_REG register 1829 * Register 5 of BLOCK9 (KEY5). 1830 */ 1831 #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) 1832 /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; 1833 * Stores the fifth 32 bits of KEY5. 1834 */ 1835 #define EFUSE_KEY5_DATA5 0xFFFFFFFFU 1836 #define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) 1837 #define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU 1838 #define EFUSE_KEY5_DATA5_S 0 1839 1840 /** EFUSE_RD_KEY5_DATA6_REG register 1841 * Register 6 of BLOCK9 (KEY5). 1842 */ 1843 #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) 1844 /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; 1845 * Stores the sixth 32 bits of KEY5. 1846 */ 1847 #define EFUSE_KEY5_DATA6 0xFFFFFFFFU 1848 #define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) 1849 #define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU 1850 #define EFUSE_KEY5_DATA6_S 0 1851 1852 /** EFUSE_RD_KEY5_DATA7_REG register 1853 * Register 7 of BLOCK9 (KEY5). 1854 */ 1855 #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) 1856 /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; 1857 * Stores the seventh 32 bits of KEY5. 1858 */ 1859 #define EFUSE_KEY5_DATA7 0xFFFFFFFFU 1860 #define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) 1861 #define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU 1862 #define EFUSE_KEY5_DATA7_S 0 1863 1864 /** EFUSE_RD_SYS_PART2_DATA0_REG register 1865 * Register 0 of BLOCK10 (system). 1866 */ 1867 #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) 1868 /** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; 1869 * Stores the 0th 32 bits of the 2nd part of system data. 1870 */ 1871 #define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU 1872 #define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) 1873 #define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU 1874 #define EFUSE_SYS_DATA_PART2_0_S 0 1875 1876 /** EFUSE_RD_SYS_PART2_DATA1_REG register 1877 * Register 1 of BLOCK9 (KEY5). 1878 */ 1879 #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) 1880 /** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; 1881 * Stores the 1st 32 bits of the 2nd part of system data. 1882 */ 1883 #define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU 1884 #define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) 1885 #define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU 1886 #define EFUSE_SYS_DATA_PART2_1_S 0 1887 1888 /** EFUSE_RD_SYS_PART2_DATA2_REG register 1889 * Register 2 of BLOCK10 (system). 1890 */ 1891 #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) 1892 /** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; 1893 * Stores the 2nd 32 bits of the 2nd part of system data. 1894 */ 1895 #define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU 1896 #define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) 1897 #define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU 1898 #define EFUSE_SYS_DATA_PART2_2_S 0 1899 1900 /** EFUSE_RD_SYS_PART2_DATA3_REG register 1901 * Register 3 of BLOCK10 (system). 1902 */ 1903 #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) 1904 /** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; 1905 * Stores the 3rd 32 bits of the 2nd part of system data. 1906 */ 1907 #define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU 1908 #define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) 1909 #define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU 1910 #define EFUSE_SYS_DATA_PART2_3_S 0 1911 1912 /** EFUSE_RD_SYS_PART2_DATA4_REG register 1913 * Register 4 of BLOCK10 (system). 1914 */ 1915 #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) 1916 /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; 1917 * Stores the 4th 32 bits of the 2nd part of system data. 1918 */ 1919 #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU 1920 #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) 1921 #define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU 1922 #define EFUSE_SYS_DATA_PART2_4_S 0 1923 1924 /** EFUSE_RD_SYS_PART2_DATA5_REG register 1925 * Register 5 of BLOCK10 (system). 1926 */ 1927 #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) 1928 /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; 1929 * Stores the 5th 32 bits of the 2nd part of system data. 1930 */ 1931 #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU 1932 #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) 1933 #define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU 1934 #define EFUSE_SYS_DATA_PART2_5_S 0 1935 1936 /** EFUSE_RD_SYS_PART2_DATA6_REG register 1937 * Register 6 of BLOCK10 (system). 1938 */ 1939 #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) 1940 /** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; 1941 * Stores the 6th 32 bits of the 2nd part of system data. 1942 */ 1943 #define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU 1944 #define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) 1945 #define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU 1946 #define EFUSE_SYS_DATA_PART2_6_S 0 1947 1948 /** EFUSE_RD_SYS_PART2_DATA7_REG register 1949 * Register 7 of BLOCK10 (system). 1950 */ 1951 #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) 1952 /** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; 1953 * Stores the 7th 32 bits of the 2nd part of system data. 1954 */ 1955 #define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU 1956 #define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) 1957 #define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU 1958 #define EFUSE_SYS_DATA_PART2_7_S 0 1959 1960 /** EFUSE_RD_REPEAT_ERR0_REG register 1961 * Programming error record register 0 of BLOCK0. 1962 */ 1963 #define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) 1964 /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; 1965 * If any bits in this filed are 1, then it indicates a programming error. 1966 */ 1967 #define EFUSE_RD_DIS_ERR 0x0000007FU 1968 #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) 1969 #define EFUSE_RD_DIS_ERR_V 0x0000007FU 1970 #define EFUSE_RD_DIS_ERR_S 0 1971 /** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; 1972 * If any bits in this filed are 1, then it indicates a programming error. 1973 */ 1974 #define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) 1975 #define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) 1976 #define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001U 1977 #define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 1978 /** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; 1979 * If any bits in this filed are 1, then it indicates a programming error. 1980 */ 1981 #define EFUSE_DIS_ICACHE_ERR (BIT(8)) 1982 #define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) 1983 #define EFUSE_DIS_ICACHE_ERR_V 0x00000001U 1984 #define EFUSE_DIS_ICACHE_ERR_S 8 1985 /** EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; 1986 * If any bits in this filed are 1, then it indicates a programming error. 1987 */ 1988 #define EFUSE_DIS_DCACHE_ERR (BIT(9)) 1989 #define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) 1990 #define EFUSE_DIS_DCACHE_ERR_V 0x00000001U 1991 #define EFUSE_DIS_DCACHE_ERR_S 9 1992 /** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; 1993 * If any bits in this filed are 1, then it indicates a programming error. 1994 */ 1995 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) 1996 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) 1997 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U 1998 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 1999 /** EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; 2000 * If any bits in this filed are 1, then it indicates a programming error. 2001 */ 2002 #define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) 2003 #define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) 2004 #define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001U 2005 #define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 2006 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; 2007 * If any bits in this filed are 1, then it indicates a programming error. 2008 */ 2009 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) 2010 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) 2011 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U 2012 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 2013 /** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; 2014 * If any bits in this filed are 1, then it indicates a programming error. 2015 */ 2016 #define EFUSE_DIS_USB_ERR (BIT(13)) 2017 #define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) 2018 #define EFUSE_DIS_USB_ERR_V 0x00000001U 2019 #define EFUSE_DIS_USB_ERR_S 13 2020 /** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; 2021 * If any bits in this filed are 1, then it indicates a programming error. 2022 */ 2023 #define EFUSE_DIS_CAN_ERR (BIT(14)) 2024 #define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) 2025 #define EFUSE_DIS_CAN_ERR_V 0x00000001U 2026 #define EFUSE_DIS_CAN_ERR_S 14 2027 /** EFUSE_DIS_APP_CPU_ERR : RO; bitpos: [15]; default: 0; 2028 * If any bits in this filed are 1, then it indicates a programming error. 2029 */ 2030 #define EFUSE_DIS_APP_CPU_ERR (BIT(15)) 2031 #define EFUSE_DIS_APP_CPU_ERR_M (EFUSE_DIS_APP_CPU_ERR_V << EFUSE_DIS_APP_CPU_ERR_S) 2032 #define EFUSE_DIS_APP_CPU_ERR_V 0x00000001U 2033 #define EFUSE_DIS_APP_CPU_ERR_S 15 2034 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; 2035 * If any bits in this filed are 1, then it indicates a programming error. 2036 */ 2037 #define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U 2038 #define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) 2039 #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U 2040 #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 2041 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; 2042 * If any bits in this filed are 1, then it indicates a programming error. 2043 */ 2044 #define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) 2045 #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) 2046 #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U 2047 #define EFUSE_DIS_PAD_JTAG_ERR_S 19 2048 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; 2049 * If any bits in this filed are 1, then it indicates a programming error. 2050 */ 2051 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) 2052 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) 2053 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U 2054 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 2055 /** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; 2056 * If any bits in this filed are 1, then it indicates a programming error. 2057 */ 2058 #define EFUSE_USB_DREFH_ERR 0x00000003U 2059 #define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) 2060 #define EFUSE_USB_DREFH_ERR_V 0x00000003U 2061 #define EFUSE_USB_DREFH_ERR_S 21 2062 /** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; 2063 * If any bits in this filed are 1, then it indicates a programming error. 2064 */ 2065 #define EFUSE_USB_DREFL_ERR 0x00000003U 2066 #define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) 2067 #define EFUSE_USB_DREFL_ERR_V 0x00000003U 2068 #define EFUSE_USB_DREFL_ERR_S 23 2069 /** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; 2070 * If any bits in this filed are 1, then it indicates a programming error. 2071 */ 2072 #define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) 2073 #define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) 2074 #define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U 2075 #define EFUSE_USB_EXCHG_PINS_ERR_S 25 2076 /** EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [26]; default: 0; 2077 * If any bits in this filed are 1, then it indicates a programming error. 2078 */ 2079 #define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) 2080 #define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) 2081 #define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001U 2082 #define EFUSE_EXT_PHY_ENABLE_ERR_S 26 2083 /** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0; 2084 * If any bits in this filed are 1, then it indicates a programming error. 2085 */ 2086 #define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003U 2087 #define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S) 2088 #define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003U 2089 #define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 2090 /** EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; 2091 * If any bits in this filed are 1, then it indicates a programming error. 2092 */ 2093 #define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) 2094 #define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) 2095 #define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001U 2096 #define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 2097 /** EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; 2098 * If any bits in this filed are 1, then it indicates a programming error. 2099 */ 2100 #define EFUSE_VDD_SPI_DREFH_ERR 0x00000003U 2101 #define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) 2102 #define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003U 2103 #define EFUSE_VDD_SPI_DREFH_ERR_S 30 2104 2105 /** EFUSE_RD_REPEAT_ERR1_REG register 2106 * Programming error record register 1 of BLOCK0. 2107 */ 2108 #define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) 2109 /** EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; 2110 * If any bits in this filed are 1, then it indicates a programming error. 2111 */ 2112 #define EFUSE_VDD_SPI_DREFM_ERR 0x00000003U 2113 #define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) 2114 #define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003U 2115 #define EFUSE_VDD_SPI_DREFM_ERR_S 0 2116 /** EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; 2117 * If any bits in this filed are 1, then it indicates a programming error. 2118 */ 2119 #define EFUSE_VDD_SPI_DREFL_ERR 0x00000003U 2120 #define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) 2121 #define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003U 2122 #define EFUSE_VDD_SPI_DREFL_ERR_S 2 2123 /** EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; 2124 * If any bits in this filed are 1, then it indicates a programming error. 2125 */ 2126 #define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) 2127 #define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) 2128 #define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001U 2129 #define EFUSE_VDD_SPI_XPD_ERR_S 4 2130 /** EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; 2131 * If any bits in this filed are 1, then it indicates a programming error. 2132 */ 2133 #define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) 2134 #define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) 2135 #define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001U 2136 #define EFUSE_VDD_SPI_TIEH_ERR_S 5 2137 /** EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; 2138 * If any bits in this filed are 1, then it indicates a programming error. 2139 */ 2140 #define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) 2141 #define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) 2142 #define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001U 2143 #define EFUSE_VDD_SPI_FORCE_ERR_S 6 2144 /** EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; 2145 * If any bits in this filed are 1, then it indicates a programming error. 2146 */ 2147 #define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) 2148 #define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) 2149 #define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001U 2150 #define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 2151 /** EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; 2152 * If any bits in this filed are 1, then it indicates a programming error. 2153 */ 2154 #define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) 2155 #define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) 2156 #define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001U 2157 #define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 2158 /** EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; 2159 * If any bits in this filed are 1, then it indicates a programming error. 2160 */ 2161 #define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007U 2162 #define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) 2163 #define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007U 2164 #define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 2165 /** EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; 2166 * If any bits in this filed are 1, then it indicates a programming error. 2167 */ 2168 #define EFUSE_VDD_SPI_INIT_ERR 0x00000003U 2169 #define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) 2170 #define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003U 2171 #define EFUSE_VDD_SPI_INIT_ERR_S 12 2172 /** EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; 2173 * If any bits in this filed are 1, then it indicates a programming error. 2174 */ 2175 #define EFUSE_VDD_SPI_DCAP_ERR 0x00000003U 2176 #define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) 2177 #define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003U 2178 #define EFUSE_VDD_SPI_DCAP_ERR_S 14 2179 /** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; 2180 * If any bits in this filed are 1, then it indicates a programming error. 2181 */ 2182 #define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U 2183 #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) 2184 #define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U 2185 #define EFUSE_WDT_DELAY_SEL_ERR_S 16 2186 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; 2187 * If any bits in this filed are 1, then it indicates a programming error. 2188 */ 2189 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U 2190 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) 2191 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U 2192 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 2193 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; 2194 * If any bits in this filed are 1, then it indicates a programming error. 2195 */ 2196 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) 2197 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) 2198 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U 2199 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 2200 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; 2201 * If any bits in this filed are 1, then it indicates a programming error. 2202 */ 2203 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) 2204 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) 2205 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U 2206 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 2207 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; 2208 * If any bits in this filed are 1, then it indicates a programming error. 2209 */ 2210 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) 2211 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) 2212 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U 2213 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 2214 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; 2215 * If any bits in this filed are 1, then it indicates a programming error. 2216 */ 2217 #define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU 2218 #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) 2219 #define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU 2220 #define EFUSE_KEY_PURPOSE_0_ERR_S 24 2221 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; 2222 * If any bits in this filed are 1, then it indicates a programming error. 2223 */ 2224 #define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU 2225 #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) 2226 #define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU 2227 #define EFUSE_KEY_PURPOSE_1_ERR_S 28 2228 2229 /** EFUSE_RD_REPEAT_ERR2_REG register 2230 * Programming error record register 2 of BLOCK0. 2231 */ 2232 #define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) 2233 /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; 2234 * If any bits in this filed are 1, then it indicates a programming error. 2235 */ 2236 #define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU 2237 #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) 2238 #define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU 2239 #define EFUSE_KEY_PURPOSE_2_ERR_S 0 2240 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; 2241 * If any bits in this filed are 1, then it indicates a programming error. 2242 */ 2243 #define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU 2244 #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) 2245 #define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU 2246 #define EFUSE_KEY_PURPOSE_3_ERR_S 4 2247 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; 2248 * If any bits in this filed are 1, then it indicates a programming error. 2249 */ 2250 #define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU 2251 #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) 2252 #define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU 2253 #define EFUSE_KEY_PURPOSE_4_ERR_S 8 2254 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; 2255 * If any bits in this filed are 1, then it indicates a programming error. 2256 */ 2257 #define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU 2258 #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) 2259 #define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU 2260 #define EFUSE_KEY_PURPOSE_5_ERR_S 12 2261 /** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [19:16]; default: 0; 2262 * If any bits in this filed are 1, then it indicates a programming error. 2263 */ 2264 #define EFUSE_RPT4_RESERVED0_ERR 0x0000000FU 2265 #define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) 2266 #define EFUSE_RPT4_RESERVED0_ERR_V 0x0000000FU 2267 #define EFUSE_RPT4_RESERVED0_ERR_S 16 2268 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; 2269 * If any bits in this filed are 1, then it indicates a programming error. 2270 */ 2271 #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) 2272 #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) 2273 #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U 2274 #define EFUSE_SECURE_BOOT_EN_ERR_S 20 2275 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; 2276 * If any bits in this filed are 1, then it indicates a programming error. 2277 */ 2278 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) 2279 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) 2280 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U 2281 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 2282 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [22]; default: 0; 2283 * If any bits in this filed are 1, then it indicates a programming error. 2284 */ 2285 #define EFUSE_DIS_USB_JTAG_ERR (BIT(22)) 2286 #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) 2287 #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U 2288 #define EFUSE_DIS_USB_JTAG_ERR_S 22 2289 /** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [23]; default: 0; 2290 * If any bits in this filed are 1, then it indicates a programming error. 2291 */ 2292 #define EFUSE_DIS_USB_DEVICE_ERR (BIT(23)) 2293 #define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S) 2294 #define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001U 2295 #define EFUSE_DIS_USB_DEVICE_ERR_S 23 2296 /** EFUSE_STRAP_JTAG_SEL_ERR : RO; bitpos: [24]; default: 0; 2297 * If any bits in this filed are 1, then it indicates a programming error. 2298 */ 2299 #define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24)) 2300 #define EFUSE_STRAP_JTAG_SEL_ERR_M (EFUSE_STRAP_JTAG_SEL_ERR_V << EFUSE_STRAP_JTAG_SEL_ERR_S) 2301 #define EFUSE_STRAP_JTAG_SEL_ERR_V 0x00000001U 2302 #define EFUSE_STRAP_JTAG_SEL_ERR_S 24 2303 /** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0; 2304 * If any bits in this filed are 1, then it indicates a programming error. 2305 */ 2306 #define EFUSE_USB_PHY_SEL_ERR (BIT(25)) 2307 #define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S) 2308 #define EFUSE_USB_PHY_SEL_ERR_V 0x00000001U 2309 #define EFUSE_USB_PHY_SEL_ERR_S 25 2310 /** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [27:26]; default: 0; 2311 * If any bits in this filed are 1, then it indicates a programming error. 2312 */ 2313 #define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003U 2314 #define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S) 2315 #define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003U 2316 #define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26 2317 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; 2318 * If any bits in this filed are 1, then it indicates a programming error. 2319 */ 2320 #define EFUSE_FLASH_TPUW_ERR 0x0000000FU 2321 #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) 2322 #define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU 2323 #define EFUSE_FLASH_TPUW_ERR_S 28 2324 2325 /** EFUSE_RD_REPEAT_ERR3_REG register 2326 * Programming error record register 3 of BLOCK0. 2327 */ 2328 #define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) 2329 /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; 2330 * If any bits in this filed are 1, then it indicates a programming error. 2331 */ 2332 #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) 2333 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) 2334 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U 2335 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 2336 /** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; 2337 * If any bits in this filed are 1, then it indicates a programming error. 2338 */ 2339 #define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) 2340 #define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) 2341 #define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001U 2342 #define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 2343 /** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; 2344 * If any bits in this filed are 1, then it indicates a programming error. 2345 */ 2346 #define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) 2347 #define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) 2348 #define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001U 2349 #define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 2350 /** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0; 2351 * If any bits in this filed are 1, then it indicates a programming error. 2352 */ 2353 #define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) 2354 #define EFUSE_FLASH_ECC_MODE_ERR_M (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S) 2355 #define EFUSE_FLASH_ECC_MODE_ERR_V 0x00000001U 2356 #define EFUSE_FLASH_ECC_MODE_ERR_S 3 2357 /** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; 2358 * If any bits in this filed are 1, then it indicates a programming error. 2359 */ 2360 #define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) 2361 #define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) 2362 #define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001U 2363 #define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 2364 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; 2365 * If any bits in this filed are 1, then it indicates a programming error. 2366 */ 2367 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) 2368 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) 2369 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U 2370 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 2371 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; 2372 * If any bits in this filed are 1, then it indicates a programming error. 2373 */ 2374 #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U 2375 #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) 2376 #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U 2377 #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 2378 /** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; 2379 * If any bits in this filed are 1, then it indicates a programming error. 2380 */ 2381 #define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) 2382 #define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) 2383 #define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001U 2384 #define EFUSE_PIN_POWER_SELECTION_ERR_S 8 2385 /** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; 2386 * If any bits in this filed are 1, then it indicates a programming error. 2387 */ 2388 #define EFUSE_FLASH_TYPE_ERR (BIT(9)) 2389 #define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) 2390 #define EFUSE_FLASH_TYPE_ERR_V 0x00000001U 2391 #define EFUSE_FLASH_TYPE_ERR_S 9 2392 /** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0; 2393 * If any bits in this filed are 1, then it indicates a programming error. 2394 */ 2395 #define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U 2396 #define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) 2397 #define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U 2398 #define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 2399 /** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0; 2400 * If any bits in this filed are 1, then it indicates a programming error. 2401 */ 2402 #define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) 2403 #define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) 2404 #define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U 2405 #define EFUSE_FLASH_ECC_EN_ERR_S 12 2406 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; 2407 * If any bits in this filed are 1, then it indicates a programming error. 2408 */ 2409 #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) 2410 #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) 2411 #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U 2412 #define EFUSE_FORCE_SEND_RESUME_ERR_S 13 2413 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; 2414 * If any bits in this filed are 1, then it indicates a programming error. 2415 */ 2416 #define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU 2417 #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) 2418 #define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU 2419 #define EFUSE_SECURE_VERSION_ERR_S 14 2420 /** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [30]; default: 0; 2421 * If any bits in this filed are 1, then it indicates a programming error. 2422 */ 2423 #define EFUSE_POWERGLITCH_EN_ERR (BIT(30)) 2424 #define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) 2425 #define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U 2426 #define EFUSE_POWERGLITCH_EN_ERR_S 30 2427 /** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31]; default: 0; 2428 * Reserved. 2429 */ 2430 #define EFUSE_RPT4_RESERVED1_ERR (BIT(31)) 2431 #define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) 2432 #define EFUSE_RPT4_RESERVED1_ERR_V 0x00000001U 2433 #define EFUSE_RPT4_RESERVED1_ERR_S 31 2434 2435 /** EFUSE_RD_REPEAT_ERR4_REG register 2436 * Programming error record register 4 of BLOCK0. 2437 */ 2438 #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) 2439 /** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [23:0]; default: 0; 2440 * If any bits in this filed are 1, then it indicates a programming error. 2441 */ 2442 #define EFUSE_RPT4_RESERVED2_ERR 0x00FFFFFFU 2443 #define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) 2444 #define EFUSE_RPT4_RESERVED2_ERR_V 0x00FFFFFFU 2445 #define EFUSE_RPT4_RESERVED2_ERR_S 0 2446 2447 /** EFUSE_RD_RS_ERR0_REG register 2448 * Programming error record register 0 of BLOCK1-10. 2449 */ 2450 #define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) 2451 /** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; 2452 * The value of this signal means the number of error bytes. 2453 */ 2454 #define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U 2455 #define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) 2456 #define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U 2457 #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 2458 /** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; 2459 * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that 2460 * programming user data failed and the number of error bytes is over 6. 2461 */ 2462 #define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) 2463 #define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) 2464 #define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U 2465 #define EFUSE_MAC_SPI_8M_FAIL_S 3 2466 /** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; 2467 * The value of this signal means the number of error bytes. 2468 */ 2469 #define EFUSE_SYS_PART1_NUM 0x00000007U 2470 #define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) 2471 #define EFUSE_SYS_PART1_NUM_V 0x00000007U 2472 #define EFUSE_SYS_PART1_NUM_S 4 2473 /** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; 2474 * 0: Means no failure and that the data of system part1 is reliable 1: Means that 2475 * programming user data failed and the number of error bytes is over 6. 2476 */ 2477 #define EFUSE_SYS_PART1_FAIL (BIT(7)) 2478 #define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) 2479 #define EFUSE_SYS_PART1_FAIL_V 0x00000001U 2480 #define EFUSE_SYS_PART1_FAIL_S 7 2481 /** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; 2482 * The value of this signal means the number of error bytes. 2483 */ 2484 #define EFUSE_USR_DATA_ERR_NUM 0x00000007U 2485 #define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) 2486 #define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U 2487 #define EFUSE_USR_DATA_ERR_NUM_S 8 2488 /** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; 2489 * 0: Means no failure and that the user data is reliable 1: Means that programming 2490 * user data failed and the number of error bytes is over 6. 2491 */ 2492 #define EFUSE_USR_DATA_FAIL (BIT(11)) 2493 #define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) 2494 #define EFUSE_USR_DATA_FAIL_V 0x00000001U 2495 #define EFUSE_USR_DATA_FAIL_S 11 2496 /** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; 2497 * The value of this signal means the number of error bytes. 2498 */ 2499 #define EFUSE_KEY0_ERR_NUM 0x00000007U 2500 #define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) 2501 #define EFUSE_KEY0_ERR_NUM_V 0x00000007U 2502 #define EFUSE_KEY0_ERR_NUM_S 12 2503 /** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; 2504 * 0: Means no failure and that the data of key0 is reliable 1: Means that programming 2505 * key0 failed and the number of error bytes is over 6. 2506 */ 2507 #define EFUSE_KEY0_FAIL (BIT(15)) 2508 #define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) 2509 #define EFUSE_KEY0_FAIL_V 0x00000001U 2510 #define EFUSE_KEY0_FAIL_S 15 2511 /** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; 2512 * The value of this signal means the number of error bytes. 2513 */ 2514 #define EFUSE_KEY1_ERR_NUM 0x00000007U 2515 #define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) 2516 #define EFUSE_KEY1_ERR_NUM_V 0x00000007U 2517 #define EFUSE_KEY1_ERR_NUM_S 16 2518 /** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; 2519 * 0: Means no failure and that the data of key1 is reliable 1: Means that programming 2520 * key1 failed and the number of error bytes is over 6. 2521 */ 2522 #define EFUSE_KEY1_FAIL (BIT(19)) 2523 #define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) 2524 #define EFUSE_KEY1_FAIL_V 0x00000001U 2525 #define EFUSE_KEY1_FAIL_S 19 2526 /** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; 2527 * The value of this signal means the number of error bytes. 2528 */ 2529 #define EFUSE_KEY2_ERR_NUM 0x00000007U 2530 #define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) 2531 #define EFUSE_KEY2_ERR_NUM_V 0x00000007U 2532 #define EFUSE_KEY2_ERR_NUM_S 20 2533 /** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; 2534 * 0: Means no failure and that the data of key2 is reliable 1: Means that programming 2535 * key2 failed and the number of error bytes is over 6. 2536 */ 2537 #define EFUSE_KEY2_FAIL (BIT(23)) 2538 #define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) 2539 #define EFUSE_KEY2_FAIL_V 0x00000001U 2540 #define EFUSE_KEY2_FAIL_S 23 2541 /** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; 2542 * The value of this signal means the number of error bytes. 2543 */ 2544 #define EFUSE_KEY3_ERR_NUM 0x00000007U 2545 #define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) 2546 #define EFUSE_KEY3_ERR_NUM_V 0x00000007U 2547 #define EFUSE_KEY3_ERR_NUM_S 24 2548 /** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; 2549 * 0: Means no failure and that the data of key3 is reliable 1: Means that programming 2550 * key3 failed and the number of error bytes is over 6. 2551 */ 2552 #define EFUSE_KEY3_FAIL (BIT(27)) 2553 #define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) 2554 #define EFUSE_KEY3_FAIL_V 0x00000001U 2555 #define EFUSE_KEY3_FAIL_S 27 2556 /** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; 2557 * The value of this signal means the number of error bytes. 2558 */ 2559 #define EFUSE_KEY4_ERR_NUM 0x00000007U 2560 #define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) 2561 #define EFUSE_KEY4_ERR_NUM_V 0x00000007U 2562 #define EFUSE_KEY4_ERR_NUM_S 28 2563 /** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; 2564 * 0: Means no failure and that the data of key4 is reliable 1: Means that programming 2565 * key4 failed and the number of error bytes is over 6. 2566 */ 2567 #define EFUSE_KEY4_FAIL (BIT(31)) 2568 #define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) 2569 #define EFUSE_KEY4_FAIL_V 0x00000001U 2570 #define EFUSE_KEY4_FAIL_S 31 2571 2572 /** EFUSE_RD_RS_ERR1_REG register 2573 * Programming error record register 1 of BLOCK1-10. 2574 */ 2575 #define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) 2576 /** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; 2577 * The value of this signal means the number of error bytes. 2578 */ 2579 #define EFUSE_KEY5_ERR_NUM 0x00000007U 2580 #define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) 2581 #define EFUSE_KEY5_ERR_NUM_V 0x00000007U 2582 #define EFUSE_KEY5_ERR_NUM_S 0 2583 /** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; 2584 * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming 2585 * user data failed and the number of error bytes is over 6. 2586 */ 2587 #define EFUSE_KEY5_FAIL (BIT(3)) 2588 #define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) 2589 #define EFUSE_KEY5_FAIL_V 0x00000001U 2590 #define EFUSE_KEY5_FAIL_S 3 2591 /** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; 2592 * The value of this signal means the number of error bytes. 2593 */ 2594 #define EFUSE_SYS_PART2_ERR_NUM 0x00000007U 2595 #define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) 2596 #define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U 2597 #define EFUSE_SYS_PART2_ERR_NUM_S 4 2598 /** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; 2599 * 0: Means no failure and that the data of system part2 is reliable 1: Means that 2600 * programming user data failed and the number of error bytes is over 6. 2601 */ 2602 #define EFUSE_SYS_PART2_FAIL (BIT(7)) 2603 #define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) 2604 #define EFUSE_SYS_PART2_FAIL_V 0x00000001U 2605 #define EFUSE_SYS_PART2_FAIL_S 7 2606 2607 /** EFUSE_CLK_REG register 2608 * eFuse clcok configuration register. 2609 */ 2610 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) 2611 /** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; 2612 * Set this bit to force eFuse SRAM into power-saving mode. 2613 */ 2614 #define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) 2615 #define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) 2616 #define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001U 2617 #define EFUSE_EFUSE_MEM_FORCE_PD_S 0 2618 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; 2619 * Set this bit and force to activate clock signal of eFuse SRAM. 2620 */ 2621 #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) 2622 #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) 2623 #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U 2624 #define EFUSE_MEM_CLK_FORCE_ON_S 1 2625 /** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; 2626 * Set this bit to force eFuse SRAM into working mode. 2627 */ 2628 #define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) 2629 #define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) 2630 #define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001U 2631 #define EFUSE_EFUSE_MEM_FORCE_PU_S 2 2632 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; 2633 * Set this bit and force to enable clock signal of eFuse memory. 2634 */ 2635 #define EFUSE_CLK_EN (BIT(16)) 2636 #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) 2637 #define EFUSE_CLK_EN_V 0x00000001U 2638 #define EFUSE_CLK_EN_S 16 2639 2640 /** EFUSE_CONF_REG register 2641 * eFuse operation mode configuraiton register 2642 */ 2643 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) 2644 /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; 2645 * 0x5A5A: Operate programming command 0x5AA5: Operate read command. 2646 */ 2647 #define EFUSE_OP_CODE 0x0000FFFFU 2648 #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) 2649 #define EFUSE_OP_CODE_V 0x0000FFFFU 2650 #define EFUSE_OP_CODE_S 0 2651 2652 /** EFUSE_STATUS_REG register 2653 * eFuse status register. 2654 */ 2655 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) 2656 /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; 2657 * Indicates the state of the eFuse state machine. 2658 */ 2659 #define EFUSE_STATE 0x0000000FU 2660 #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) 2661 #define EFUSE_STATE_V 0x0000000FU 2662 #define EFUSE_STATE_S 0 2663 /** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; 2664 * The value of OTP_LOAD_SW. 2665 */ 2666 #define EFUSE_OTP_LOAD_SW (BIT(4)) 2667 #define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) 2668 #define EFUSE_OTP_LOAD_SW_V 0x00000001U 2669 #define EFUSE_OTP_LOAD_SW_S 4 2670 /** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; 2671 * The value of OTP_VDDQ_C_SYNC2. 2672 */ 2673 #define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) 2674 #define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) 2675 #define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U 2676 #define EFUSE_OTP_VDDQ_C_SYNC2_S 5 2677 /** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; 2678 * The value of OTP_STROBE_SW. 2679 */ 2680 #define EFUSE_OTP_STROBE_SW (BIT(6)) 2681 #define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) 2682 #define EFUSE_OTP_STROBE_SW_V 0x00000001U 2683 #define EFUSE_OTP_STROBE_SW_S 6 2684 /** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; 2685 * The value of OTP_CSB_SW. 2686 */ 2687 #define EFUSE_OTP_CSB_SW (BIT(7)) 2688 #define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) 2689 #define EFUSE_OTP_CSB_SW_V 0x00000001U 2690 #define EFUSE_OTP_CSB_SW_S 7 2691 /** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; 2692 * The value of OTP_PGENB_SW. 2693 */ 2694 #define EFUSE_OTP_PGENB_SW (BIT(8)) 2695 #define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) 2696 #define EFUSE_OTP_PGENB_SW_V 0x00000001U 2697 #define EFUSE_OTP_PGENB_SW_S 8 2698 /** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; 2699 * The value of OTP_VDDQ_IS_SW. 2700 */ 2701 #define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) 2702 #define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) 2703 #define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U 2704 #define EFUSE_OTP_VDDQ_IS_SW_S 9 2705 /** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; 2706 * Indicates the number of error bits during programming BLOCK0. 2707 */ 2708 #define EFUSE_REPEAT_ERR_CNT 0x000000FFU 2709 #define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) 2710 #define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU 2711 #define EFUSE_REPEAT_ERR_CNT_S 10 2712 2713 /** EFUSE_CMD_REG register 2714 * eFuse command register. 2715 */ 2716 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) 2717 /** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0; 2718 * Set this bit to send read command. 2719 */ 2720 #define EFUSE_READ_CMD (BIT(0)) 2721 #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) 2722 #define EFUSE_READ_CMD_V 0x00000001U 2723 #define EFUSE_READ_CMD_S 0 2724 /** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0; 2725 * Set this bit to send programming command. 2726 */ 2727 #define EFUSE_PGM_CMD (BIT(1)) 2728 #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) 2729 #define EFUSE_PGM_CMD_V 0x00000001U 2730 #define EFUSE_PGM_CMD_S 1 2731 /** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; 2732 * The serial number of the block to be programmed. Value 0-10 corresponds to block 2733 * number 0-10, respectively. 2734 */ 2735 #define EFUSE_BLK_NUM 0x0000000FU 2736 #define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) 2737 #define EFUSE_BLK_NUM_V 0x0000000FU 2738 #define EFUSE_BLK_NUM_S 2 2739 2740 /** EFUSE_INT_RAW_REG register 2741 * eFuse raw interrupt register. 2742 */ 2743 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) 2744 /** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0; 2745 * The raw bit signal for read_done interrupt. 2746 */ 2747 #define EFUSE_READ_DONE_INT_RAW (BIT(0)) 2748 #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) 2749 #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U 2750 #define EFUSE_READ_DONE_INT_RAW_S 0 2751 /** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0; 2752 * The raw bit signal for pgm_done interrupt. 2753 */ 2754 #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) 2755 #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) 2756 #define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U 2757 #define EFUSE_PGM_DONE_INT_RAW_S 1 2758 2759 /** EFUSE_INT_ST_REG register 2760 * eFuse interrupt status register. 2761 */ 2762 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) 2763 /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; 2764 * The status signal for read_done interrupt. 2765 */ 2766 #define EFUSE_READ_DONE_INT_ST (BIT(0)) 2767 #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) 2768 #define EFUSE_READ_DONE_INT_ST_V 0x00000001U 2769 #define EFUSE_READ_DONE_INT_ST_S 0 2770 /** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; 2771 * The status signal for pgm_done interrupt. 2772 */ 2773 #define EFUSE_PGM_DONE_INT_ST (BIT(1)) 2774 #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) 2775 #define EFUSE_PGM_DONE_INT_ST_V 0x00000001U 2776 #define EFUSE_PGM_DONE_INT_ST_S 1 2777 2778 /** EFUSE_INT_ENA_REG register 2779 * eFuse interrupt enable register. 2780 */ 2781 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) 2782 /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; 2783 * The enable signal for read_done interrupt. 2784 */ 2785 #define EFUSE_READ_DONE_INT_ENA (BIT(0)) 2786 #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) 2787 #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U 2788 #define EFUSE_READ_DONE_INT_ENA_S 0 2789 /** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; 2790 * The enable signal for pgm_done interrupt. 2791 */ 2792 #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) 2793 #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) 2794 #define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U 2795 #define EFUSE_PGM_DONE_INT_ENA_S 1 2796 2797 /** EFUSE_INT_CLR_REG register 2798 * eFuse interrupt clear register. 2799 */ 2800 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) 2801 /** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; 2802 * The clear signal for read_done interrupt. 2803 */ 2804 #define EFUSE_READ_DONE_INT_CLR (BIT(0)) 2805 #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) 2806 #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U 2807 #define EFUSE_READ_DONE_INT_CLR_S 0 2808 /** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; 2809 * The clear signal for pgm_done interrupt. 2810 */ 2811 #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) 2812 #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) 2813 #define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U 2814 #define EFUSE_PGM_DONE_INT_CLR_S 1 2815 2816 /** EFUSE_DAC_CONF_REG register 2817 * Controls the eFuse programming voltage. 2818 */ 2819 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) 2820 /** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; 2821 * Controls the division factor of the rising clock of the programming voltage. 2822 */ 2823 #define EFUSE_DAC_CLK_DIV 0x000000FFU 2824 #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) 2825 #define EFUSE_DAC_CLK_DIV_V 0x000000FFU 2826 #define EFUSE_DAC_CLK_DIV_S 0 2827 /** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; 2828 * Don't care. 2829 */ 2830 #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) 2831 #define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) 2832 #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U 2833 #define EFUSE_DAC_CLK_PAD_SEL_S 8 2834 /** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; 2835 * Controls the rising period of the programming voltage. 2836 */ 2837 #define EFUSE_DAC_NUM 0x000000FFU 2838 #define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) 2839 #define EFUSE_DAC_NUM_V 0x000000FFU 2840 #define EFUSE_DAC_NUM_S 9 2841 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; 2842 * Reduces the power supply of the programming voltage. 2843 */ 2844 #define EFUSE_OE_CLR (BIT(17)) 2845 #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) 2846 #define EFUSE_OE_CLR_V 0x00000001U 2847 #define EFUSE_OE_CLR_S 17 2848 2849 /** EFUSE_RD_TIM_CONF_REG register 2850 * Configures read timing parameters. 2851 */ 2852 #define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) 2853 /** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; 2854 * Configures the initial read time of eFuse. 2855 */ 2856 #define EFUSE_READ_INIT_NUM 0x000000FFU 2857 #define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) 2858 #define EFUSE_READ_INIT_NUM_V 0x000000FFU 2859 #define EFUSE_READ_INIT_NUM_S 24 2860 2861 /** EFUSE_WR_TIM_CONF1_REG register 2862 * Configurarion register 1 of eFuse programming timing parameters. 2863 */ 2864 #define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) 2865 /** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; 2866 * Configures the power up time for VDDQ. 2867 */ 2868 #define EFUSE_PWR_ON_NUM 0x0000FFFFU 2869 #define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) 2870 #define EFUSE_PWR_ON_NUM_V 0x0000FFFFU 2871 #define EFUSE_PWR_ON_NUM_S 8 2872 2873 /** EFUSE_WR_TIM_CONF2_REG register 2874 * Configurarion register 2 of eFuse programming timing parameters. 2875 */ 2876 #define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) 2877 /** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; 2878 * Configures the power outage time for VDDQ. 2879 */ 2880 #define EFUSE_PWR_OFF_NUM 0x0000FFFFU 2881 #define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) 2882 #define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU 2883 #define EFUSE_PWR_OFF_NUM_S 0 2884 2885 /** EFUSE_DATE_REG register 2886 * eFuse version register. 2887 */ 2888 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) 2889 /** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34607760; 2890 * Stores eFuse version. 2891 */ 2892 #define EFUSE_DATE 0x0FFFFFFFU 2893 #define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) 2894 #define EFUSE_DATE_V 0x0FFFFFFFU 2895 #define EFUSE_DATE_S 0 2896 2897 #ifdef __cplusplus 2898 } 2899 #endif 2900
