1 /** 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** ECC_MULT_INT_RAW_REG register 15 * ECC interrupt raw register, valid in level. 16 */ 17 #define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc) 18 /** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; 19 * The raw interrupt status bit for the ecc_calc_done_int interrupt 20 */ 21 #define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) 22 #define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) 23 #define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U 24 #define ECC_MULT_CALC_DONE_INT_RAW_S 0 25 26 /** ECC_MULT_INT_ST_REG register 27 * ECC interrupt status register. 28 */ 29 #define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) 30 /** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; 31 * The masked interrupt status bit for the ecc_calc_done_int interrupt 32 */ 33 #define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) 34 #define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) 35 #define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U 36 #define ECC_MULT_CALC_DONE_INT_ST_S 0 37 38 /** ECC_MULT_INT_ENA_REG register 39 * ECC interrupt enable register. 40 */ 41 #define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) 42 /** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; 43 * The interrupt enable bit for the ecc_calc_done_int interrupt 44 */ 45 #define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) 46 #define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) 47 #define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U 48 #define ECC_MULT_CALC_DONE_INT_ENA_S 0 49 50 /** ECC_MULT_INT_CLR_REG register 51 * ECC interrupt clear register. 52 */ 53 #define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) 54 /** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; 55 * Set this bit to clear the ecc_calc_done_int interrupt 56 */ 57 #define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) 58 #define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) 59 #define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U 60 #define ECC_MULT_CALC_DONE_INT_CLR_S 0 61 62 /** ECC_MULT_CONF_REG register 63 * ECC configure register 64 */ 65 #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) 66 /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; 67 * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after 68 * the caculatrion is done. 69 */ 70 #define ECC_MULT_START (BIT(0)) 71 #define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) 72 #define ECC_MULT_START_V 0x00000001U 73 #define ECC_MULT_START_S 0 74 /** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; 75 * Write 1 to reset ECC Accelerator. 76 */ 77 #define ECC_MULT_RESET (BIT(1)) 78 #define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) 79 #define ECC_MULT_RESET_V 0x00000001U 80 #define ECC_MULT_RESET_S 1 81 /** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; 82 * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. 83 */ 84 #define ECC_MULT_KEY_LENGTH (BIT(2)) 85 #define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) 86 #define ECC_MULT_KEY_LENGTH_V 0x00000001U 87 #define ECC_MULT_KEY_LENGTH_S 2 88 /** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0; 89 * The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 90 * 1: p(mod base of curve) 91 */ 92 #define ECC_MULT_MOD_BASE (BIT(3)) 93 #define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S) 94 #define ECC_MULT_MOD_BASE_V 0x00000001U 95 #define ECC_MULT_MOD_BASE_S 3 96 /** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0; 97 * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point 98 * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point 99 * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 100 * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. 101 */ 102 #define ECC_MULT_WORK_MODE 0x0000000FU 103 #define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) 104 #define ECC_MULT_WORK_MODE_V 0x0000000FU 105 #define ECC_MULT_WORK_MODE_S 4 106 /** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0; 107 * Reserved 108 */ 109 #define ECC_MULT_SECURITY_MODE (BIT(8)) 110 #define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) 111 #define ECC_MULT_SECURITY_MODE_V 0x00000001U 112 #define ECC_MULT_SECURITY_MODE_S 8 113 /** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0; 114 * The verification result bit of ECC Accelerator, only valid when calculation is done. 115 */ 116 #define ECC_MULT_VERIFICATION_RESULT (BIT(29)) 117 #define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) 118 #define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U 119 #define ECC_MULT_VERIFICATION_RESULT_S 29 120 /** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0; 121 * Write 1 to force on register clock gate. 122 */ 123 #define ECC_MULT_CLK_EN (BIT(30)) 124 #define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) 125 #define ECC_MULT_CLK_EN_V 0x00000001U 126 #define ECC_MULT_CLK_EN_S 30 127 /** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1; 128 * ECC memory clock gate force on register 129 */ 130 #define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) 131 #define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) 132 #define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U 133 #define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31 134 135 /** ECC_MULT_DATE_REG register 136 * Version control register 137 */ 138 #define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) 139 /** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35680640; 140 * ECC mult version control register 141 */ 142 #define ECC_MULT_DATE 0x0FFFFFFFU 143 #define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S) 144 #define ECC_MULT_DATE_V 0x0FFFFFFFU 145 #define ECC_MULT_DATE_S 0 146 147 /** ECC_MULT_K_MEM register 148 * The memory that stores k. 149 */ 150 #define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100) 151 #define ECC_MULT_K_MEM_SIZE_BYTES 32 152 153 /** ECC_MULT_PX_MEM register 154 * The memory that stores Px. 155 */ 156 #define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120) 157 #define ECC_MULT_PX_MEM_SIZE_BYTES 32 158 159 /** ECC_MULT_PY_MEM register 160 * The memory that stores Py. 161 */ 162 #define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) 163 #define ECC_MULT_PY_MEM_SIZE_BYTES 32 164 165 /** ECC_MULT_QX_MEM register 166 * The memory that stores Qx. 167 */ 168 #define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160) 169 #define ECC_MULT_QX_MEM_SIZE_BYTES 32 170 171 /** ECC_MULT_QY_MEM register 172 * The memory that stores Qy. 173 */ 174 #define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180) 175 #define ECC_MULT_QY_MEM_SIZE_BYTES 32 176 177 /** ECC_MULT_QZ_MEM register 178 * The memory that stores Qz. 179 */ 180 #define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0) 181 #define ECC_MULT_QZ_MEM_SIZE_BYTES 32 182 183 #ifdef __cplusplus 184 } 185 #endif 186
