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Searched refs:DR_REG_TRACE_BASE (Results 1 – 4 of 4) sorted by relevance

/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dtrace_reg.h17 #define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
29 #define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
41 #define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
53 #define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
65 #define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
84 #define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
103 #define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
122 #define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
141 #define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
176 #define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
[all …]
Dreg_base.h66 #define DR_REG_TRACE_BASE 0x600C0000 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dtrace_reg.h17 #define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
29 #define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
41 #define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
53 #define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
65 #define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
84 #define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
103 #define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
122 #define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
141 #define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
176 #define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
[all …]
Dreg_base.h76 #define DR_REG_TRACE_BASE 0x600C0000 macro