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Searched refs:DR_REG_TEE_BASE (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dtee_reg.h17 #define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
30 #define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
43 #define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
56 #define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
69 #define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
82 #define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
95 #define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
108 #define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
121 #define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
134 #define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
[all …]
Dreg_base.h53 #define DR_REG_TEE_BASE 0x60098000 macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dtee_reg.h17 #define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
30 #define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
43 #define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
56 #define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
69 #define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
82 #define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
95 #define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
108 #define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
121 #define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
134 #define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
[all …]
Dreg_base.h48 #define DR_REG_TEE_BASE 0x60098000 macro
/hal_espressif-latest/components/esp_hw_support/
Dsleep_system_peripheral.c67 #define N_REGS_TEE() (((TEE_CLOCK_GATE_REG - DR_REG_TEE_BASE) / 4) + 1) in sleep_sys_periph_tee_apm_retention_init()
72 …onfig = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(1), DR_REG_TEE_BASE, DR_REG_TEE_BASE, … in sleep_sys_periph_tee_apm_retention_init()