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Searched refs:DR_REG_SYSTEM_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dsystem_reg.h16 #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0)
35 #define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4)
54 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8)
88 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xc)
100 #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x10)
182 #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x14)
215 #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x18)
297 #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x1c)
330 #define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x20)
342 #define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x24)
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Dreg_base.h6 #define DR_REG_SYSTEM_BASE 0x600c0000 macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dsystem_reg.h14 #define DPORT_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000)
22 #define DPORT_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004)
36 #define DPORT_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008)
44 #define DPORT_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C)
53 #define DPORT_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x010)
71 #define DPORT_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x014)
85 #define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018)
111 #define DPORT_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x01C)
119 #define DPORT_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x020)
127 #define DPORT_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x024)
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Dreg_base.h6 #define DR_REG_SYSTEM_BASE 0x3f4c0000 macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dsystem_reg.h22 #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000)
36 #define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x004)
50 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x008)
76 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C)
84 #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x010)
278 #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x014)
340 #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x018)
534 #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x01C)
596 #define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x020)
604 #define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024)
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Dreg_base.h6 #define DR_REG_SYSTEM_BASE 0x600c0000 macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dsystem_reg.h23 #define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0)
43 #define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x4)
51 #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x8)
65 #define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0xC)
79 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x10)
105 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x14)
113 #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18)
307 #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C)
375 #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20)
569 #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x24)
[all …]
Dreg_base.h59 #define DR_REG_SYSTEM_BASE 0x600C0000 macro